// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
// Netlist written on Fri Jan 05 14:24:49 2024
//
// Verilog Description of module prox_detect
//

module prox_detect (clk, rst_n, i2c_scl, i2c_sda, seg_rck, seg_sck, 
            seg_din, led) /* synthesis syn_module_defined=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(18[8:19])
    input clk;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(19[12:15])
    input rst_n;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(20[12:17])
    output i2c_scl;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(22[12:19])
    inout i2c_sda;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(23[12:19])
    output seg_rck;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(24[12:19])
    output seg_sck;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(25[12:19])
    output seg_din;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(26[12:19])
    output [7:0]led;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(19[12:15])
    wire dat_valid /* synthesis is_clock=1, SET_AS_NETWORK=dat_valid */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(31[6:15])
    wire clk_400khz /* synthesis is_clock=1, SET_AS_NETWORK=\u1/clk_400khz */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(47[10:20])
    
    wire GND_net, VCC_net, rst_n_c, i2c_scl_c, seg_rck_c, seg_sck_c, 
        seg_din_c, led_c_7, led_c_5, led_c_4, led_c_3, led_c_2, 
        led_c_1;
    wire [15:0]ch0_dat;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(32[13:20])
    wire [15:0]ch1_dat;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(32[22:29])
    wire [15:0]prox_dat;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(32[31:39])
    wire [31:0]lux_data;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(33[13:21])
    
    wire ack_flag;
    wire [3:0]cnt_main;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[17:25])
    wire [3:0]cnt_mode1;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[27:36])
    wire [3:0]cnt_mode2;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[38:47])
    wire [3:0]cnt_start;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[49:58])
    wire [3:0]cnt_write;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[60:69])
    wire [3:0]cnt_read;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[71:79])
    wire [3:0]state;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    wire [3:0]state_back;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[20:30])
    
    wire n110489, n110467, dat_valid_N_458, n110994, n110993, n1961, 
        n324, n110513, n5022, n21676, n2359, i2c_sda_N_471, n481, 
        clk_c_enable_149, n110987, clk_c_enable_65, n83242, i2c_sda_N_454, 
        n6358, n6354, n16300;
    wire [31:0]lux;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(53[12:15])
    wire [41:0]lux_31__N_576;
    
    wire lux_31__N_575;
    wire [42:0]lux_31__N_625;
    wire [42:0]lux_31__N_657;
    wire [31:0]lux_31__N_543;
    wire [41:0]lux_31__N_754;
    
    wire lux_31__N_753, n15168, n15169, n15170, n15171, n15172, 
        n15173, n15174, n15175, n15176, n15177, n15178, n15179, 
        n15180, n15181, n15182, n15183, n15184, n15185, n15186, 
        n15187, n486, n109587, n15065, n15066, n15068, n15069, 
        n15070, n15072, n15073, n15074, n15075, n15076, n15077, 
        n110980, n110979, n4;
    wire [31:0]lux_31__N_511;
    
    wire n14, n110972, n109724, n110952, n110966, bcd_code_31__N_842, 
        bcd_code_31__N_846, n6295, bcd_code_31__N_841, bcd_code_31__N_860, 
        bcd_code_31__N_864, n110965, n6291, bcd_code_31__N_859, bcd_code_31__N_887, 
        bcd_code_31__N_891, bcd_code_31__N_851, bcd_code_31__N_855, bcd_code_31__N_886, 
        bcd_code_31__N_914, bcd_code_31__N_918, bcd_code_31__N_850, bcd_code_31__N_913, 
        bcd_code_31__N_952, bcd_code_31__N_956, n6268, n6264, bcd_code_31__N_951, 
        bcd_code_31__N_988, bcd_code_31__N_992, bcd_code_31__N_896, bcd_code_31__N_900, 
        bcd_code_31__N_987, bcd_code_31__N_1030, bcd_code_31__N_1034, 
        bcd_code_31__N_895, n109347, bcd_code_31__N_1029, bcd_code_31__N_1079, 
        bcd_code_31__N_1083, bcd_code_31__N_1078, bcd_code_31__N_1130, 
        bcd_code_31__N_1134, bcd_code_31__N_961, bcd_code_31__N_965, bcd_code_31__N_1129, 
        bcd_code_31__N_1181, bcd_code_31__N_1185, bcd_code_31__N_960, 
        bcd_code_31__N_1180, bcd_code_31__N_1247, bcd_code_31__N_1251, 
        n110958, clk_c_enable_99, bcd_code_31__N_1246, bcd_code_31__N_1307, 
        bcd_code_31__N_1311, bcd_code_31__N_1043, bcd_code_31__N_1047, 
        bcd_code_31__N_1306, bcd_code_31__N_1367, bcd_code_31__N_1371, 
        bcd_code_31__N_1042, bcd_code_31__N_1366, bcd_code_31__N_1451, 
        bcd_code_31__N_1455, n83413, bcd_code_31__N_1450, bcd_code_31__N_1520, 
        bcd_code_31__N_1524, bcd_code_31__N_798, bcd_code_31__N_1140, 
        bcd_code_31__N_1519, bcd_code_31__N_1589, bcd_code_31__N_1593, 
        n6059, bcd_code_31__N_797, bcd_code_31__N_1588, bcd_code_31__N_1691, 
        bcd_code_31__N_1695, n110463, bcd_code_31__N_1690, bcd_code_31__N_1769, 
        bcd_code_31__N_1773, n6021, bcd_code_31__N_1257, bcd_code_31__N_795, 
        bcd_code_31__N_1768, bcd_code_31__N_1845, bcd_code_31__N_1849, 
        n5988, bcd_code_31__N_1384, bcd_code_31__N_1844, bcd_code_31__N_1914, 
        bcd_code_31__N_1918, n5956, n5948;
    wire [3:0]bcd_code_31__N_1380;
    
    wire bcd_code_31__N_1913, bcd_code_31__N_1974, bcd_code_31__N_1978, 
        i2c_sda_out, n5916, bcd_code_31__N_1392, bcd_code_31__N_1394, 
        bcd_code_31__N_1973, bcd_code_31__N_2025, bcd_code_31__N_2029, 
        n5883, bcd_code_31__N_2024, bcd_code_31__N_2067, bcd_code_31__N_2071, 
        n5845, bcd_code_31__N_2066, bcd_code_31__N_2100, bcd_code_31__N_2104, 
        bcd_code_31__N_2099, bcd_code_31__N_2124, bcd_code_31__N_2128, 
        n5804, bcd_code_31__N_2123, bcd_code_31__N_2139, bcd_code_31__N_2143, 
        bcd_code_31__N_2145, bcd_code_31__N_2138, n5740, n14_adj_2755, 
        n14_adj_2756, n14_adj_2757, n110944, n110943, n14_adj_2758, 
        n14_adj_2759, n14_adj_2760, n14_adj_2761, n14_adj_2762, n7, 
        n14_adj_2763, n7_adj_2764, n14_adj_2765, n14_adj_2766, n7_adj_2767, 
        n14_adj_2768, n14_adj_2769, n110936, n14_adj_2770, n7_adj_2771, 
        n14_adj_2772, n14_adj_2773, n110930, n7_adj_2774, n110929, 
        n14_adj_2775, n14_adj_2776, n14_adj_2777, n14_adj_2778, n14_adj_2779, 
        n14_adj_2780, n7_adj_2781, n14_adj_2782, n110921, clk_c_enable_100, 
        n7_adj_2783, n14_adj_2784, n14_adj_2785, n7_adj_2786, n14_adj_2787, 
        n7_adj_2788, n110913, n14_adj_2789, n14_adj_2790, n7_adj_2791, 
        n14_adj_2792, n14_adj_2793, n14_adj_2794, n14_adj_2795, n7_adj_2796, 
        n14_adj_2797, n7_adj_2798, n14_adj_2799, n14_adj_2800, n110905, 
        n14_adj_2801, n14_adj_2802, n7_adj_2803, n14_adj_2804, n110902, 
        n14_adj_2805, n7_adj_2806, n14_adj_2807, n14_adj_2808, n2356, 
        n2353, n5701, n5695, n5660, n5653, n5621, n24, n30, 
        n24_adj_2809, n67, n2350, n22, n22070, n5548, n16550, 
        n2285, n110508, n2281, n1991, n1990, n1989, n110893, n1985, 
        n1984, n5502, n1971, n4_adj_2810, n110482, n24_adj_2811, 
        n45, n5470, n5465, n5433, n5401, n5369, n5329, n5292, 
        n5260, n5225, n5181, n5141, n110885, n110391, n110884, 
        n110385, n110481, n110876, n110868, n110858, n110507, n110506, 
        n4_adj_2812, n5, n6, n8, n10, n12, n14_adj_2813, n16, 
        n18, n20, n22_adj_2814, n24_adj_2815, n26, n28, n30_adj_2816, 
        n10_adj_2817, n11, n12_adj_2818, n14_adj_2819, n16_adj_2820, 
        n18_adj_2821, n20_adj_2822, n22_adj_2823, n24_adj_2824, n26_adj_2825, 
        n28_adj_2826, n30_adj_2827, n4_adj_2828, n6_adj_2829, n8_adj_2830, 
        n10_adj_2831, n12_adj_2832, n13, n14_adj_2833, n16_adj_2834, 
        n18_adj_2835, n20_adj_2836, n22_adj_2837, n24_adj_2838, n26_adj_2839, 
        n28_adj_2840, n109806, n30_adj_2841, n109219, n6_adj_2842, 
        n8_adj_2843, n10_adj_2844, n12_adj_2845, n13_adj_2846, n14_adj_2847, 
        n16_adj_2848, n18_adj_2849, n20_adj_2850, n22_adj_2851, n24_adj_2852, 
        n26_adj_2853, n28_adj_2854, n109801, n30_adj_2855, n15273, 
        n22079, n110505, n110504, n110850, n4_adj_2856, n110503, 
        n109187, n110487, n110840, n110480, n22821, n110478, clk_c_enable_126, 
        n20_adj_2857, n110817, clk_c_enable_120, n110289, n16738, 
        n16726, n16700, n110285, n110284, n110282, n110281, n110279, 
        n110278, n110276, n110275, n16625, n110273, n16601, n16584, 
        n110272, n110270, n110269, n16565, n16558, n110806, n16541, 
        n16471, n16456, n110486, n111990, n16428, n110592, n110591, 
        n16351, n17, n22026, n110497, n107675, n107670, n107668, 
        n107666, n107664, n107662, n111256, n111254, n111249, n111243, 
        n111237, n111228, n111224, n111222, n111220, n111219, n111217, 
        n109824, n111213, n111212, n111209, n15, n111208, n111207, 
        n110476, n109371, n15_adj_2858, n14_adj_2859, n110582, n111204, 
        n111203, n14_adj_2860, n110581, n111202, n109229, n111201, 
        n110580, n110475, n109366, n111200, n111198, n111197, n9, 
        n111196, n109023, n111195, n111194, n111193, n109362, n111192, 
        n111191, n111190, n110578, n111189, n110788, n111188, n83327, 
        n111187, n111186, clk_c_enable_124, n111184, n111183, n111182, 
        n109352, n111180, n111179, n111178, n111177, n111176, n22_adj_2861, 
        n109269, n109208, n109339, n111175, n111173, n111172, n20_adj_2862, 
        n111171, n111170, n111169, n111167, n109334, n111166, n111165, 
        n111164, n111163, n111162, n83319, n111161, n110568, n111160, 
        n110496, n83313, n111159, n110495, n111158, n109768, n111157, 
        n83307, n83303, n111156, n83295, n111155, n23, n110567, 
        n111154, n111153, n111152, n111151, n110566, n12_adj_2863, 
        n14_adj_2864, n23_adj_2865, n110494, n109589, n109588, n110493, 
        n110559, n9_adj_2866, n109792, n109566, n110558, n110557, 
        n109794, n109562, n111115, n110556, n111114, n111113, n109558, 
        n109798, n109556, n4_adj_2867, n109549, n111110, n109545, 
        n111109, n109803, n109541, n110485, n111108, n109536, n111107, 
        n4_adj_2868, n110484, n109525, n109522, clk_c_enable_111, 
        n109512, n111102, n110547, n111101, n110546, n110545, n109501, 
        n111098, n111097, n109492, n109488, n111092, n18_adj_2869, 
        n15_adj_2870, n3, n109808, n109484, n4_adj_2871, n109479, 
        n111089, n111088, n110721, n110720, n109468, n8_adj_2872, 
        n109465, n109455, n40, n111082, n25, n110536, n111081, 
        n111080, n110535, n109214, n110534, n109444, n111075, n111074, 
        n110533, n110532, n109810, n109435, n111067, n109433, n111066, 
        n109430, n110701, n110530, n109416, n111059, n20_adj_2873, 
        n109411, n109760, n111058, n109408, n110524, n109217, n111050, 
        n111049, clk_c_enable_106, n111259, n110523, n111044, n23_adj_2874, 
        n109398, n111258, n110522, n110126, n111037, n111036, n110521, 
        n110520, n17_adj_2875, n109388, n45_adj_2876, n107610, n109790, 
        n110491, n110490, n111031, n109324, n57, n19, n81716, 
        n111026, n111025, n81685, n109184, n111016, n111015, n109384, 
        n83415, n64, n111006, n111005, n110515, n45_adj_2877, n110514;
    
    VHI i102560 (.Z(VCC_net));
    BB i2c_sda_pad (.I(i2c_sda_N_454), .T(n15273), .B(i2c_sda), .O(i2c_sda_out));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(70[2] 217[5])
    LUT4 i11465_3_lut_4_lut (.A(n5292), .B(lux[4]), .C(lux[3]), .D(n5181), 
         .Z(bcd_code_31__N_2128)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11465_3_lut_4_lut.init = 16'h6966;
    OB i2c_scl_pad (.I(i2c_scl_c), .O(i2c_scl));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(22[12:19])
    OB seg_rck_pad (.I(seg_rck_c), .O(seg_rck));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(24[12:19])
    OB seg_sck_pad (.I(seg_sck_c), .O(seg_sck));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(25[12:19])
    OB seg_din_pad (.I(seg_din_c), .O(seg_din));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(26[12:19])
    OB led_pad_7 (.I(led_c_7), .O(led[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_6 (.I(n111222), .O(led[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_5 (.I(led_c_5), .O(led[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_4 (.I(led_c_4), .O(led[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_3 (.I(led_c_3), .O(led[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_2 (.I(led_c_2), .O(led[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_1 (.I(led_c_1), .O(led[1]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    OB led_pad_0 (.I(GND_net), .O(led[0]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(28[16:19])
    IB clk_pad (.I(clk), .O(clk_c));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(19[12:15])
    IB rst_n_pad (.I(rst_n), .O(rst_n_c));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(20[12:17])
    GSR GSR_INST (.GSR(rst_n_c));
    L6MUX21 LessThan_1516_i32 (.D0(n26_adj_2839), .D1(n30_adj_2841), .SD(n109492), 
            .Z(n2353));
    L6MUX21 LessThan_1522_i32 (.D0(n24_adj_2815), .D1(n30_adj_2816), .SD(n109384), 
            .Z(n2359));
    L6MUX21 LessThan_1513_i32 (.D0(n26_adj_2853), .D1(n30_adj_2855), .SD(n109549), 
            .Z(n2350));
    PFUMX LessThan_1516_i30 (.BLUT(n14_adj_2833), .ALUT(n28_adj_2840), .C0(n109562), 
          .Z(n30_adj_2841));
    PFUMX LessThan_1516_i26 (.BLUT(n18_adj_2835), .ALUT(n24_adj_2838), .C0(n109484), 
          .Z(n26_adj_2839));
    PFUMX LessThan_1522_i30 (.BLUT(n12), .ALUT(n28), .C0(n109558), .Z(n30_adj_2816));
    LUT4 i11475_3_lut_4_lut (.A(n110884), .B(lux[4]), .C(n5292), .D(bcd_code_31__N_2071), 
         .Z(bcd_code_31__N_2100)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11475_3_lut_4_lut.init = 16'h1fe0;
    L6MUX21 mux_1177_i1 (.D0(n1971), .D1(n1985), .SD(n109324), .Z(n1991));
    PFUMX mux_1177_i2 (.BLUT(n81716), .ALUT(n1984), .C0(n109556), .Z(n1990));
    LUT4 i101891_4_lut (.A(n2285), .B(n111180), .C(n2281), .D(state[2]), 
         .Z(n109324)) /* synthesis lut_function=(A+!(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101891_4_lut.init = 16'haaea;
    LUT4 i1_4_lut_then_4_lut (.A(n24_adj_2809), .B(state[1]), .C(state[0]), 
         .D(n111203), .Z(n111259)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i1_4_lut_then_4_lut.init = 16'h0aca;
    LUT4 i74263_4_lut_4_lut (.A(cnt_main[1]), .B(cnt_main[0]), .C(cnt_main[2]), 
         .D(dat_valid_N_458), .Z(n4_adj_2856)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A (B+((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(25[17:26])
    defparam i74263_4_lut_4_lut.init = 16'h0810;
    LUT4 i101870_4_lut (.A(n2285), .B(n111180), .C(n45_adj_2876), .D(state[0]), 
         .Z(n109556)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101870_4_lut.init = 16'hfeff;
    PFUMX LessThan_1522_i24 (.BLUT(n16), .ALUT(n22_adj_2814), .C0(n109371), 
          .Z(n24_adj_2815));
    PFUMX mux_1165_i1 (.BLUT(n109023), .ALUT(n1961), .C0(n3), .Z(n1971));
    LUT4 i101841_4_lut (.A(n111160), .B(n111167), .C(n111166), .D(n109352), 
         .Z(n109768)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101841_4_lut.init = 16'hefee;
    LUT4 state_2__bdd_4_lut (.A(state[2]), .B(n24_adj_2809), .C(n22), 
         .D(state[0]), .Z(n24)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam state_2__bdd_4_lut.init = 16'hf088;
    LUT4 i20_3_lut (.A(cnt_main[2]), .B(cnt_main[1]), .C(dat_valid_N_458), 
         .Z(n9_adj_2866)) /* synthesis lut_function=(!(A (C)+!A (B+!(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(25[17:26])
    defparam i20_3_lut.init = 16'h1a1a;
    LUT4 i101863_4_lut (.A(n109545), .B(n111176), .C(n111182), .D(n13_adj_2846), 
         .Z(n109790)) /* synthesis lut_function=(!(A (B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101863_4_lut.init = 16'h5557;
    PFUMX LessThan_1513_i30 (.BLUT(n14_adj_2847), .ALUT(n28_adj_2854), .C0(n109566), 
          .Z(n30_adj_2855));
    LUT4 i10_4_lut (.A(n15), .B(n20_adj_2873), .C(lux_31__N_754[18]), 
         .D(lux_31__N_754[16]), .Z(lux_31__N_753)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i10_4_lut.init = 16'hfffe;
    LUT4 i101874_4_lut (.A(n111164), .B(n111172), .C(n111171), .D(n109522), 
         .Z(n109801)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101874_4_lut.init = 16'hefee;
    LUT4 i4_2_lut (.A(lux_31__N_754[21]), .B(lux_31__N_754[22]), .Z(n15)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i4_2_lut.init = 16'heeee;
    LUT4 i9_4_lut (.A(n17_adj_2875), .B(lux_31__N_754[23]), .C(n14_adj_2860), 
         .D(lux_31__N_754[17]), .Z(n20_adj_2873)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i6_3_lut (.A(lux_31__N_754[19]), .B(n2353), .C(lux_31__N_754[24]), 
         .Z(n17_adj_2875)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i6_3_lut.init = 16'hfefe;
    LUT4 i3_2_lut (.A(lux_31__N_754[25]), .B(lux_31__N_754[20]), .Z(n14_adj_2860)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3_2_lut.init = 16'heeee;
    PFUMX LessThan_1513_i26 (.BLUT(n18_adj_2849), .ALUT(n24_adj_2852), .C0(n109541), 
          .Z(n26_adj_2853));
    LUT4 i101883_4_lut (.A(n111188), .B(n111194), .C(n111193), .D(n109411), 
         .Z(n109810)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101883_4_lut.init = 16'hfeff;
    LUT4 i101323_4_lut (.A(n111201), .B(n111200), .C(n111207), .D(n109398), 
         .Z(n109411)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101323_4_lut.init = 16'h5455;
    LUT4 i101310_4_lut (.A(n111208), .B(n111220), .C(n111219), .D(n11), 
         .Z(n109398)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101310_4_lut.init = 16'h5554;
    L6MUX21 LessThan_1519_i32 (.D0(n20_adj_2822), .D1(n30_adj_2827), .SD(n109433), 
            .Z(n2356));
    LUT4 LessThan_1519_i11_2_lut (.A(ch1_dat[5]), .B(lux_31__N_625[3]), 
         .Z(n11)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i11_2_lut.init = 16'h6666;
    LUT4 i75421_2_lut (.A(n2356), .B(n21676), .Z(n486)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i75421_2_lut.init = 16'heeee;
    LUT4 i10_4_lut_adj_252 (.A(n15_adj_2870), .B(n20_adj_2862), .C(n15179), 
         .D(n15187), .Z(n21676)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i10_4_lut_adj_252.init = 16'hfffe;
    LUT4 i4_2_lut_adj_253 (.A(n15185), .B(n15184), .Z(n15_adj_2870)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i4_2_lut_adj_253.init = 16'heeee;
    LUT4 i9_4_lut_adj_254 (.A(n15186), .B(n18_adj_2869), .C(n15177), .D(n15181), 
         .Z(n20_adj_2862)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut_adj_254.init = 16'hfffe;
    LUT4 i7_4_lut (.A(n15183), .B(n15178), .C(n15182), .D(n15180), .Z(n18_adj_2869)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i7_4_lut.init = 16'hfffe;
    LUT4 i101881_4_lut (.A(n111188), .B(n111194), .C(n111193), .D(n109416), 
         .Z(n109808)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101881_4_lut.init = 16'hefee;
    LUT4 n7_bdd_4_lut (.A(n111203), .B(i2c_sda_N_471), .C(n4_adj_2810), 
         .D(state[1]), .Z(n110467)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A ((D)+!C))) */ ;
    defparam n7_bdd_4_lut.init = 16'h22f0;
    PFUMX LessThan_1519_i30 (.BLUT(n22_adj_2823), .ALUT(n28_adj_2826), .C0(n109435), 
          .Z(n30_adj_2827));
    LUT4 n6_bdd_4_lut (.A(n111213), .B(cnt_read[3]), .C(n110385), .D(state[1]), 
         .Z(n24_adj_2809)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A ((D)+!C))) */ ;
    defparam n6_bdd_4_lut.init = 16'h22f0;
    LUT4 i11617_4_lut (.A(bcd_code_31__N_1589), .B(n5956), .C(n110993), 
         .D(bcd_code_31__N_1593), .Z(bcd_code_31__N_1588)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11617_4_lut.init = 16'h6aaa;
    LUT4 i11503_4_lut (.A(bcd_code_31__N_1520), .B(n5470), .C(n111005), 
         .D(bcd_code_31__N_1524), .Z(bcd_code_31__N_1519)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11503_4_lut.init = 16'h6aaa;
    PFUMX mux_1175_i1 (.BLUT(n9), .ALUT(n324), .C0(n2285), .Z(n1985));
    LUT4 i11620_4_lut (.A(bcd_code_31__N_1451), .B(n5988), .C(n111015), 
         .D(bcd_code_31__N_1455), .Z(bcd_code_31__N_1450)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11620_4_lut.init = 16'h6aaa;
    LUT4 i11482_4_lut (.A(bcd_code_31__N_1367), .B(n5369), .C(n111025), 
         .D(bcd_code_31__N_1371), .Z(bcd_code_31__N_1366)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11482_4_lut.init = 16'h6aaa;
    LUT4 i11593_4_lut (.A(bcd_code_31__N_1307), .B(n5883), .C(n111036), 
         .D(bcd_code_31__N_1311), .Z(bcd_code_31__N_1306)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11593_4_lut.init = 16'h6aaa;
    LUT4 i11502_3_lut_4_lut (.A(n111006), .B(lux[12]), .C(n5470), .D(bcd_code_31__N_1524), 
         .Z(bcd_code_31__N_1589)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11502_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14055_2_lut_rep_947_3_lut (.A(n5988), .B(lux[13]), .C(lux[12]), 
         .Z(n111005)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14055_2_lut_rep_947_3_lut.init = 16'hf6f6;
    LUT4 i11501_3_lut_4_lut (.A(n5988), .B(lux[13]), .C(lux[12]), .D(n5470), 
         .Z(bcd_code_31__N_1593)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11501_3_lut_4_lut.init = 16'h6966;
    LUT4 i11470_4_lut (.A(bcd_code_31__N_1247), .B(n5225), .C(n111049), 
         .D(bcd_code_31__N_1251), .Z(bcd_code_31__N_1246)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11470_4_lut.init = 16'h6aaa;
    LUT4 i11485_4_lut (.A(bcd_code_31__N_1181), .B(n5401), .C(n111058), 
         .D(bcd_code_31__N_1185), .Z(bcd_code_31__N_1180)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11485_4_lut.init = 16'h6aaa;
    LUT4 i11566_4_lut (.A(bcd_code_31__N_1130), .B(n5740), .C(n111066), 
         .D(bcd_code_31__N_1134), .Z(bcd_code_31__N_1129)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11566_4_lut.init = 16'h6aaa;
    LUT4 i11590_4_lut (.A(bcd_code_31__N_1079), .B(n5845), .C(n111074), 
         .D(bcd_code_31__N_1083), .Z(bcd_code_31__N_1078)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11590_4_lut.init = 16'h6aaa;
    LUT4 i11596_4_lut (.A(bcd_code_31__N_1030), .B(n5916), .C(n111080), 
         .D(bcd_code_31__N_1034), .Z(bcd_code_31__N_1029)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11596_4_lut.init = 16'h6aaa;
    LUT4 i11623_4_lut (.A(bcd_code_31__N_988), .B(n6021), .C(n111088), 
         .D(bcd_code_31__N_992), .Z(bcd_code_31__N_987)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11623_4_lut.init = 16'h6aaa;
    LUT4 i11647_4_lut (.A(bcd_code_31__N_952), .B(n6059), .C(n111097), 
         .D(bcd_code_31__N_956), .Z(bcd_code_31__N_951)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11647_4_lut.init = 16'h6aaa;
    LUT4 i11619_3_lut_4_lut (.A(n111016), .B(lux[13]), .C(n5988), .D(bcd_code_31__N_1455), 
         .Z(bcd_code_31__N_1520)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11619_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14068_2_lut_rep_957_3_lut (.A(n5369), .B(lux[14]), .C(lux[13]), 
         .Z(n111015)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14068_2_lut_rep_957_3_lut.init = 16'hf6f6;
    LUT4 i11618_3_lut_4_lut (.A(n5369), .B(lux[14]), .C(lux[13]), .D(n5988), 
         .Z(bcd_code_31__N_1524)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11618_3_lut_4_lut.init = 16'h6966;
    LUT4 i11479_4_lut (.A(bcd_code_31__N_914), .B(n5329), .C(n111101), 
         .D(bcd_code_31__N_918), .Z(bcd_code_31__N_913)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11479_4_lut.init = 16'h6aaa;
    LUT4 i11488_4_lut (.A(bcd_code_31__N_887), .B(n5433), .C(n111107), 
         .D(bcd_code_31__N_891), .Z(bcd_code_31__N_886)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11488_4_lut.init = 16'h6aaa;
    PFUMX i101501 (.BLUT(n109587), .ALUT(n109588), .C0(state[1]), .Z(n109589));
    PFUMX LessThan_1519_i20 (.BLUT(n10_adj_2817), .ALUT(n18_adj_2821), .C0(n109408), 
          .Z(n20_adj_2822));
    LUT4 i11521_4_lut (.A(bcd_code_31__N_860), .B(n5548), .C(n111109), 
         .D(bcd_code_31__N_864), .Z(bcd_code_31__N_859)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11521_4_lut.init = 16'h6aaa;
    LUT4 i2_4_lut (.A(n111113), .B(n5465), .C(bcd_code_31__N_841), .Z(bcd_code_31__N_855)) /* synthesis lut_function=(A ((C)+!B)+!A !((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2_4_lut.init = 16'ha6a6;
    LUT4 i11481_3_lut_4_lut (.A(n111026), .B(lux[14]), .C(n5369), .D(bcd_code_31__N_1371), 
         .Z(bcd_code_31__N_1451)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11481_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14052_2_lut_rep_967_3_lut (.A(n5883), .B(lux[15]), .C(lux[14]), 
         .Z(n111025)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14052_2_lut_rep_967_3_lut.init = 16'hf6f6;
    LUT4 i11480_3_lut_4_lut (.A(n5883), .B(lux[15]), .C(lux[14]), .D(n5369), 
         .Z(bcd_code_31__N_1455)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11480_3_lut_4_lut.init = 16'h6966;
    LUT4 i11572_4_lut (.A(bcd_code_31__N_842), .B(n5804), .C(n111114), 
         .D(bcd_code_31__N_846), .Z(bcd_code_31__N_841)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11572_4_lut.init = 16'h6aaa;
    LUT4 i11592_3_lut_4_lut (.A(n111037), .B(lux[15]), .C(n5883), .D(bcd_code_31__N_1311), 
         .Z(bcd_code_31__N_1367)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11592_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14065_2_lut_rep_978_3_lut (.A(n5225), .B(lux[16]), .C(lux[15]), 
         .Z(n111036)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14065_2_lut_rep_978_3_lut.init = 16'hf6f6;
    LUT4 i11591_3_lut_4_lut (.A(n5225), .B(lux[16]), .C(lux[15]), .D(n5883), 
         .Z(bcd_code_31__N_1371)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11591_3_lut_4_lut.init = 16'h6966;
    LUT4 i1_4_lut_else_4_lut (.A(state[1]), .B(state[0]), .C(cnt_mode1[2]), 
         .D(cnt_mode1[3]), .Z(n111258)) /* synthesis lut_function=(A (B+!(C+(D)))) */ ;
    defparam i1_4_lut_else_4_lut.init = 16'h888a;
    LUT4 i11469_3_lut_4_lut (.A(n111050), .B(lux[16]), .C(n5225), .D(bcd_code_31__N_1251), 
         .Z(bcd_code_31__N_1307)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11469_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14048_2_lut_rep_991_3_lut (.A(n5401), .B(lux[17]), .C(lux[16]), 
         .Z(n111049)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14048_2_lut_rep_991_3_lut.init = 16'hf6f6;
    LUT4 i11468_3_lut_4_lut (.A(n5401), .B(lux[17]), .C(lux[16]), .D(n5225), 
         .Z(bcd_code_31__N_1311)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11468_3_lut_4_lut.init = 16'h6966;
    LUT4 i11484_3_lut_4_lut (.A(n111059), .B(lux[17]), .C(n5401), .D(bcd_code_31__N_1185), 
         .Z(bcd_code_31__N_1247)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11484_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14053_2_lut_rep_1000_3_lut (.A(n5740), .B(lux[18]), .C(lux[17]), 
         .Z(n111058)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14053_2_lut_rep_1000_3_lut.init = 16'hf6f6;
    LUT4 i11483_3_lut_4_lut (.A(n5740), .B(lux[18]), .C(lux[17]), .D(n5401), 
         .Z(bcd_code_31__N_1251)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11483_3_lut_4_lut.init = 16'h6966;
    LUT4 i2_4_lut_adj_255 (.A(bcd_code_31__N_850), .B(n111092), .C(n23), 
         .D(n111082), .Z(bcd_code_31__N_900)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A !(B (C+(D))+!B !(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2_4_lut_adj_255.init = 16'h6669;
    LUT4 i11565_3_lut_4_lut (.A(n111067), .B(lux[18]), .C(n5740), .D(bcd_code_31__N_1134), 
         .Z(bcd_code_31__N_1181)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11565_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14061_2_lut_rep_1008_3_lut (.A(n5845), .B(lux[19]), .C(lux[18]), 
         .Z(n111066)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14061_2_lut_rep_1008_3_lut.init = 16'hf6f6;
    LUT4 i11564_3_lut_4_lut (.A(n5845), .B(lux[19]), .C(lux[18]), .D(n5740), 
         .Z(bcd_code_31__N_1185)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11564_3_lut_4_lut.init = 16'h6966;
    LUT4 i101867_4_lut (.A(n111155), .B(n111154), .C(n111177), .D(n109339), 
         .Z(n109794)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101867_4_lut.init = 16'hefee;
    LUT4 i11616_3_lut_4_lut (.A(n110994), .B(lux[11]), .C(n5956), .D(bcd_code_31__N_1593), 
         .Z(bcd_code_31__N_1691)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11616_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14067_2_lut_rep_935_3_lut (.A(n5470), .B(lux[12]), .C(lux[11]), 
         .Z(n110993)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14067_2_lut_rep_935_3_lut.init = 16'hf6f6;
    LUT4 i11615_3_lut_4_lut (.A(n5470), .B(lux[12]), .C(lux[11]), .D(n5956), 
         .Z(bcd_code_31__N_1695)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11615_3_lut_4_lut.init = 16'h6966;
    LUT4 i11589_3_lut_4_lut (.A(n111075), .B(lux[19]), .C(n5845), .D(bcd_code_31__N_1083), 
         .Z(bcd_code_31__N_1130)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11589_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14064_2_lut_rep_1016_3_lut (.A(n5916), .B(lux[20]), .C(lux[19]), 
         .Z(n111074)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14064_2_lut_rep_1016_3_lut.init = 16'hf6f6;
    LUT4 i11588_3_lut_4_lut (.A(n5916), .B(lux[20]), .C(lux[19]), .D(n5845), 
         .Z(bcd_code_31__N_1134)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11588_3_lut_4_lut.init = 16'h6966;
    LUT4 bcd_code_31__N_923_bdd_3_lut_102083_4_lut_3_lut_4_lut (.A(n6354), 
         .B(n6358), .C(n111044), .D(bcd_code_31__N_960), .Z(n110279)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam bcd_code_31__N_923_bdd_3_lut_102083_4_lut_3_lut_4_lut.init = 16'hca0a;
    LUT4 i11595_3_lut_4_lut (.A(n111081), .B(lux[20]), .C(n5916), .D(bcd_code_31__N_1034), 
         .Z(bcd_code_31__N_1079)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11595_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14066_2_lut_rep_1022_3_lut (.A(n6021), .B(lux[21]), .C(lux[20]), 
         .Z(n111080)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14066_2_lut_rep_1022_3_lut.init = 16'hf6f6;
    LUT4 i11594_3_lut_4_lut (.A(n6021), .B(lux[21]), .C(lux[20]), .D(n5916), 
         .Z(bcd_code_31__N_1083)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11594_3_lut_4_lut.init = 16'h6966;
    LUT4 i8728_2_lut_rep_872_3_lut_4_lut (.A(n6354), .B(n6358), .C(n111044), 
         .D(n110944), .Z(n110930)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+(D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i8728_2_lut_rep_872_3_lut_4_lut.init = 16'h3af0;
    LUT4 i2633_2_lut_rep_921_4_lut (.A(n6354), .B(n6358), .C(n111044), 
         .D(bcd_code_31__N_960), .Z(n110979)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2633_2_lut_rep_921_4_lut.init = 16'hffca;
    LUT4 i3399_2_lut_rep_922_3_lut (.A(n6358), .B(n111044), .C(bcd_code_31__N_960), 
         .Z(n110980)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3399_2_lut_rep_922_3_lut.init = 16'hc8c8;
    LUT4 i11622_3_lut_4_lut (.A(n111089), .B(lux[21]), .C(n6021), .D(bcd_code_31__N_992), 
         .Z(bcd_code_31__N_1030)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11622_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14069_2_lut_rep_1030_3_lut (.A(n6059), .B(lux[22]), .C(lux[21]), 
         .Z(n111088)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14069_2_lut_rep_1030_3_lut.init = 16'hf6f6;
    LUT4 i11621_3_lut_4_lut (.A(n6059), .B(lux[22]), .C(lux[21]), .D(n6021), 
         .Z(bcd_code_31__N_1034)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11621_3_lut_4_lut.init = 16'h6966;
    LUT4 i11646_3_lut_4_lut (.A(n111098), .B(lux[22]), .C(n6059), .D(bcd_code_31__N_956), 
         .Z(bcd_code_31__N_988)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11646_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14070_2_lut_rep_1039_3_lut (.A(n5329), .B(lux[23]), .C(lux[22]), 
         .Z(n111097)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14070_2_lut_rep_1039_3_lut.init = 16'hf6f6;
    LUT4 i11645_3_lut_4_lut (.A(n5329), .B(lux[23]), .C(lux[22]), .D(n6059), 
         .Z(bcd_code_31__N_992)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11645_3_lut_4_lut.init = 16'h6966;
    LUT4 i11478_3_lut_4_lut (.A(n111102), .B(lux[23]), .C(n5329), .D(bcd_code_31__N_918), 
         .Z(bcd_code_31__N_952)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11478_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14051_2_lut_rep_1043_3_lut (.A(n5433), .B(lux[24]), .C(lux[23]), 
         .Z(n111101)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14051_2_lut_rep_1043_3_lut.init = 16'hf6f6;
    LUT4 i14060_2_lut_rep_914_3_lut (.A(n5956), .B(lux[11]), .C(lux[10]), 
         .Z(n110972)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14060_2_lut_rep_914_3_lut.init = 16'hf6f6;
    LUT4 i11477_3_lut_4_lut (.A(n5433), .B(lux[24]), .C(lux[23]), .D(n5329), 
         .Z(bcd_code_31__N_956)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11477_3_lut_4_lut.init = 16'h6966;
    LUT4 i2_4_lut_adj_256 (.A(bcd_code_31__N_895), .B(n111044), .C(n23_adj_2865), 
         .D(n111031), .Z(bcd_code_31__N_965)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A !(B (C+(D))+!B !(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2_4_lut_adj_256.init = 16'h6669;
    LUT4 i11561_3_lut_4_lut (.A(n5956), .B(lux[11]), .C(lux[10]), .D(n5701), 
         .Z(bcd_code_31__N_1773)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11561_3_lut_4_lut.init = 16'h6966;
    LUT4 i11487_3_lut_4_lut (.A(n111108), .B(lux[24]), .C(n5433), .D(bcd_code_31__N_891), 
         .Z(bcd_code_31__N_914)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11487_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14054_2_lut_rep_1049_3_lut (.A(n5548), .B(lux[25]), .C(lux[24]), 
         .Z(n111107)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14054_2_lut_rep_1049_3_lut.init = 16'hf6f6;
    LUT4 i11486_3_lut_4_lut (.A(n5548), .B(lux[25]), .C(lux[24]), .D(n5433), 
         .Z(bcd_code_31__N_918)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11486_3_lut_4_lut.init = 16'h6966;
    LUT4 i11520_3_lut_4_lut (.A(n111110), .B(lux[25]), .C(n5548), .D(bcd_code_31__N_864), 
         .Z(bcd_code_31__N_887)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11520_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14057_2_lut_rep_1051_3_lut (.A(n5804), .B(lux[26]), .C(lux[25]), 
         .Z(n111109)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14057_2_lut_rep_1051_3_lut.init = 16'hf6f6;
    LUT4 i11519_3_lut_4_lut (.A(n5804), .B(lux[26]), .C(lux[25]), .D(n5548), 
         .Z(bcd_code_31__N_891)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11519_3_lut_4_lut.init = 16'h6966;
    LUT4 i11571_3_lut_4_lut (.A(n111115), .B(lux[26]), .C(n5804), .D(bcd_code_31__N_846), 
         .Z(bcd_code_31__N_860)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11571_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14063_2_lut_rep_1056_3_lut (.A(lux[27]), .B(lux[26]), .Z(n111114)) /* synthesis lut_function=(A+(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14063_2_lut_rep_1056_3_lut.init = 16'heeee;
    LUT4 i11570_3_lut_4_lut (.A(lux[27]), .B(lux[26]), .C(n5804), .Z(bcd_code_31__N_864)) /* synthesis lut_function=(A (B+!(C))+!A !(B+!(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11570_3_lut_4_lut.init = 16'h9a9a;
    LUT4 i4_4_lut (.A(state[1]), .B(n8_adj_2872), .C(cnt_read[2]), .D(n111243), 
         .Z(n22079)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i4_4_lut.init = 16'h0008;
    LUT4 i1_2_lut (.A(state[2]), .B(state[0]), .Z(n109184)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut.init = 16'h2222;
    LUT4 mux_2455_i1_3_lut_rep_1067 (.A(lux_31__N_511[27]), .B(lux_31__N_543[27]), 
         .C(lux_31__N_575), .Z(lux[27])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam mux_2455_i1_3_lut_rep_1067.init = 16'hcaca;
    LUT4 i10022_2_lut_rep_1057_4_lut (.A(lux_31__N_511[27]), .B(lux_31__N_543[27]), 
         .C(lux_31__N_575), .Z(n111115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10022_2_lut_rep_1057_4_lut.init = 16'hcaca;
    LUT4 i10023_2_lut_rep_1052_4_lut (.A(lux_31__N_511[26]), .B(lux_31__N_543[26]), 
         .C(lux_31__N_575), .D(n5804), .Z(n111110)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10023_2_lut_rep_1052_4_lut.init = 16'h35ca;
    LUT4 i14050_2_lut_rep_818_3_lut (.A(n5260), .B(lux[5]), .C(lux[4]), 
         .Z(n110876)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14050_2_lut_rep_818_3_lut.init = 16'hf6f6;
    LUT4 i10015_2_lut_rep_1050_4_lut (.A(lux_31__N_511[25]), .B(lux_31__N_543[25]), 
         .C(lux_31__N_575), .D(n5548), .Z(n111108)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10015_2_lut_rep_1050_4_lut.init = 16'h35ca;
    LUT4 i10010_2_lut_rep_1044_4_lut (.A(lux_31__N_511[24]), .B(lux_31__N_543[24]), 
         .C(lux_31__N_575), .D(n5433), .Z(n111102)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10010_2_lut_rep_1044_4_lut.init = 16'h35ca;
    LUT4 i10007_2_lut_rep_1040_4_lut (.A(lux_31__N_511[23]), .B(lux_31__N_543[23]), 
         .C(lux_31__N_575), .D(n5329), .Z(n111098)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10007_2_lut_rep_1040_4_lut.init = 16'h35ca;
    LUT4 i10032_2_lut_rep_1031_4_lut (.A(lux_31__N_511[22]), .B(lux_31__N_543[22]), 
         .C(lux_31__N_575), .D(n6059), .Z(n111089)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10032_2_lut_rep_1031_4_lut.init = 16'h35ca;
    LUT4 i10031_2_lut_rep_1023_4_lut (.A(lux_31__N_511[21]), .B(lux_31__N_543[21]), 
         .C(lux_31__N_575), .D(n6021), .Z(n111081)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10031_2_lut_rep_1023_4_lut.init = 16'h35ca;
    LUT4 i10025_2_lut_rep_1009_4_lut (.A(lux_31__N_511[19]), .B(lux_31__N_543[19]), 
         .C(lux_31__N_575), .D(n5845), .Z(n111067)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10025_2_lut_rep_1009_4_lut.init = 16'h35ca;
    LUT4 i2_4_lut_adj_257 (.A(bcd_code_31__N_960), .B(n110980), .C(n5948), 
         .D(n110966), .Z(bcd_code_31__N_1047)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B ((D)+!C)+!B !((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2_4_lut_adj_257.init = 16'h6696;
    LUT4 i11474_3_lut_4_lut (.A(n5260), .B(lux[5]), .C(lux[4]), .D(n5292), 
         .Z(bcd_code_31__N_2104)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11474_3_lut_4_lut.init = 16'h6966;
    LUT4 i10027_2_lut_rep_1017_4_lut (.A(lux_31__N_511[20]), .B(lux_31__N_543[20]), 
         .C(lux_31__N_575), .D(n5916), .Z(n111075)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10027_2_lut_rep_1017_4_lut.init = 16'h35ca;
    LUT4 i10021_2_lut_rep_1001_4_lut (.A(lux_31__N_511[18]), .B(lux_31__N_543[18]), 
         .C(lux_31__N_575), .D(n5740), .Z(n111059)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10021_2_lut_rep_1001_4_lut.init = 16'h35ca;
    LUT4 i10009_2_lut_rep_992_4_lut (.A(lux_31__N_511[17]), .B(lux_31__N_543[17]), 
         .C(lux_31__N_575), .D(n5401), .Z(n111050)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10009_2_lut_rep_992_4_lut.init = 16'h35ca;
    LUT4 i10004_2_lut_rep_979_4_lut (.A(lux_31__N_511[16]), .B(lux_31__N_543[16]), 
         .C(lux_31__N_575), .D(n5225), .Z(n111037)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10004_2_lut_rep_979_4_lut.init = 16'h35ca;
    LUT4 i10026_2_lut_rep_968_4_lut (.A(lux_31__N_511[15]), .B(lux_31__N_543[15]), 
         .C(lux_31__N_575), .D(n5883), .Z(n111026)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10026_2_lut_rep_968_4_lut.init = 16'h35ca;
    LUT4 i10008_2_lut_rep_958_4_lut (.A(lux_31__N_511[14]), .B(lux_31__N_543[14]), 
         .C(lux_31__N_575), .D(n5369), .Z(n111016)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10008_2_lut_rep_958_4_lut.init = 16'h35ca;
    LUT4 i10030_2_lut_rep_948_4_lut (.A(lux_31__N_511[13]), .B(lux_31__N_543[13]), 
         .C(lux_31__N_575), .D(n5988), .Z(n111006)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10030_2_lut_rep_948_4_lut.init = 16'h35ca;
    LUT4 i10012_2_lut_rep_936_4_lut (.A(lux_31__N_511[12]), .B(lux_31__N_543[12]), 
         .C(lux_31__N_575), .D(n5470), .Z(n110994)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10012_2_lut_rep_936_4_lut.init = 16'h35ca;
    LUT4 i10029_2_lut_rep_929_4_lut (.A(lux_31__N_511[11]), .B(lux_31__N_543[11]), 
         .C(lux_31__N_575), .D(n5956), .Z(n110987)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10029_2_lut_rep_929_4_lut.init = 16'h35ca;
    LUT4 i10002_2_lut_4_lut (.A(lux_31__N_511[2]), .B(lux_31__N_543[2]), 
         .C(lux_31__N_575), .D(n5141), .Z(bcd_code_31__N_2145)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10002_2_lut_4_lut.init = 16'h35ca;
    LUT4 i10003_2_lut_rep_792_4_lut (.A(lux_31__N_511[3]), .B(lux_31__N_543[3]), 
         .C(lux_31__N_575), .D(n5181), .Z(n110850)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10003_2_lut_rep_792_4_lut.init = 16'h35ca;
    LUT4 i10006_2_lut_rep_810_4_lut (.A(lux_31__N_511[4]), .B(lux_31__N_543[4]), 
         .C(lux_31__N_575), .D(n5292), .Z(n110868)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10006_2_lut_rep_810_4_lut.init = 16'h35ca;
    LUT4 i10005_2_lut_rep_826_4_lut (.A(lux_31__N_511[5]), .B(lux_31__N_543[5]), 
         .C(lux_31__N_575), .D(n5260), .Z(n110884)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10005_2_lut_rep_826_4_lut.init = 16'h35ca;
    LUT4 i10018_2_lut_rep_844_4_lut (.A(lux_31__N_511[6]), .B(lux_31__N_543[6]), 
         .C(lux_31__N_575), .D(n5660), .Z(n110902)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10018_2_lut_rep_844_4_lut.init = 16'h35ca;
    LUT4 i9996_2_lut_rep_863_4_lut (.A(lux_31__N_511[7]), .B(lux_31__N_543[7]), 
         .C(lux_31__N_575), .D(n5022), .Z(n110921)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i9996_2_lut_rep_863_4_lut.init = 16'h35ca;
    LUT4 i10013_2_lut_rep_878_4_lut (.A(lux_31__N_511[8]), .B(lux_31__N_543[8]), 
         .C(lux_31__N_575), .D(n5502), .Z(n110936)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10013_2_lut_rep_878_4_lut.init = 16'h35ca;
    LUT4 i10016_2_lut_rep_894_4_lut (.A(lux_31__N_511[9]), .B(lux_31__N_543[9]), 
         .C(lux_31__N_575), .D(n5621), .Z(n110952)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10016_2_lut_rep_894_4_lut.init = 16'h35ca;
    LUT4 i10020_2_lut_rep_907_4_lut (.A(lux_31__N_511[10]), .B(lux_31__N_543[10]), 
         .C(lux_31__N_575), .D(n5701), .Z(n110965)) /* synthesis lut_function=(!(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i10020_2_lut_rep_907_4_lut.init = 16'h35ca;
    LUT4 cnt_main_0__bdd_4_lut (.A(cnt_main[0]), .B(dat_valid_N_458), .C(cnt_main[1]), 
         .D(cnt_main[2]), .Z(n110391)) /* synthesis lut_function=(!(A (B (C+(D)))+!A (B+(D)))) */ ;
    defparam cnt_main_0__bdd_4_lut.init = 16'h223b;
    LUT4 i101626_4_lut_4_lut (.A(n111151), .B(n109388), .C(n26), .D(n4_adj_2812), 
         .Z(n28)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101626_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i101630_4_lut_4_lut (.A(n111152), .B(n109488), .C(n16_adj_2834), 
         .D(n6_adj_2829), .Z(n28_adj_2840)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101630_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i101628_4_lut_4_lut (.A(n111157), .B(n109479), .C(n22_adj_2837), 
         .D(n8_adj_2830), .Z(n24_adj_2838)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101628_4_lut_4_lut.init = 16'hf4b0;
    LUT4 LessThan_1522_i31_2_lut_rep_1093 (.A(ch1_dat[15]), .B(n15077), 
         .Z(n111151)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i31_2_lut_rep_1093.init = 16'h6666;
    LUT4 LessThan_1522_i26_3_lut_3_lut (.A(ch1_dat[15]), .B(n15077), .C(n14_adj_2813), 
         .Z(n26)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i26_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101898_2_lut_3_lut (.A(ch1_dat[15]), .B(n15077), .C(n109824), 
         .Z(n109384)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101898_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i101868_2_lut_3_lut (.A(ch1_dat[15]), .B(n15077), .C(n109794), 
         .Z(n109558)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101868_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1516_i31_2_lut_rep_1094 (.A(ch1_dat[15]), .B(lux_31__N_754[15]), 
         .Z(n111152)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i31_2_lut_rep_1094.init = 16'h6666;
    LUT4 LessThan_1516_i16_3_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_754[15]), 
         .C(lux_31__N_754[14]), .Z(n16_adj_2834)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101877_2_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_754[15]), .C(n109803), 
         .Z(n109492)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101877_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i101866_2_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_754[15]), .C(n109792), 
         .Z(n109562)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101866_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i101799_2_lut_4_lut (.A(n111209), .B(state[3]), .C(n111158), 
         .D(n109724), .Z(clk_c_enable_100)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B !(D)))) */ ;
    defparam i101799_2_lut_4_lut.init = 16'h1500;
    LUT4 LessThan_1522_i27_2_lut_rep_1096 (.A(ch1_dat[13]), .B(n15075), 
         .Z(n111154)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i27_2_lut_rep_1096.init = 16'h6666;
    LUT4 LessThan_1522_i29_2_lut_rep_1097 (.A(ch1_dat[14]), .B(n15076), 
         .Z(n111155)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i29_2_lut_rep_1097.init = 16'h6666;
    LUT4 i101300_2_lut_3_lut_4_lut (.A(ch1_dat[14]), .B(n15076), .C(n15075), 
         .D(ch1_dat[13]), .Z(n109388)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101300_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_1522_i14_3_lut_3_lut (.A(ch1_dat[14]), .B(n15076), .C(n15075), 
         .Z(n14_adj_2813)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1516_i25_2_lut_rep_1098 (.A(ch1_dat[12]), .B(lux_31__N_754[12]), 
         .Z(n111156)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i25_2_lut_rep_1098.init = 16'h6666;
    LUT4 LessThan_1516_i20_3_lut_3_lut (.A(ch1_dat[12]), .B(lux_31__N_754[12]), 
         .C(lux_31__N_754[11]), .Z(n20_adj_2836)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1516_i27_2_lut_rep_1099 (.A(ch1_dat[13]), .B(lux_31__N_754[13]), 
         .Z(n111157)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i27_2_lut_rep_1099.init = 16'h6666;
    LUT4 LessThan_1516_i22_3_lut_3_lut (.A(ch1_dat[13]), .B(lux_31__N_754[13]), 
         .C(n20_adj_2836), .Z(n22_adj_2837)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i22_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101880_2_lut_3_lut (.A(ch1_dat[13]), .B(lux_31__N_754[13]), .C(n109806), 
         .Z(n109484)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101880_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i1_3_lut_rep_1095_4_lut (.A(n481), .B(n111228), .C(state[3]), 
         .D(n111209), .Z(n111153)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_3_lut_rep_1095_4_lut.init = 16'hffd0;
    LUT4 i101614_4_lut_4_lut (.A(n111159), .B(n109545), .C(n16_adj_2848), 
         .D(n6_adj_2842), .Z(n28_adj_2854)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101614_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i101618_4_lut_4_lut (.A(n111161), .B(n109366), .C(n20), .D(n6), 
         .Z(n22_adj_2814)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101618_4_lut_4_lut.init = 16'hf4b0;
    LUT4 LessThan_1513_i31_2_lut_rep_1101 (.A(ch1_dat[15]), .B(lux_31__N_576[15]), 
         .Z(n111159)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i31_2_lut_rep_1101.init = 16'h6666;
    LUT4 LessThan_1513_i16_3_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_576[15]), 
         .C(lux_31__N_576[14]), .Z(n16_adj_2848)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101872_2_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_576[15]), .C(n109798), 
         .Z(n109549)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101872_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i101864_2_lut_3_lut (.A(ch1_dat[15]), .B(lux_31__N_576[15]), .C(n109790), 
         .Z(n109566)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101864_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1522_i23_2_lut_rep_1102 (.A(ch1_dat[11]), .B(n15073), 
         .Z(n111160)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i23_2_lut_rep_1102.init = 16'h6666;
    LUT4 LessThan_1522_i18_3_lut_3_lut (.A(ch1_dat[11]), .B(n15073), .C(n15072), 
         .Z(n18)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i18_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1522_i25_2_lut_rep_1103 (.A(ch1_dat[12]), .B(n15074), 
         .Z(n111161)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i25_2_lut_rep_1103.init = 16'h6666;
    LUT4 LessThan_1522_i20_3_lut_3_lut (.A(ch1_dat[12]), .B(n15074), .C(n18), 
         .Z(n20)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101842_2_lut_3_lut (.A(ch1_dat[12]), .B(n15074), .C(n109768), 
         .Z(n109371)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101842_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1516_i21_2_lut_rep_1104 (.A(ch1_dat[10]), .B(lux_31__N_754[10]), 
         .Z(n111162)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i21_2_lut_rep_1104.init = 16'h6666;
    LUT4 LessThan_1516_i18_3_lut_3_lut (.A(ch1_dat[10]), .B(lux_31__N_754[10]), 
         .C(n10_adj_2831), .Z(n18_adj_2835)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i18_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1516_i23_2_lut_rep_1105 (.A(ch1_dat[11]), .B(lux_31__N_754[11]), 
         .Z(n111163)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i23_2_lut_rep_1105.init = 16'h6666;
    LUT4 i101391_2_lut_3_lut_4_lut (.A(ch1_dat[11]), .B(lux_31__N_754[11]), 
         .C(lux_31__N_754[12]), .D(ch1_dat[12]), .Z(n109479)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101391_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i101612_4_lut_4_lut (.A(n111165), .B(n109536), .C(n22_adj_2851), 
         .D(n8_adj_2843), .Z(n24_adj_2852)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101612_4_lut_4_lut.init = 16'hf4b0;
    LUT4 LessThan_1513_i25_2_lut_rep_1106 (.A(ch1_dat[12]), .B(lux_31__N_576[12]), 
         .Z(n111164)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i25_2_lut_rep_1106.init = 16'h6666;
    LUT4 LessThan_1513_i20_3_lut_3_lut (.A(ch1_dat[12]), .B(lux_31__N_576[12]), 
         .C(lux_31__N_576[11]), .Z(n20_adj_2850)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1513_i27_2_lut_rep_1107 (.A(ch1_dat[13]), .B(lux_31__N_576[13]), 
         .Z(n111165)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i27_2_lut_rep_1107.init = 16'h6666;
    LUT4 LessThan_1513_i22_3_lut_3_lut (.A(ch1_dat[13]), .B(lux_31__N_576[13]), 
         .C(n20_adj_2850), .Z(n22_adj_2851)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i22_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101875_2_lut_3_lut (.A(ch1_dat[13]), .B(lux_31__N_576[13]), .C(n109801), 
         .Z(n109541)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101875_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1519_i10_4_lut (.A(lux_31__N_754[0]), .B(lux_31__N_625[2]), 
         .C(ch1_dat[4]), .D(ch1_dat[3]), .Z(n10_adj_2817)) /* synthesis lut_function=(!(A (B (C (D))+!B (C+(D)))+!A ((C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i10_4_lut.init = 16'h0c8e;
    LUT4 LessThan_1522_i21_2_lut_rep_1109 (.A(ch1_dat[10]), .B(n15072), 
         .Z(n111167)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i21_2_lut_rep_1109.init = 16'h6666;
    LUT4 i101278_2_lut_3_lut_4_lut (.A(ch1_dat[10]), .B(n15072), .C(n15073), 
         .D(ch1_dat[11]), .Z(n109366)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101278_2_lut_3_lut_4_lut.init = 16'h9009;
    VLO i1 (.Z(GND_net));
    LUT4 i101500_4_lut (.A(cnt_read[3]), .B(n111203), .C(state[0]), .D(i2c_sda_N_471), 
         .Z(n109588)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam i101500_4_lut.init = 16'hca0a;
    LUT4 LessThan_1516_i19_2_lut_rep_1111 (.A(ch1_dat[9]), .B(lux_31__N_754[9]), 
         .Z(n111169)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i19_2_lut_rep_1111.init = 16'h6666;
    LUT4 i101499_4_lut (.A(n45_adj_2877), .B(cnt_write[3]), .C(state[0]), 
         .D(cnt_start[3]), .Z(n109587)) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
    defparam i101499_4_lut.init = 16'hcfca;
    LUT4 i2_4_lut_adj_258 (.A(bcd_code_31__N_1042), .B(n110905), .C(n23_adj_2874), 
         .D(n110885), .Z(bcd_code_31__N_1140)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A !(B (C+(D))+!B !(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2_4_lut_adj_258.init = 16'h6669;
    LUT4 LessThan_1516_i10_3_lut_3_lut (.A(ch1_dat[9]), .B(lux_31__N_754[9]), 
         .C(lux_31__N_754[5]), .Z(n10_adj_2831)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i10_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1513_i21_2_lut_rep_1113 (.A(ch1_dat[10]), .B(lux_31__N_576[10]), 
         .Z(n111171)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i21_2_lut_rep_1113.init = 16'h6666;
    LUT4 LessThan_1513_i18_3_lut_3_lut (.A(ch1_dat[10]), .B(lux_31__N_576[10]), 
         .C(n10_adj_2844), .Z(n18_adj_2849)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i18_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1513_i23_2_lut_rep_1114 (.A(ch1_dat[11]), .B(lux_31__N_576[11]), 
         .Z(n111172)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i23_2_lut_rep_1114.init = 16'h6666;
    LUT4 i101448_2_lut_3_lut_4_lut (.A(ch1_dat[11]), .B(lux_31__N_576[11]), 
         .C(lux_31__N_576[12]), .D(ch1_dat[12]), .Z(n109536)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101448_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_1513_i19_2_lut_rep_1117 (.A(ch1_dat[9]), .B(lux_31__N_576[9]), 
         .Z(n111175)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i19_2_lut_rep_1117.init = 16'h6666;
    LUT4 LessThan_1513_i10_3_lut_3_lut (.A(ch1_dat[9]), .B(lux_31__N_576[9]), 
         .C(lux_31__N_576[5]), .Z(n10_adj_2844)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i10_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1513_i17_2_lut_rep_1118 (.A(ch1_dat[8]), .B(lux_31__N_576[8]), 
         .Z(n111176)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i17_2_lut_rep_1118.init = 16'h6666;
    LUT4 LessThan_1513_i14_3_lut_3_lut (.A(ch1_dat[8]), .B(lux_31__N_576[8]), 
         .C(n12_adj_2845), .Z(n14_adj_2847)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1522_i15_2_lut_rep_1119 (.A(ch1_dat[7]), .B(n15069), .Z(n111177)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i15_2_lut_rep_1119.init = 16'h6666;
    LUT4 LessThan_1522_i12_3_lut_3_lut (.A(ch1_dat[7]), .B(n15069), .C(n10), 
         .Z(n12)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i12_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1522_i17_2_lut_rep_1120 (.A(ch1_dat[8]), .B(n15070), .Z(n111178)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i17_2_lut_rep_1120.init = 16'h6666;
    LUT4 LessThan_1522_i8_3_lut_3_lut (.A(ch1_dat[8]), .B(n15070), .C(n15066), 
         .Z(n8)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i8_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i1_3_lut_4_lut_4_lut (.A(n67), .B(cnt_main[0]), .C(n9_adj_2866), 
         .D(n111195), .Z(n57)) /* synthesis lut_function=(A (B (C (D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(25[17:26])
    defparam i1_3_lut_4_lut_4_lut.init = 16'hc040;
    LUT4 LessThan_1516_i15_2_lut_rep_1121 (.A(ch1_dat[7]), .B(lux_31__N_754[7]), 
         .Z(n111179)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i15_2_lut_rep_1121.init = 16'h6666;
    LUT4 LessThan_1516_i12_3_lut_3_lut (.A(ch1_dat[7]), .B(lux_31__N_754[7]), 
         .C(lux_31__N_754[6]), .Z(n12_adj_2832)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i12_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101606_4_lut_4_lut (.A(n111187), .B(n109430), .C(n26_adj_2825), 
         .D(n12_adj_2818), .Z(n28_adj_2826)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101606_4_lut_4_lut.init = 16'hf4b0;
    LUT4 LessThan_1513_i15_2_lut_rep_1124 (.A(ch1_dat[7]), .B(lux_31__N_576[7]), 
         .Z(n111182)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i15_2_lut_rep_1124.init = 16'h6666;
    LUT4 LessThan_1522_i13_2_lut_rep_1125 (.A(ch1_dat[6]), .B(n15068), .Z(n111183)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i13_2_lut_rep_1125.init = 16'h6666;
    LUT4 LessThan_1516_i11_2_lut_rep_1126 (.A(ch1_dat[5]), .B(lux_31__N_754[5]), 
         .Z(n111184)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i11_2_lut_rep_1126.init = 16'h6666;
    LUT4 i101377_2_lut_3_lut_4_lut (.A(ch1_dat[5]), .B(lux_31__N_754[5]), 
         .C(lux_31__N_754[9]), .D(ch1_dat[9]), .Z(n109465)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101377_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_1519_i31_2_lut_rep_1129 (.A(ch1_dat[15]), .B(n15176), 
         .Z(n111187)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i31_2_lut_rep_1129.init = 16'h6666;
    LUT4 LessThan_1519_i26_3_lut_3_lut (.A(ch1_dat[15]), .B(n15176), .C(n24_adj_2824), 
         .Z(n26_adj_2825)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i26_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101884_2_lut_3_lut (.A(ch1_dat[15]), .B(n15176), .C(n109810), 
         .Z(n109433)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101884_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1513_i6_3_lut (.A(n4_adj_2828), .B(lux_31__N_576[2]), 
         .C(ch1_dat[2]), .Z(n6_adj_2842)) /* synthesis lut_function=(A (B+!(C))+!A !((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i6_3_lut.init = 16'h8e8e;
    LUT4 i101882_2_lut_3_lut (.A(ch1_dat[15]), .B(n15176), .C(n109808), 
         .Z(n109435)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101882_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_1519_i29_2_lut_rep_1130 (.A(ch1_dat[14]), .B(n15175), 
         .Z(n111188)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i29_2_lut_rep_1130.init = 16'h6666;
    LUT4 LessThan_1519_i24_3_lut_3_lut (.A(ch1_dat[14]), .B(n15175), .C(n15174), 
         .Z(n24_adj_2824)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i24_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i101251_2_lut_3_lut_4_lut (.A(ch1_dat[5]), .B(n111197), .C(n15068), 
         .D(ch1_dat[6]), .Z(n109339)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101251_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i2_3_lut_4_lut (.A(state[3]), .B(n111202), .C(n110391), .D(n109187), 
         .Z(clk_c_enable_126)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i2_3_lut_4_lut.init = 16'h4000;
    LUT4 i3_3_lut_4_lut (.A(state[3]), .B(n111202), .C(cnt_read[1]), .D(n109184), 
         .Z(n8_adj_2872)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i3_3_lut_4_lut.init = 16'h4000;
    LUT4 LessThan_1519_i25_2_lut_rep_1135 (.A(ch1_dat[12]), .B(n15173), 
         .Z(n111193)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i25_2_lut_rep_1135.init = 16'h6666;
    LUT4 LessThan_1519_i22_3_lut_3_lut (.A(ch1_dat[12]), .B(n15173), .C(n14_adj_2819), 
         .Z(n22_adj_2823)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i22_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1519_i27_2_lut_rep_1136 (.A(ch1_dat[13]), .B(n15174), 
         .Z(n111194)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i27_2_lut_rep_1136.init = 16'h6666;
    LUT4 i101342_2_lut_3_lut_4_lut (.A(ch1_dat[13]), .B(n15174), .C(n15175), 
         .D(ch1_dat[14]), .Z(n109430)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101342_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i101907_3_lut (.A(cnt_read[1]), .B(n111192), .C(cnt_read[0]), 
         .Z(n64)) /* synthesis lut_function=(!(A (B+(C))+!A (B+!(C)))) */ ;
    defparam i101907_3_lut.init = 16'h1212;
    LUT4 i2_4_lut_adj_259 (.A(bcd_code_31__N_797), .B(n110806), .C(n5653), 
         .D(n110788), .Z(bcd_code_31__N_795)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B ((D)+!C)+!B !((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2_4_lut_adj_259.init = 16'h6696;
    LUT4 i50_4_lut (.A(n81685), .B(n2281), .C(n111180), .D(n110463), 
         .Z(n19)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i50_4_lut.init = 16'hca0a;
    LUT4 i1_2_lut_3_lut_4_lut (.A(n111209), .B(state[3]), .C(n24), .D(n30), 
         .Z(n109214)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut.init = 16'h1000;
    LUT4 LessThan_1513_i11_2_lut_rep_1138 (.A(ch1_dat[5]), .B(lux_31__N_576[5]), 
         .Z(n111196)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i11_2_lut_rep_1138.init = 16'h6666;
    LUT4 i101434_2_lut_3_lut_4_lut (.A(ch1_dat[5]), .B(lux_31__N_576[5]), 
         .C(lux_31__N_576[9]), .D(ch1_dat[9]), .Z(n109522)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101434_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_1522_i9_2_lut_rep_1140 (.A(ch1_dat[4]), .B(n15066), .Z(n111198)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i9_2_lut_rep_1140.init = 16'h6666;
    LUT4 i101264_2_lut_3_lut_4_lut (.A(ch1_dat[4]), .B(n15066), .C(n15070), 
         .D(ch1_dat[8]), .Z(n109352)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101264_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i1_4_lut (.A(n111173), .B(n81685), .C(n57), .D(state[0]), .Z(n1961)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut.init = 16'hfcee;
    LUT4 LessThan_1519_i21_2_lut_rep_1142 (.A(ch1_dat[10]), .B(n15171), 
         .Z(n111200)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i21_2_lut_rep_1142.init = 16'h6666;
    LUT4 i101886_2_lut_3_lut_4_lut (.A(ch1_dat[10]), .B(n15171), .C(n111208), 
         .D(n111207), .Z(n109408)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101886_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 LessThan_1519_i18_3_lut_3_lut (.A(ch1_dat[10]), .B(n15171), .C(n16_adj_2820), 
         .Z(n18_adj_2821)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i18_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1519_i23_2_lut_rep_1143 (.A(ch1_dat[11]), .B(n15172), 
         .Z(n111201)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i23_2_lut_rep_1143.init = 16'h6666;
    LUT4 LessThan_1519_i14_3_lut_3_lut (.A(ch1_dat[11]), .B(n15172), .C(n15168), 
         .Z(n14_adj_2819)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i1_2_lut_3_lut_4_lut_adj_260 (.A(rst_n_c), .B(n111209), .C(n22070), 
         .D(state[3]), .Z(n4_adj_2871)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_260.init = 16'h0020;
    LUT4 i2_3_lut_4_lut_adj_261 (.A(rst_n_c), .B(n111209), .C(state[0]), 
         .D(n111254), .Z(n22026)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
    defparam i2_3_lut_4_lut_adj_261.init = 16'hffdf;
    LUT4 i1_3_lut_4_lut (.A(rst_n_c), .B(n111209), .C(n111217), .D(state[0]), 
         .Z(n109219)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i1_3_lut_4_lut.init = 16'h0200;
    LUT4 LessThan_1513_i9_2_lut_rep_1146 (.A(ch1_dat[4]), .B(lux_31__N_576[4]), 
         .Z(n111204)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i9_2_lut_rep_1146.init = 16'h6666;
    LUT4 LessThan_1513_i8_3_lut_3_lut (.A(ch1_dat[4]), .B(lux_31__N_576[4]), 
         .C(lux_31__N_576[3]), .Z(n8_adj_2843)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i8_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1519_i19_2_lut_rep_1149 (.A(ch1_dat[9]), .B(n15170), .Z(n111207)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i19_2_lut_rep_1149.init = 16'h6666;
    LUT4 i2_4_lut_adj_262 (.A(bcd_code_31__N_1384), .B(n110721), .C(n5695), 
         .D(n110701), .Z(bcd_code_31__N_1394)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B ((D)+!C)+!B !((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2_4_lut_adj_262.init = 16'h6696;
    LUT4 LessThan_1519_i16_3_lut_3_lut (.A(ch1_dat[9]), .B(n15170), .C(n15169), 
         .Z(n16_adj_2820)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_1519_i17_2_lut_rep_1150 (.A(ch1_dat[8]), .B(n15169), .Z(n111208)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i17_2_lut_rep_1150.init = 16'h6666;
    LUT4 i54_2_lut_rep_1151 (.A(clk_400khz), .B(n22821), .Z(n111209)) /* synthesis lut_function=(A+!(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i54_2_lut_rep_1151.init = 16'hbbbb;
    LUT4 i3_2_lut_rep_1144_3_lut (.A(clk_400khz), .B(n22821), .C(rst_n_c), 
         .Z(n111202)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i3_2_lut_rep_1144_3_lut.init = 16'h4040;
    LUT4 i3_1_lut_2_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(n30), 
         .D(state[3]), .Z(n3)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i3_1_lut_2_lut_3_lut_4_lut.init = 16'hffbf;
    LUT4 LessThan_1516_i6_3_lut (.A(n4_adj_2828), .B(lux_31__N_754[2]), 
         .C(ch1_dat[2]), .Z(n6_adj_2829)) /* synthesis lut_function=(A (B+!(C))+!A !((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i6_3_lut.init = 16'h8e8e;
    LUT4 i2_2_lut_rep_1122_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(n30), 
         .D(state[3]), .Z(n111180)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_2_lut_rep_1122_3_lut_4_lut.init = 16'h0040;
    LUT4 i75457_2_lut_rep_1137_3_lut (.A(clk_400khz), .B(n22821), .C(state[3]), 
         .Z(n111195)) /* synthesis lut_function=(A+((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i75457_2_lut_rep_1137_3_lut.init = 16'hfbfb;
    LUT4 i101805_2_lut_rep_1127_2_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), 
         .C(n111228), .D(state[3]), .Z(clk_c_enable_124)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101805_2_lut_rep_1127_2_lut_3_lut_4_lut.init = 16'h0004;
    LUT4 i101862_2_lut_rep_1115_2_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), 
         .C(n67), .D(state[3]), .Z(n111173)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101862_2_lut_rep_1115_2_lut_3_lut_4_lut.init = 16'hffbf;
    LUT4 i101819_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(state[2]), 
         .D(n111228), .Z(clk_c_enable_149)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101819_3_lut_4_lut.init = 16'h0004;
    LUT4 i2_2_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(n24), .D(state[3]), 
         .Z(n2281)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_2_lut_3_lut_4_lut.init = 16'h0040;
    PFUMX i102152 (.BLUT(n111258), .ALUT(n111259), .C0(state[2]), .Z(n30));
    LUT4 i1_2_lut_rep_1131_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(n109217), 
         .D(state[3]), .Z(n111189)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_rep_1131_3_lut_4_lut.init = 16'h0040;
    LUT4 i101837_3_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(n40), 
         .D(n4_adj_2867), .Z(clk_c_enable_111)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101837_3_lut_3_lut_4_lut.init = 16'h0004;
    LUT4 i101849_2_lut_3_lut_4_lut (.A(clk_400khz), .B(n22821), .C(state[0]), 
         .D(n111254), .Z(clk_c_enable_120)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101849_2_lut_3_lut_4_lut.init = 16'h0004;
    LUT4 i1_2_lut_3_lut_4_lut_adj_263 (.A(clk_400khz), .B(n22821), .C(n111237), 
         .D(n111254), .Z(clk_c_enable_99)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_263.init = 16'h0040;
    LUT4 LessThan_1522_i7_2_lut_rep_1154 (.A(ch1_dat[3]), .B(n15065), .Z(n111212)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam LessThan_1522_i7_2_lut_rep_1154.init = 16'h6666;
    LUT4 LessThan_1519_i15_2_lut_rep_1162 (.A(ch1_dat[7]), .B(n15168), .Z(n111220)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam LessThan_1519_i15_2_lut_rep_1162.init = 16'h6666;
    LUT4 i101328_2_lut_3_lut_4_lut (.A(ch1_dat[7]), .B(n15168), .C(n15172), 
         .D(ch1_dat[11]), .Z(n109416)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[10:28])
    defparam i101328_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i1_2_lut_rep_1166 (.A(state[0]), .B(state[1]), .Z(n111224)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_1166.init = 16'h2222;
    LUT4 i1_2_lut_3_lut (.A(state[0]), .B(state[1]), .C(state[2]), .Z(n109187)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i1_2_lut_3_lut.init = 16'h0202;
    LUT4 i1_4_lut_4_lut (.A(cnt_mode1[1]), .B(cnt_mode1[2]), .C(cnt_mode1[0]), 
         .D(cnt_mode1[3]), .Z(n22_adj_2861)) /* synthesis lut_function=(!(A (B+(D))+!A (B ((D)+!C)+!B (D)))) */ ;
    defparam i1_4_lut_4_lut.init = 16'h0073;
    LUT4 i22_4_lut_4_lut (.A(cnt_mode1[2]), .B(n111189), .C(n2281), .D(state_back[0]), 
         .Z(n109023)) /* synthesis lut_function=(A ((D)+!C)+!A (B (C (D))+!B ((D)+!C))) */ ;
    defparam i22_4_lut_4_lut.init = 16'hfb0b;
    LUT4 i101200_2_lut_rep_1191 (.A(cnt_main[0]), .B(cnt_main[1]), .Z(n111249)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i101200_2_lut_rep_1191.init = 16'heeee;
    LUT4 i2_3_lut_4_lut_adj_264 (.A(cnt_main[0]), .B(cnt_main[1]), .C(n111186), 
         .D(dat_valid_N_458), .Z(clk_c_enable_65)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i2_3_lut_4_lut_adj_264.init = 16'h0100;
    LUT4 i11524_4_lut (.A(bcd_code_31__N_1769), .B(n5621), .C(n110958), 
         .D(bcd_code_31__N_1773), .Z(bcd_code_31__N_1768)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11524_4_lut.init = 16'h6aaa;
    LUT4 LessThan_1516_i4_3_lut_4_lut_4_lut (.A(lux_31__N_754[0]), .B(lux_31__N_657[0]), 
         .C(lux_31__N_657[1]), .D(lux_31__N_625[2]), .Z(n4_adj_2828)) /* synthesis lut_function=(!(A (B (C+(D))+!B (C (D)))+!A (C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i4_3_lut_4_lut_4_lut.init = 16'h072a;
    LUT4 LessThan_1522_i4_3_lut_4_lut (.A(lux_31__N_754[0]), .B(lux_31__N_657[0]), 
         .C(lux_31__N_657[1]), .D(lux_31__N_625[2]), .Z(n4_adj_2812)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !((D)+!C))+!A (C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1522_i4_3_lut_4_lut.init = 16'h2f02;
    LUT4 i101859_2_lut_rep_1198 (.A(cnt_mode2[1]), .B(cnt_mode2[2]), .Z(n111256)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i101859_2_lut_rep_1198.init = 16'h1111;
    LUT4 i25_3_lut_4_lut_3_lut (.A(cnt_mode2[1]), .B(cnt_mode2[2]), .C(cnt_mode2[3]), 
         .Z(n14_adj_2864)) /* synthesis lut_function=(!(A ((C)+!B)+!A (B+!(C)))) */ ;
    defparam i25_3_lut_4_lut_3_lut.init = 16'h1818;
    LUT4 i11506_4_lut (.A(bcd_code_31__N_1845), .B(n5502), .C(n110943), 
         .D(bcd_code_31__N_1849), .Z(bcd_code_31__N_1844)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11506_4_lut.init = 16'h6aaa;
    LUT4 i11399_4_lut (.A(bcd_code_31__N_1914), .B(n5022), .C(n110929), 
         .D(bcd_code_31__N_1918), .Z(bcd_code_31__N_1913)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11399_4_lut.init = 16'h6aaa;
    LUT4 i11548_4_lut (.A(bcd_code_31__N_1974), .B(n5660), .C(n110913), 
         .D(bcd_code_31__N_1978), .Z(bcd_code_31__N_1973)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11548_4_lut.init = 16'h6aaa;
    LUT4 i11473_4_lut (.A(bcd_code_31__N_2025), .B(n5260), .C(n110893), 
         .D(bcd_code_31__N_2029), .Z(bcd_code_31__N_2024)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11473_4_lut.init = 16'h6aaa;
    LUT4 i11476_4_lut (.A(bcd_code_31__N_2067), .B(n5292), .C(n110876), 
         .D(bcd_code_31__N_2071), .Z(bcd_code_31__N_2066)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11476_4_lut.init = 16'h6aaa;
    LUT4 i11467_4_lut (.A(bcd_code_31__N_2100), .B(n5181), .C(n110858), 
         .D(bcd_code_31__N_2104), .Z(bcd_code_31__N_2099)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11467_4_lut.init = 16'h6aaa;
    LUT4 i3454_2_lut_rep_663_3_lut (.A(n6295), .B(n110806), .C(bcd_code_31__N_1384), 
         .Z(n110721)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3454_2_lut_rep_663_3_lut.init = 16'hc8c8;
    LUT4 mux_9082_i1_4_lut_4_lut_4_lut (.A(n6291), .B(n6295), .C(n110806), 
         .D(bcd_code_31__N_1384), .Z(bcd_code_31__N_1380[2])) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A (B (C+!(D))+!B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam mux_9082_i1_4_lut_4_lut_4_lut.init = 16'h0f3a;
    LUT4 i140_2_lut (.A(n30), .B(n67), .Z(n83242)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i140_2_lut.init = 16'heeee;
    LUT4 i3236_2_lut_rep_662_4_lut (.A(n6291), .B(n6295), .C(n110806), 
         .D(bcd_code_31__N_1384), .Z(n110720)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3236_2_lut_rep_662_4_lut.init = 16'hffca;
    LUT4 bcd_code_31__N_1381_bdd_3_lut_4_lut_3_lut_4_lut (.A(n6291), .B(n6295), 
         .C(n110806), .D(bcd_code_31__N_1384), .Z(n110270)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam bcd_code_31__N_1381_bdd_3_lut_4_lut_3_lut_4_lut.init = 16'hca0a;
    LUT4 i1_3_lut (.A(state[2]), .B(state[3]), .C(n45), .Z(n24_adj_2811)) /* synthesis lut_function=(A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_3_lut.init = 16'ha8a8;
    LUT4 i3_4_lut (.A(n111195), .B(n111224), .C(state[2]), .D(n109229), 
         .Z(n2285)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i3_4_lut.init = 16'h0040;
    LUT4 i92_4_lut (.A(n22_adj_2861), .B(n109589), .C(state[2]), .D(n109269), 
         .Z(n67)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
    defparam i92_4_lut.init = 16'hc5c0;
    LUT4 i101180_2_lut (.A(state[0]), .B(state[1]), .Z(n109269)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i101180_2_lut.init = 16'h4444;
    LUT4 i11464_4_lut (.A(bcd_code_31__N_2124), .B(n5141), .C(n110840), 
         .D(bcd_code_31__N_2128), .Z(bcd_code_31__N_2123)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11464_4_lut.init = 16'h6aaa;
    LUT4 i101834_4_lut (.A(n24_adj_2811), .B(n109760), .C(n2285), .D(n25), 
         .Z(clk_c_enable_106)) /* synthesis lut_function=(!(A+!(B (C+!(D))))) */ ;
    defparam i101834_4_lut.init = 16'h4044;
    LUT4 i101833_3_lut (.A(ack_flag), .B(n111153), .C(n2285), .Z(n109760)) /* synthesis lut_function=(!(A (B+(C))+!A (B))) */ ;
    defparam i101833_3_lut.init = 16'h1313;
    LUT4 i101876_4_lut (.A(n109488), .B(n111157), .C(n111156), .D(n109468), 
         .Z(n109803)) /* synthesis lut_function=(!(A (B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101876_4_lut.init = 16'h5755;
    LUT4 i101380_4_lut (.A(n111163), .B(n111162), .C(n111169), .D(n109455), 
         .Z(n109468)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101380_4_lut.init = 16'h0001;
    LUT4 i101367_4_lut (.A(n111170), .B(n111179), .C(n13), .D(n109444), 
         .Z(n109455)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101367_4_lut.init = 16'h0001;
    LUT4 i101356_4_lut (.A(n111184), .B(n111191), .C(ch1_dat[3]), .D(lux_31__N_754[3]), 
         .Z(n109444)) /* synthesis lut_function=(!(A+(B+!(C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101356_4_lut.init = 16'h1001;
    LUT4 LessThan_1516_i13_2_lut (.A(ch1_dat[6]), .B(lux_31__N_754[6]), 
         .Z(n13)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i13_2_lut.init = 16'h6666;
    LUT4 LessThan_1516_i29_2_lut (.A(ch1_dat[14]), .B(lux_31__N_754[14]), 
         .Z(n109488)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam LessThan_1516_i29_2_lut.init = 16'h9999;
    LUT4 i6_4_lut (.A(n111249), .B(n12_adj_2863), .C(state[0]), .D(n111180), 
         .Z(n109208)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i6_4_lut.init = 16'h0040;
    LUT4 i5_4_lut (.A(dat_valid_N_458), .B(cnt_main[2]), .C(n2285), .D(n111173), 
         .Z(n12_adj_2863)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i5_4_lut.init = 16'h0400;
    LUT4 i75590_4_lut (.A(n81685), .B(n2285), .C(n110126), .D(n111180), 
         .Z(n1989)) /* synthesis lut_function=(!(A (B+(C (D)))+!A (B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i75590_4_lut.init = 16'h0322;
    LUT4 i101897_4_lut (.A(n111155), .B(n111154), .C(n111161), .D(n109362), 
         .Z(n109824)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101897_4_lut.init = 16'hefee;
    LUT4 i101274_4_lut (.A(n111160), .B(n111167), .C(n111166), .D(n109347), 
         .Z(n109362)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101274_4_lut.init = 16'h0100;
    LUT4 i101259_4_lut (.A(n111178), .B(n111177), .C(n111183), .D(n109334), 
         .Z(n109347)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101259_4_lut.init = 16'h5455;
    LUT4 i101246_4_lut (.A(n111190), .B(n111198), .C(n111212), .D(n5), 
         .Z(n109334)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[10:30])
    defparam i101246_4_lut.init = 16'h5554;
    LUT4 i1_2_lut_adj_265 (.A(cnt_mode1[3]), .B(cnt_mode1[1]), .Z(n4_adj_2868)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_adj_265.init = 16'heeee;
    LUT4 i8112_3_lut_4_lut (.A(n6264), .B(n6268), .C(n110905), .D(n4), 
         .Z(n6291)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+(D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i8112_3_lut_4_lut.init = 16'h3af0;
    LUT4 i3367_2_lut_rep_748_3_lut (.A(n6268), .B(n110905), .C(bcd_code_31__N_797), 
         .Z(n110806)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i3367_2_lut_rep_748_3_lut.init = 16'hc8c8;
    LUT4 bcd_code_31__N_1190_bdd_3_lut_4_lut_3_lut_4_lut (.A(n6264), .B(n6268), 
         .C(n110905), .D(bcd_code_31__N_797), .Z(n110273)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam bcd_code_31__N_1190_bdd_3_lut_4_lut_3_lut_4_lut.init = 16'hca0a;
    LUT4 i101871_4_lut (.A(n109545), .B(n111165), .C(n111164), .D(n109525), 
         .Z(n109798)) /* synthesis lut_function=(!(A (B+(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101871_4_lut.init = 16'h5755;
    LUT4 i101437_4_lut (.A(n111172), .B(n111171), .C(n111175), .D(n109512), 
         .Z(n109525)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101437_4_lut.init = 16'h0001;
    LUT4 i101424_4_lut (.A(n111176), .B(n111182), .C(n13_adj_2846), .D(n109501), 
         .Z(n109512)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101424_4_lut.init = 16'h0001;
    LUT4 i101413_4_lut (.A(n111196), .B(n111204), .C(ch1_dat[3]), .D(lux_31__N_576[3]), 
         .Z(n109501)) /* synthesis lut_function=(!(A+(B+!(C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam i101413_4_lut.init = 16'h1001;
    LUT4 LessThan_1513_i29_2_lut (.A(ch1_dat[14]), .B(lux_31__N_576[14]), 
         .Z(n109545)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[5:22])
    defparam LessThan_1513_i29_2_lut.init = 16'h9999;
    LUT4 i11463_3_lut_4_lut (.A(n110850), .B(lux[2]), .C(n5141), .D(bcd_code_31__N_2128), 
         .Z(bcd_code_31__N_2139)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11463_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14046_2_lut_rep_782_3_lut (.A(n5181), .B(lux[3]), .C(lux[2]), 
         .Z(n110840)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14046_2_lut_rep_782_3_lut.init = 16'hf6f6;
    LUT4 i11462_3_lut_4_lut (.A(n5181), .B(lux[3]), .C(lux[2]), .D(n5141), 
         .Z(bcd_code_31__N_2143)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11462_3_lut_4_lut.init = 16'h6966;
    LUT4 i11466_3_lut_4_lut (.A(n110868), .B(lux[3]), .C(n5181), .D(bcd_code_31__N_2104), 
         .Z(bcd_code_31__N_2124)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11466_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14047_2_lut_rep_800_3_lut (.A(n5292), .B(lux[4]), .C(lux[3]), 
         .Z(n110858)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14047_2_lut_rep_800_3_lut.init = 16'hf6f6;
    PFUMX i102062 (.BLUT(GND_net), .ALUT(n110289), .C0(n5465), .Z(bcd_code_31__N_851));
    LUT4 i11472_3_lut_4_lut (.A(n110902), .B(lux[5]), .C(n5260), .D(bcd_code_31__N_2029), 
         .Z(bcd_code_31__N_2067)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11472_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14049_2_lut_rep_835_3_lut (.A(n5660), .B(lux[6]), .C(lux[5]), 
         .Z(n110893)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14049_2_lut_rep_835_3_lut.init = 16'hf6f6;
    LUT4 i11471_3_lut_4_lut (.A(n5660), .B(lux[6]), .C(lux[5]), .D(n5260), 
         .Z(bcd_code_31__N_2071)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11471_3_lut_4_lut.init = 16'h6966;
    PFUMX i102060 (.BLUT(n110285), .ALUT(n110284), .C0(n23), .Z(bcd_code_31__N_896));
    LUT4 i11547_3_lut_4_lut (.A(n110921), .B(lux[6]), .C(n5660), .D(bcd_code_31__N_1978), 
         .Z(bcd_code_31__N_2025)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11547_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i14059_2_lut_rep_855_3_lut (.A(n5022), .B(lux[7]), .C(lux[6]), 
         .Z(n110913)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14059_2_lut_rep_855_3_lut.init = 16'hf6f6;
    LUT4 i11546_3_lut_4_lut (.A(n5022), .B(lux[7]), .C(lux[6]), .D(n5660), 
         .Z(bcd_code_31__N_2029)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11546_3_lut_4_lut.init = 16'h6966;
    LUT4 i11563_4_lut (.A(bcd_code_31__N_1691), .B(n5701), .C(n110972), 
         .D(bcd_code_31__N_1695), .Z(bcd_code_31__N_1690)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11563_4_lut.init = 16'h6aaa;
    LUT4 i11398_3_lut_4_lut (.A(n110936), .B(lux[7]), .C(n5022), .D(bcd_code_31__N_1918), 
         .Z(bcd_code_31__N_1974)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11398_3_lut_4_lut.init = 16'h1fe0;
    PFUMX i102058 (.BLUT(n110282), .ALUT(n110281), .C0(n23_adj_2865), 
          .Z(bcd_code_31__N_961));
    LUT4 i101865_4_lut (.A(n109488), .B(n111170), .C(n111179), .D(n13), 
         .Z(n109792)) /* synthesis lut_function=(!(A (B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101865_4_lut.init = 16'h5557;
    LUT4 i14045_2_lut_rep_871_3_lut (.A(n5502), .B(lux[8]), .C(lux[7]), 
         .Z(n110929)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14045_2_lut_rep_871_3_lut.init = 16'hf6f6;
    LUT4 i11397_3_lut_4_lut (.A(n5502), .B(lux[8]), .C(lux[7]), .D(n5022), 
         .Z(bcd_code_31__N_1978)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11397_3_lut_4_lut.init = 16'h6966;
    LUT4 i101879_4_lut (.A(n111156), .B(n111163), .C(n111162), .D(n109465), 
         .Z(n109806)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[10:28])
    defparam i101879_4_lut.init = 16'hefee;
    LUT4 i11505_3_lut_4_lut (.A(n110952), .B(lux[8]), .C(n5502), .D(bcd_code_31__N_1849), 
         .Z(bcd_code_31__N_1914)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11505_3_lut_4_lut.init = 16'h1fe0;
    PFUMX i102056 (.BLUT(n110279), .ALUT(n110278), .C0(n5948), .Z(bcd_code_31__N_1043));
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 i23_4_lut_4_lut (.A(cnt_mode2[0]), .B(cnt_mode2[1]), .C(cnt_mode2[3]), 
         .D(cnt_mode2[2]), .Z(n9)) /* synthesis lut_function=(!(A (B+(D))+!A (B (D)+!B (C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i23_4_lut_4_lut.init = 16'h0166;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    LUT4 i14056_2_lut_rep_885_3_lut (.A(n5621), .B(lux[9]), .C(lux[8]), 
         .Z(n110943)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14056_2_lut_rep_885_3_lut.init = 16'hf6f6;
    LUT4 i11504_3_lut_4_lut (.A(n5621), .B(lux[9]), .C(lux[8]), .D(n5502), 
         .Z(bcd_code_31__N_1918)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11504_3_lut_4_lut.init = 16'h6966;
    LUT4 i10_4_lut_adj_266 (.A(n15_adj_2858), .B(n20_adj_2857), .C(lux_31__N_576[18]), 
         .D(lux_31__N_576[16]), .Z(lux_31__N_575)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i10_4_lut_adj_266.init = 16'hfffe;
    LUT4 i4_2_lut_adj_267 (.A(lux_31__N_576[21]), .B(lux_31__N_576[22]), 
         .Z(n15_adj_2858)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i4_2_lut_adj_267.init = 16'heeee;
    LUT4 i9_4_lut_adj_268 (.A(n17), .B(lux_31__N_576[23]), .C(n14_adj_2859), 
         .D(lux_31__N_576[17]), .Z(n20_adj_2857)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut_adj_268.init = 16'hfffe;
    LUT4 i74208_4_lut_4_lut_4_lut_4_lut (.A(n67), .B(cnt_mode1[2]), .C(n109217), 
         .D(n111195), .Z(n81716)) /* synthesis lut_function=((B (C+(D))+!B (D))+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(25[17:26])
    defparam i74208_4_lut_4_lut_4_lut_4_lut.init = 16'hffd5;
    LUT4 i6_3_lut_adj_269 (.A(lux_31__N_576[19]), .B(n2350), .C(lux_31__N_576[24]), 
         .Z(n17)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i6_3_lut_adj_269.init = 16'hfefe;
    LUT4 i3_2_lut_adj_270 (.A(lux_31__N_576[25]), .B(lux_31__N_576[20]), 
         .Z(n14_adj_2859)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3_2_lut_adj_270.init = 16'heeee;
    LUT4 i11523_3_lut_4_lut (.A(n110965), .B(lux[9]), .C(n5621), .D(bcd_code_31__N_1773), 
         .Z(bcd_code_31__N_1845)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11523_3_lut_4_lut.init = 16'h1fe0;
    PFUMX i102054 (.BLUT(n110276), .ALUT(n110275), .C0(n23_adj_2874), 
          .Z(bcd_code_31__N_798));
    rpr0521rs_driver u1 (.i2c_sda_N_454(i2c_sda_N_454), .clk_400khz(clk_400khz), 
            .clk_c(clk_c), .\lux_31__N_657[0] (lux_31__N_657[0]), .\lux_31__N_754[0] (lux_31__N_754[0]), 
            .clk_c_enable_65(clk_c_enable_65), .state({state}), .cnt_mode2({cnt_mode2}), 
            .\state_back[0] (state_back[0]), .clk_c_enable_99(clk_c_enable_99), 
            .n22821(n22821), .dat_valid(dat_valid), .dat_valid_N_458(dat_valid_N_458), 
            .i2c_sda_out(i2c_sda_out), .\lux_31__N_657[1] (lux_31__N_657[1]), 
            .\ch1_dat[2] (ch1_dat[2]), .\ch1_dat[3] (ch1_dat[3]), .\ch1_dat[4] (ch1_dat[4]), 
            .\ch1_dat[5] (ch1_dat[5]), .\ch1_dat[6] (ch1_dat[6]), .\ch1_dat[7] (ch1_dat[7]), 
            .\ch1_dat[8] (ch1_dat[8]), .\ch1_dat[9] (ch1_dat[9]), .\ch1_dat[10] (ch1_dat[10]), 
            .\ch1_dat[11] (ch1_dat[11]), .\ch1_dat[12] (ch1_dat[12]), .\ch1_dat[13] (ch1_dat[13]), 
            .\ch1_dat[14] (ch1_dat[14]), .\ch1_dat[15] (ch1_dat[15]), .clk_c_enable_126(clk_c_enable_126), 
            .\lux_31__N_625[2] (lux_31__N_625[2]), .\lux_31__N_625[3] (lux_31__N_625[3]), 
            .\ch0_dat[3] (ch0_dat[3]), .\ch0_dat[4] (ch0_dat[4]), .\ch0_dat[5] (ch0_dat[5]), 
            .\ch0_dat[6] (ch0_dat[6]), .\ch0_dat[7] (ch0_dat[7]), .\ch0_dat[8] (ch0_dat[8]), 
            .\ch0_dat[9] (ch0_dat[9]), .\ch0_dat[10] (ch0_dat[10]), .\ch0_dat[11] (ch0_dat[11]), 
            .\ch0_dat[12] (ch0_dat[12]), .\ch0_dat[13] (ch0_dat[13]), .\ch0_dat[14] (ch0_dat[14]), 
            .\ch0_dat[15] (ch0_dat[15]), .prox_dat({prox_dat}), .GND_net(GND_net), 
            .n481(n481), .n111990(n111990), .cnt_read({cnt_read}), .n64(n64), 
            .\cnt_write[3] (cnt_write[3]), .\cnt_main[2] (cnt_main[2]), 
            .clk_c_enable_100(clk_c_enable_100), .n1991(n1991), .\cnt_main[0] (cnt_main[0]), 
            .cnt_mode1({cnt_mode1}), .clk_c_enable_120(clk_c_enable_120), 
            .clk_c_enable_124(clk_c_enable_124), .clk_c_enable_106(clk_c_enable_106), 
            .n1990(n1990), .clk_c_enable_149(clk_c_enable_149), .n109208(n109208), 
            .clk_c_enable_111(clk_c_enable_111), .n1989(n1989), .\cnt_main[1] (cnt_main[1]), 
            .i2c_scl_c(i2c_scl_c), .\cnt_start[3] (cnt_start[3]), .ack_flag(ack_flag), 
            .n22026(n22026), .n111256(n111256), .n22070(n22070), .n45(n45_adj_2877), 
            .rst_n_c(rst_n_c), .n111209(n111209), .n109219(n109219), .n111186(n111186), 
            .n4(n4_adj_2871), .n111202(n111202), .n109214(n109214), .n14(n14_adj_2864), 
            .n111195(n111195), .n109217(n109217), .n67(n67), .n81685(n81685), 
            .n111228(n111228), .n22(n22), .n111217(n111217), .n111192(n111192), 
            .n111237(n111237), .n111254(n111254), .n111243(n111243), .n2281(n2281), 
            .n110126(n110126), .n111203(n111203), .n109229(n109229), .n4_adj_171(n4_adj_2810), 
            .n111158(n111158), .n110385(n110385), .n22079(n22079), .n111213(n111213), 
            .n45_adj_172(n45_adj_2876), .n19(n19), .n2285(n2285), .n1984(n1984), 
            .n324(n324), .n110463(n110463), .n24(n24_adj_2811), .n109724(n109724), 
            .n25(n25), .n83242(n83242), .n110467(n110467), .n45_adj_173(n45), 
            .n40(n40), .n4_adj_174(n4_adj_2867), .n4_adj_175(n4_adj_2868), 
            .n109269(n109269), .n15273(n15273), .i2c_sda_N_471(i2c_sda_N_471), 
            .n4_adj_176(n4_adj_2856), .n109187(n109187)) /* synthesis syn_module_defined=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(34[18] 44[3])
    LUT4 i14058_2_lut_rep_900_3_lut (.A(n5701), .B(lux[10]), .C(lux[9]), 
         .Z(n110958)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i14058_2_lut_rep_900_3_lut.init = 16'hf6f6;
    LUT4 i11522_3_lut_4_lut (.A(n5701), .B(lux[10]), .C(lux[9]), .D(n5621), 
         .Z(bcd_code_31__N_1849)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11522_3_lut_4_lut.init = 16'h6966;
    PFUMX i102052 (.BLUT(n110273), .ALUT(n110272), .C0(n5653), .Z(bcd_code_31__N_1257));
    LUT4 i11562_3_lut_4_lut (.A(n110987), .B(lux[10]), .C(n5701), .D(bcd_code_31__N_1695), 
         .Z(bcd_code_31__N_1769)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11562_3_lut_4_lut.init = 16'h1fe0;
    LUT4 m0_lut (.Z(n111990)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
    defparam m0_lut.init = 16'h0000;
    decoder u2 (.dat_valid(dat_valid), .prox_dat({prox_dat}), .\ch0_dat[13] (ch0_dat[13]), 
            .\ch0_dat[12] (ch0_dat[12]), .GND_net(GND_net), .\ch0_dat[14] (ch0_dat[14]), 
            .\ch0_dat[11] (ch0_dat[11]), .\ch0_dat[10] (ch0_dat[10]), .\ch0_dat[3] (ch0_dat[3]), 
            .\lux_31__N_754[0] (lux_31__N_754[0]), .\ch0_dat[4] (ch0_dat[4]), 
            .\lux_31__N_625[2] (lux_31__N_625[2]), .\ch0_dat[9] (ch0_dat[9]), 
            .\ch0_dat[8] (ch0_dat[8]), .\lux_31__N_576[16] (lux_31__N_576[16]), 
            .\lux_31__N_576[17] (lux_31__N_576[17]), .\lux_31__N_511[25] (lux_31__N_511[25]), 
            .\lux_31__N_543[25] (lux_31__N_543[25]), .lux_31__N_575(lux_31__N_575), 
            .\lux[25] (lux[25]), .\lux_31__N_511[17] (lux_31__N_511[17]), 
            .\lux_31__N_543[17] (lux_31__N_543[17]), .\lux[17] (lux[17]), 
            .\ch0_dat[7] (ch0_dat[7]), .\ch0_dat[6] (ch0_dat[6]), .\ch0_dat[5] (ch0_dat[5]), 
            .\lux_31__N_625[3] (lux_31__N_625[3]), .\lux_31__N_657[0] (lux_31__N_657[0]), 
            .\lux_31__N_657[1] (lux_31__N_657[1]), .\ch1_dat[15] (ch1_dat[15]), 
            .\ch1_dat[14] (ch1_dat[14]), .\ch1_dat[13] (ch1_dat[13]), .\ch1_dat[12] (ch1_dat[12]), 
            .\ch1_dat[11] (ch1_dat[11]), .\ch1_dat[10] (ch1_dat[10]), .\ch1_dat[8] (ch1_dat[8]), 
            .\ch1_dat[9] (ch1_dat[9]), .\ch1_dat[6] (ch1_dat[6]), .\ch1_dat[7] (ch1_dat[7]), 
            .\ch1_dat[4] (ch1_dat[4]), .\ch1_dat[5] (ch1_dat[5]), .\ch1_dat[2] (ch1_dat[2]), 
            .\ch1_dat[3] (ch1_dat[3]), .\ch0_dat[15] (ch0_dat[15]), .\lux_31__N_576[14] (lux_31__N_576[14]), 
            .\lux_31__N_576[15] (lux_31__N_576[15]), .\lux_31__N_576[12] (lux_31__N_576[12]), 
            .\lux_31__N_576[13] (lux_31__N_576[13]), .\lux_31__N_576[10] (lux_31__N_576[10]), 
            .\lux_31__N_576[11] (lux_31__N_576[11]), .\lux_31__N_576[8] (lux_31__N_576[8]), 
            .\lux_31__N_576[9] (lux_31__N_576[9]), .\lux_31__N_576[7] (lux_31__N_576[7]), 
            .\lux_31__N_754[24] (lux_31__N_754[24]), .\lux_31__N_754[25] (lux_31__N_754[25]), 
            .\lux_31__N_754[22] (lux_31__N_754[22]), .\lux_31__N_754[23] (lux_31__N_754[23]), 
            .\lux_31__N_754[20] (lux_31__N_754[20]), .\lux_31__N_754[21] (lux_31__N_754[21]), 
            .\lux_31__N_754[18] (lux_31__N_754[18]), .\lux_31__N_754[19] (lux_31__N_754[19]), 
            .\lux_31__N_754[16] (lux_31__N_754[16]), .\lux_31__N_754[17] (lux_31__N_754[17]), 
            .\lux_31__N_754[14] (lux_31__N_754[14]), .\lux_31__N_754[15] (lux_31__N_754[15]), 
            .\lux_31__N_754[12] (lux_31__N_754[12]), .\lux_31__N_754[13] (lux_31__N_754[13]), 
            .\lux_31__N_754[10] (lux_31__N_754[10]), .\lux_31__N_754[11] (lux_31__N_754[11]), 
            .\lux_31__N_754[9] (lux_31__N_754[9]), .lux_31__N_753(lux_31__N_753), 
            .\lux_31__N_754[6] (lux_31__N_754[6]), .\lux_31__N_754[7] (lux_31__N_754[7]), 
            .\lux_31__N_754[5] (lux_31__N_754[5]), .n15077(n15077), .n15075(n15075), 
            .n15076(n15076), .n15073(n15073), .n15074(n15074), .\lux_31__N_543[27] (lux_31__N_543[27]), 
            .\lux_31__N_543[26] (lux_31__N_543[26]), .n15072(n15072), .\lux_31__N_543[23] (lux_31__N_543[23]), 
            .\lux_31__N_543[24] (lux_31__N_543[24]), .\lux_31__N_543[21] (lux_31__N_543[21]), 
            .\lux_31__N_543[22] (lux_31__N_543[22]), .\lux_31__N_543[19] (lux_31__N_543[19]), 
            .\lux_31__N_543[20] (lux_31__N_543[20]), .\lux_31__N_543[18] (lux_31__N_543[18]), 
            .\lux_31__N_543[15] (lux_31__N_543[15]), .\lux_31__N_543[16] (lux_31__N_543[16]), 
            .\lux_31__N_543[13] (lux_31__N_543[13]), .\lux_31__N_543[14] (lux_31__N_543[14]), 
            .\lux_31__N_543[11] (lux_31__N_543[11]), .\lux_31__N_543[12] (lux_31__N_543[12]), 
            .\lux_31__N_543[9] (lux_31__N_543[9]), .\lux_31__N_543[10] (lux_31__N_543[10]), 
            .\lux_31__N_543[7] (lux_31__N_543[7]), .\lux_31__N_543[8] (lux_31__N_543[8]), 
            .n15066(n15066), .n15065(n15065), .\lux_31__N_543[5] (lux_31__N_543[5]), 
            .\lux_31__N_543[6] (lux_31__N_543[6]), .\lux_31__N_543[3] (lux_31__N_543[3]), 
            .\lux_31__N_543[4] (lux_31__N_543[4]), .\lux_31__N_543[2] (lux_31__N_543[2]), 
            .n15069(n15069), .n15070(n15070), .n15068(n15068), .\lux_31__N_511[18] (lux_31__N_511[18]), 
            .led_c_4(led_c_4), .led_c_3(led_c_3), .led_c_2(led_c_2), .\lux_31__N_511[27] (lux_31__N_511[27]), 
            .n486(n486), .n2359(n2359), .\lux_31__N_576[5] (lux_31__N_576[5]), 
            .\lux_31__N_576[3] (lux_31__N_576[3]), .\lux_31__N_576[4] (lux_31__N_576[4]), 
            .\lux_31__N_576[2] (lux_31__N_576[2]), .\lux_31__N_511[10] (lux_31__N_511[10]), 
            .n2356(n2356), .n21676(n21676), .\lux_31__N_511[19] (lux_31__N_511[19]), 
            .\lux[19] (lux[19]), .\lux_31__N_511[26] (lux_31__N_511[26]), 
            .\lux[26] (lux[26]), .n15187(n15187), .n15185(n15185), .n15186(n15186), 
            .\lux[18] (lux[18]), .n15183(n15183), .n15184(n15184), .n15181(n15181), 
            .n15182(n15182), .n111166(n111166), .n8(n8), .n16(n16), 
            .n111170(n111170), .n12(n12_adj_2832), .n14(n14_adj_2833), 
            .n15179(n15179), .n15180(n15180), .n15177(n15177), .n15178(n15178), 
            .n15175(n15175), .n15176(n15176), .n15173(n15173), .n15174(n15174), 
            .n13(n13_adj_2846), .n12_adj_111(n12_adj_2845), .n111197(n111197), 
            .n10(n10), .n111190(n111190), .n111191(n111191), .n15171(n15171), 
            .n15172(n15172), .n15169(n15169), .n15170(n15170), .\lux_31__N_754[3] (lux_31__N_754[3]), 
            .n8_adj_112(n8_adj_2830), .n15168(n15168), .n111222(n111222), 
            .led_c_7(led_c_7), .n6(n6), .n5(n5), .n111219(n111219), 
            .n12_adj_113(n12_adj_2818), .\lux_31__N_754[2] (lux_31__N_754[2]), 
            .\lux_31__N_511[9] (lux_31__N_511[9]), .\lux[9] (lux[9]), .led_c_1(led_c_1), 
            .led_c_5(led_c_5), .\lux_31__N_511[8] (lux_31__N_511[8]), .\lux[8] (lux[8]), 
            .\lux_31__N_511[7] (lux_31__N_511[7]), .\lux[7] (lux[7]), .\lux_31__N_511[6] (lux_31__N_511[6]), 
            .\lux[6] (lux[6]), .\lux_31__N_511[5] (lux_31__N_511[5]), .\lux[5] (lux[5]), 
            .\lux_31__N_511[4] (lux_31__N_511[4]), .\lux[4] (lux[4]), .\lux_31__N_511[3] (lux_31__N_511[3]), 
            .\lux[3] (lux[3]), .\lux_31__N_576[24] (lux_31__N_576[24]), 
            .\lux_31__N_576[25] (lux_31__N_576[25]), .\lux_31__N_576[22] (lux_31__N_576[22]), 
            .\lux_31__N_576[23] (lux_31__N_576[23]), .\lux_31__N_576[20] (lux_31__N_576[20]), 
            .\lux_31__N_576[21] (lux_31__N_576[21]), .\lux_31__N_511[2] (lux_31__N_511[2]), 
            .\lux[2] (lux[2]), .\lux_31__N_511[20] (lux_31__N_511[20]), 
            .\lux[20] (lux[20]), .\lux_31__N_511[21] (lux_31__N_511[21]), 
            .\lux[21] (lux[21]), .\lux_31__N_511[22] (lux_31__N_511[22]), 
            .\lux[22] (lux[22]), .\lux_31__N_511[23] (lux_31__N_511[23]), 
            .\lux[23] (lux[23]), .\lux_31__N_511[24] (lux_31__N_511[24]), 
            .\lux[24] (lux[24]), .\lux_31__N_576[18] (lux_31__N_576[18]), 
            .\lux_31__N_576[19] (lux_31__N_576[19]), .\lux[10] (lux[10]), 
            .\lux_31__N_511[11] (lux_31__N_511[11]), .\lux[11] (lux[11]), 
            .\lux_31__N_511[12] (lux_31__N_511[12]), .\lux[12] (lux[12]), 
            .\lux_31__N_511[13] (lux_31__N_511[13]), .\lux[13] (lux[13]), 
            .\lux_31__N_511[14] (lux_31__N_511[14]), .\lux[14] (lux[14]), 
            .\lux_31__N_511[15] (lux_31__N_511[15]), .\lux[15] (lux[15]), 
            .\lux_31__N_511[16] (lux_31__N_511[16]), .\lux[16] (lux[16]), 
            .bcd_code_31__N_965(bcd_code_31__N_965), .n110806(n110806), 
            .n5695(n5695), .n110905(n110905), .n6295(n6295), .bcd_code_31__N_960(bcd_code_31__N_960), 
            .n111044(n111044), .n110966(n110966), .n110278(n110278), .bcd_code_31__N_1130(bcd_code_31__N_1130), 
            .bcd_code_31__N_1134(bcd_code_31__N_1134), .n111067(n111067), 
            .n5740(n5740), .n6358(n6358), .n6354(n6354), .rst_n_c(rst_n_c), 
            .n110534(n110534), .bcd_code_31__N_841(bcd_code_31__N_841), 
            .bcd_code_31__N_855(bcd_code_31__N_855), .bcd_code_31__N_851(bcd_code_31__N_851), 
            .bcd_code_31__N_859(bcd_code_31__N_859), .n6264(n6264), .n5653(n5653), 
            .bcd_code_31__N_797(bcd_code_31__N_797), .n110788(n110788), 
            .n6268(n6268), .n110521(n110521), .n110506(n110506), .n110515(n110515), 
            .n110514(n110514), .n110491(n110491), .n110497(n110497), .n110490(n110490), 
            .n16726(n16726), .bcd_code_31__N_2024(bcd_code_31__N_2024), 
            .n110559(n110559), .n110530(n110530), .n110533(n110533), .n110545(n110545), 
            .n110547(n110547), .n14_adj_114(n14_adj_2761), .n14_adj_115(n14_adj_2769), 
            .bcd_code_31__N_1042(bcd_code_31__N_1042), .n110980(n110980), 
            .n110885(n110885), .n14_adj_116(n14_adj_2799), .n83313(n83313), 
            .n110532(n110532), .n7(n7_adj_2798), .n110481(n110481), .n14_adj_117(n14_adj_2779), 
            .bcd_code_31__N_1180(bcd_code_31__N_1180), .n14_adj_118(n14_adj_2802), 
            .bcd_code_31__N_1129(bcd_code_31__N_1129), .n107666(n107666), 
            .bcd_code_31__N_961(bcd_code_31__N_961), .n14_adj_119(n14_adj_2804), 
            .n111031(n111031), .n23(n23_adj_2865), .n16565(n16565), .n7_adj_120(n7_adj_2803), 
            .n5948(n5948), .bcd_code_31__N_1078(bcd_code_31__N_1078), .n110476(n110476), 
            .n110546(n110546), .n14_adj_121(n14_adj_2755), .bcd_code_31__N_1079(bcd_code_31__N_1079), 
            .bcd_code_31__N_1083(bcd_code_31__N_1083), .n111075(n111075), 
            .n5845(n5845), .n5465(n5465), .bcd_code_31__N_1029(bcd_code_31__N_1029), 
            .n111092(n111092), .\lux_data[15] (lux_data[15]), .n110513(n110513), 
            .bcd_code_31__N_895(bcd_code_31__N_895), .n110282(n110282), 
            .n14_adj_122(n14_adj_2758), .n110480(n110480), .n110487(n110487), 
            .n16456(n16456), .bcd_code_31__N_900(bcd_code_31__N_900), .n14_adj_123(n14_adj_2800), 
            .n14_adj_124(n14_adj_2792), .n7_adj_125(n7_adj_2783), .bcd_code_31__N_987(bcd_code_31__N_987), 
            .n14_adj_126(n14_adj_2784), .bcd_code_31__N_896(bcd_code_31__N_896), 
            .n107670(n107670), .n16625(n16625), .n111113(n111113), .n14_adj_127(n14_adj_2790), 
            .bcd_code_31__N_951(bcd_code_31__N_951), .n14_adj_128(n14_adj_2808), 
            .n23_adj_129(n23), .n7_adj_130(n7_adj_2791), .bcd_code_31__N_850(bcd_code_31__N_850), 
            .n111082(n111082), .n110522(n110522), .n110485(n110485), .n110520(n110520), 
            .bcd_code_31__N_913(bcd_code_31__N_913), .n110484(n110484), 
            .n110281(n110281), .bcd_code_31__N_886(bcd_code_31__N_886), 
            .n110285(n110285), .n110284(n110284), .n110289(n110289), .n110720(n110720), 
            .n110568(n110568), .n110582(n110582), .n110567(n110567), .n16700(n16700), 
            .bcd_code_31__N_1519(bcd_code_31__N_1519), .\lux[27] (lux[27]), 
            .n83413(n83413), .n110486(n110486), .n110478(n110478), .n110930(n110930), 
            .n23_adj_131(n23_adj_2874), .n110482(n110482), .n14_adj_132(n14_adj_2756), 
            .n4(n4), .n110475(n110475), .n110721(n110721), .bcd_code_31__N_1384(bcd_code_31__N_1384), 
            .n110701(n110701), .\lux_data[11] (lux_data[11]), .n107662(n107662), 
            .n14_adj_133(n14_adj_2778), .n7_adj_134(n7_adj_2764), .n110523(n110523), 
            .n14_adj_135(n14_adj_2768), .n110535(n110535), .n14_adj_136(n14_adj_2766), 
            .n14_adj_137(n14_adj_2765), .n110524(n110524), .bcd_code_31__N_1769(bcd_code_31__N_1769), 
            .bcd_code_31__N_1773(bcd_code_31__N_1773), .n110965(n110965), 
            .n5621(n5621), .n110536(n110536), .n110507(n110507), .n110508(n110508), 
            .n14_adj_138(n14_adj_2763), .bcd_code_31__N_1845(bcd_code_31__N_1845), 
            .bcd_code_31__N_1849(bcd_code_31__N_1849), .n110952(n110952), 
            .n5502(n5502), .\lux_data[31] (lux_data[31]), .bcd_code_31__N_1973(bcd_code_31__N_1973), 
            .bcd_code_31__N_1914(bcd_code_31__N_1914), .bcd_code_31__N_1918(bcd_code_31__N_1918), 
            .n110936(n110936), .n5022(n5022), .n14_adj_139(n14_adj_2759), 
            .bcd_code_31__N_1974(bcd_code_31__N_1974), .bcd_code_31__N_1978(bcd_code_31__N_1978), 
            .n110921(n110921), .n5660(n5660), .n110269(n110269), .n14_adj_140(n14_adj_2777), 
            .\bcd_code_31__N_1380[2] (bcd_code_31__N_1380[2]), .bcd_code_31__N_2025(bcd_code_31__N_2025), 
            .bcd_code_31__N_2029(bcd_code_31__N_2029), .n110902(n110902), 
            .n5260(n5260), .n7_adj_141(n7_adj_2767), .bcd_code_31__N_2067(bcd_code_31__N_2067), 
            .bcd_code_31__N_2071(bcd_code_31__N_2071), .n110884(n110884), 
            .n5292(n5292), .n16584(n16584), .n83307(n83307), .n14_adj_142(n14_adj_2770), 
            .bcd_code_31__N_2100(bcd_code_31__N_2100), .bcd_code_31__N_2104(bcd_code_31__N_2104), 
            .n110868(n110868), .n5181(n5181), .n14_adj_143(n14), .n14_adj_144(n14_adj_2793), 
            .n14_adj_145(n14_adj_2782), .n16558(n16558), .n107664(n107664), 
            .n7_adj_146(n7), .n7_adj_147(n7_adj_2786), .bcd_code_31__N_795(bcd_code_31__N_795), 
            .n14_adj_148(n14_adj_2785), .bcd_code_31__N_1257(bcd_code_31__N_1257), 
            .n7_adj_149(n7_adj_2781), .n14_adj_150(n14_adj_2787), .n14_adj_151(n14_adj_2795), 
            .n110557(n110557), .n110556(n110556), .n110558(n110558), .bcd_code_31__N_1913(bcd_code_31__N_1913), 
            .n110495(n110495), .n110494(n110494), .n7_adj_152(n7_adj_2806), 
            .n16471(n16471), .n16601(n16601), .n110592(n110592), .n83295(n83295), 
            .n14_adj_153(n14_adj_2807), .n16738(n16738), .n110591(n110591), 
            .bcd_code_31__N_2138(bcd_code_31__N_2138), .n16428(n16428), 
            .n83319(n83319), .\lux_data[7] (lux_data[7]), .n110493(n110493), 
            .n922({bcd_code_31__N_2123, bcd_code_31__N_2139, bcd_code_31__N_2143, 
            bcd_code_31__N_2145}), .n110578(n110578), .n110496(n110496), 
            .n110581(n110581), .n110817(n110817), .n14_adj_154(n14_adj_2760), 
            .n110580(n110580), .n14_adj_155(n14_adj_2762), .n107668(n107668), 
            .bcd_code_31__N_2124(bcd_code_31__N_2124), .bcd_code_31__N_2128(bcd_code_31__N_2128), 
            .n110850(n110850), .n5141(n5141), .n14_adj_156(n14_adj_2794), 
            .n14_adj_157(n14_adj_2797), .n14_adj_158(n14_adj_2789), .n14_adj_159(n14_adj_2757), 
            .n7_adj_160(n7_adj_2788), .bcd_code_31__N_1030(bcd_code_31__N_1030), 
            .bcd_code_31__N_1034(bcd_code_31__N_1034), .n111081(n111081), 
            .n5916(n5916), .n107675(n107675), .n14_adj_161(n14_adj_2801), 
            .n7_adj_162(n7_adj_2796), .n14_adj_163(n14_adj_2805), .n16300(n16300), 
            .n110504(n110504), .n110503(n110503), .\lux_data[3] (lux_data[3]), 
            .n110505(n110505), .n110566(n110566), .bcd_code_31__N_988(bcd_code_31__N_988), 
            .bcd_code_31__N_992(bcd_code_31__N_992), .n111089(n111089), 
            .n6021(n6021), .\lux_data[23] (lux_data[23]), .n110489(n110489), 
            .bcd_code_31__N_1844(bcd_code_31__N_1844), .\lux_data[27] (lux_data[27]), 
            .n83415(n83415), .bcd_code_31__N_952(bcd_code_31__N_952), .bcd_code_31__N_956(bcd_code_31__N_956), 
            .n111098(n111098), .n6059(n6059), .bcd_code_31__N_1768(bcd_code_31__N_1768), 
            .n6291(n6291), .n110272(n110272), .bcd_code_31__N_914(bcd_code_31__N_914), 
            .bcd_code_31__N_918(bcd_code_31__N_918), .n111102(n111102), 
            .n5329(n5329), .n14_adj_164(n14_adj_2772), .n107610(n107610), 
            .n7_adj_165(n7_adj_2774), .n14_adj_166(n14_adj_2776), .n14_adj_167(n14_adj_2773), 
            .n7_adj_168(n7_adj_2771), .n14_adj_169(n14_adj_2775), .n16550(n16550), 
            .n14_adj_170(n14_adj_2780), .bcd_code_31__N_1140(bcd_code_31__N_1140), 
            .bcd_code_31__N_1690(bcd_code_31__N_1690), .bcd_code_31__N_887(bcd_code_31__N_887), 
            .bcd_code_31__N_891(bcd_code_31__N_891), .n111108(n111108), 
            .n5433(n5433), .n16351(n16351), .bcd_code_31__N_798(bcd_code_31__N_798), 
            .bcd_code_31__N_860(bcd_code_31__N_860), .bcd_code_31__N_864(bcd_code_31__N_864), 
            .n111110(n111110), .n5548(n5548), .bcd_code_31__N_2099(bcd_code_31__N_2099), 
            .bcd_code_31__N_1588(bcd_code_31__N_1588), .bcd_code_31__N_1394(bcd_code_31__N_1394), 
            .bcd_code_31__N_1450(bcd_code_31__N_1450), .\lux_data[19] (lux_data[19]), 
            .bcd_code_31__N_1246(bcd_code_31__N_1246), .n110276(n110276), 
            .bcd_code_31__N_1047(bcd_code_31__N_1047), .bcd_code_31__N_1366(bcd_code_31__N_1366), 
            .bcd_code_31__N_1043(bcd_code_31__N_1043), .bcd_code_31__N_1392(bcd_code_31__N_1392), 
            .n83303(n83303), .bcd_code_31__N_1691(bcd_code_31__N_1691), 
            .bcd_code_31__N_1695(bcd_code_31__N_1695), .n110987(n110987), 
            .n5701(n5701), .n110944(n110944), .bcd_code_31__N_842(bcd_code_31__N_842), 
            .bcd_code_31__N_846(bcd_code_31__N_846), .n111115(n111115), 
            .n5804(n5804), .bcd_code_31__N_1306(bcd_code_31__N_1306), .n83327(n83327), 
            .bcd_code_31__N_1589(bcd_code_31__N_1589), .bcd_code_31__N_1593(bcd_code_31__N_1593), 
            .n110994(n110994), .n5956(n5956), .bcd_code_31__N_1520(bcd_code_31__N_1520), 
            .bcd_code_31__N_1524(bcd_code_31__N_1524), .n111006(n111006), 
            .n5470(n5470), .bcd_code_31__N_1451(bcd_code_31__N_1451), .bcd_code_31__N_1455(bcd_code_31__N_1455), 
            .n111016(n111016), .n5988(n5988), .bcd_code_31__N_2066(bcd_code_31__N_2066), 
            .bcd_code_31__N_1367(bcd_code_31__N_1367), .bcd_code_31__N_1371(bcd_code_31__N_1371), 
            .n111026(n111026), .n5369(n5369), .n16541(n16541), .bcd_code_31__N_1307(bcd_code_31__N_1307), 
            .bcd_code_31__N_1311(bcd_code_31__N_1311), .n111037(n111037), 
            .n5883(n5883), .n110979(n110979), .n110275(n110275), .bcd_code_31__N_1247(bcd_code_31__N_1247), 
            .bcd_code_31__N_1251(bcd_code_31__N_1251), .n111050(n111050), 
            .n5225(n5225), .bcd_code_31__N_1181(bcd_code_31__N_1181), .bcd_code_31__N_1185(bcd_code_31__N_1185), 
            .n111059(n111059), .n5401(n5401)) /* synthesis syn_module_defined=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(46[9] 54[3])
    PFUMX i102050 (.BLUT(n110270), .ALUT(n110269), .C0(n5695), .Z(bcd_code_31__N_1392));
    segment_scan u4 (.clk_c(clk_c), .seg_din_c(seg_din_c), .seg_rck_c(seg_rck_c), 
            .n110534(n110534), .rst_n_c(rst_n_c), .n110536(n110536), .n110535(n110535), 
            .seg_sck_c(seg_sck_c), .n16584(n16584), .n14(n14_adj_2756), 
            .\lux_data[31] (lux_data[31]), .n7(n7_adj_2764), .n14_adj_1(n14_adj_2765), 
            .n83303(n83303), .n14_adj_2(n14_adj_2766), .n7_adj_3(n7_adj_2767), 
            .n14_adj_4(n14_adj_2768), .n16456(n16456), .n107662(n107662), 
            .n14_adj_5(n14_adj_2778), .n14_adj_6(n14_adj_2779), .n16726(n16726), 
            .\lux_data[27] (lux_data[27]), .n7_adj_7(n7_adj_2791), .n14_adj_8(n14_adj_2792), 
            .n83313(n83313), .n14_adj_9(n14_adj_2790), .n16625(n16625), 
            .n14_adj_10(n14_adj_2758), .n7_adj_11(n7_adj_2783), .n14_adj_12(n14_adj_2784), 
            .n14_adj_13(n14_adj_2808), .n107670(n107670), .n14_adj_14(n14_adj_2800), 
            .n7_adj_15(n7_adj_2806), .n14_adj_16(n14_adj_2807), .\lux_data[23] (lux_data[23]), 
            .n16601(n16601), .n14_adj_17(n14_adj_2759), .n83307(n83307), 
            .n14_adj_18(n14_adj_2762), .n7_adj_19(n7), .n14_adj_20(n14_adj_2763), 
            .n16471(n16471), .n107668(n107668), .n14_adj_21(n14_adj_2770), 
            .n14_adj_22(n14_adj_2777), .n16738(n16738), .\lux_data[19] (lux_data[19]), 
            .n7_adj_23(n7_adj_2796), .n14_adj_24(n14_adj_2797), .n83319(n83319), 
            .n14_adj_25(n14_adj_2794), .n7_adj_26(n7_adj_2788), .n14_adj_27(n14_adj_2789), 
            .n16300(n16300), .n14_adj_28(n14_adj_2757), .n14_adj_29(n14_adj_2805), 
            .n107675(n107675), .n14_adj_30(n14_adj_2801), .\lux_data[15] (lux_data[15]), 
            .n83415(n83415), .n16351(n16351), .n7_adj_31(n7_adj_2803), 
            .n14_adj_32(n14_adj_2804), .\lux_data[11] (lux_data[11]), .n83327(n83327), 
            .n14_adj_33(n14_adj_2802), .n7_adj_34(n7_adj_2798), .n14_adj_35(n14_adj_2799), 
            .n16565(n16565), .n14_adj_36(n14_adj_2755), .n16541(n16541), 
            .n107666(n107666), .n14_adj_37(n14_adj_2761), .n14_adj_38(n14_adj_2769), 
            .n16700(n16700), .\lux_data[7] (lux_data[7]), .n16558(n16558), 
            .n14_adj_39(n14), .n7_adj_40(n7_adj_2781), .n14_adj_41(n14_adj_2782), 
            .n83413(n83413), .n14_adj_42(n14_adj_2785), .n7_adj_43(n7_adj_2786), 
            .n14_adj_44(n14_adj_2787), .n14_adj_45(n14_adj_2795), .n107664(n107664), 
            .n14_adj_46(n14_adj_2793), .n16550(n16550), .n14_adj_47(n14_adj_2760), 
            .\lux_data[3] (lux_data[3]), .n7_adj_48(n7_adj_2771), .n14_adj_49(n14_adj_2772), 
            .n83295(n83295), .n14_adj_50(n14_adj_2773), .n7_adj_51(n7_adj_2774), 
            .n14_adj_52(n14_adj_2775), .n16428(n16428), .n107610(n107610), 
            .n14_adj_53(n14_adj_2776), .n14_adj_54(n14_adj_2780), .n110487(n110487), 
            .n110480(n110480), .n110481(n110481), .n110482(n110482), .n110476(n110476), 
            .n110475(n110475), .n110478(n110478), .n110497(n110497), .n110491(n110491), 
            .n110490(n110490), .n110489(n110489), .n110484(n110484), .n110485(n110485), 
            .n110486(n110486), .n110494(n110494), .n110496(n110496), .n110495(n110495), 
            .n110493(n110493), .GND_net(GND_net), .n110582(n110582), .n110568(n110568), 
            .n110567(n110567), .n110566(n110566), .n110556(n110556), .n110557(n110557), 
            .n110558(n110558), .n110506(n110506), .n110507(n110507), .n110508(n110508), 
            .bcd_code_31__N_2138(bcd_code_31__N_2138), .n110591(n110591), 
            .n110592(n110592), .n110524(n110524), .n110515(n110515), .n110514(n110514), 
            .n110513(n110513), .n110503(n110503), .n110504(n110504), .n110505(n110505), 
            .n110523(n110523), .n110522(n110522), .n110521(n110521), .n110520(n110520), 
            .n110817(n110817), .n110581(n110581), .n110580(n110580), .n110578(n110578), 
            .n110559(n110559), .n110545(n110545), .n110547(n110547), .n110546(n110546), 
            .n110533(n110533), .n110532(n110532), .n110530(n110530)) /* synthesis syn_module_defined=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(56[14] 72[3])
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module rpr0521rs_driver
//

module rpr0521rs_driver (i2c_sda_N_454, clk_400khz, clk_c, \lux_31__N_657[0] , 
            \lux_31__N_754[0] , clk_c_enable_65, state, cnt_mode2, \state_back[0] , 
            clk_c_enable_99, n22821, dat_valid, dat_valid_N_458, i2c_sda_out, 
            \lux_31__N_657[1] , \ch1_dat[2] , \ch1_dat[3] , \ch1_dat[4] , 
            \ch1_dat[5] , \ch1_dat[6] , \ch1_dat[7] , \ch1_dat[8] , 
            \ch1_dat[9] , \ch1_dat[10] , \ch1_dat[11] , \ch1_dat[12] , 
            \ch1_dat[13] , \ch1_dat[14] , \ch1_dat[15] , clk_c_enable_126, 
            \lux_31__N_625[2] , \lux_31__N_625[3] , \ch0_dat[3] , \ch0_dat[4] , 
            \ch0_dat[5] , \ch0_dat[6] , \ch0_dat[7] , \ch0_dat[8] , 
            \ch0_dat[9] , \ch0_dat[10] , \ch0_dat[11] , \ch0_dat[12] , 
            \ch0_dat[13] , \ch0_dat[14] , \ch0_dat[15] , prox_dat, GND_net, 
            n481, n111990, cnt_read, n64, \cnt_write[3] , \cnt_main[2] , 
            clk_c_enable_100, n1991, \cnt_main[0] , cnt_mode1, clk_c_enable_120, 
            clk_c_enable_124, clk_c_enable_106, n1990, clk_c_enable_149, 
            n109208, clk_c_enable_111, n1989, \cnt_main[1] , i2c_scl_c, 
            \cnt_start[3] , ack_flag, n22026, n111256, n22070, n45, 
            rst_n_c, n111209, n109219, n111186, n4, n111202, n109214, 
            n14, n111195, n109217, n67, n81685, n111228, n22, 
            n111217, n111192, n111237, n111254, n111243, n2281, 
            n110126, n111203, n109229, n4_adj_171, n111158, n110385, 
            n22079, n111213, n45_adj_172, n19, n2285, n1984, n324, 
            n110463, n24, n109724, n25, n83242, n110467, n45_adj_173, 
            n40, n4_adj_174, n4_adj_175, n109269, n15273, i2c_sda_N_471, 
            n4_adj_176, n109187) /* synthesis syn_module_defined=1 */ ;
    output i2c_sda_N_454;
    output clk_400khz;
    input clk_c;
    output \lux_31__N_657[0] ;
    output \lux_31__N_754[0] ;
    input clk_c_enable_65;
    output [3:0]state;
    output [3:0]cnt_mode2;
    output \state_back[0] ;
    input clk_c_enable_99;
    output n22821;
    output dat_valid;
    output dat_valid_N_458;
    input i2c_sda_out;
    output \lux_31__N_657[1] ;
    output \ch1_dat[2] ;
    output \ch1_dat[3] ;
    output \ch1_dat[4] ;
    output \ch1_dat[5] ;
    output \ch1_dat[6] ;
    output \ch1_dat[7] ;
    output \ch1_dat[8] ;
    output \ch1_dat[9] ;
    output \ch1_dat[10] ;
    output \ch1_dat[11] ;
    output \ch1_dat[12] ;
    output \ch1_dat[13] ;
    output \ch1_dat[14] ;
    output \ch1_dat[15] ;
    input clk_c_enable_126;
    output \lux_31__N_625[2] ;
    output \lux_31__N_625[3] ;
    output \ch0_dat[3] ;
    output \ch0_dat[4] ;
    output \ch0_dat[5] ;
    output \ch0_dat[6] ;
    output \ch0_dat[7] ;
    output \ch0_dat[8] ;
    output \ch0_dat[9] ;
    output \ch0_dat[10] ;
    output \ch0_dat[11] ;
    output \ch0_dat[12] ;
    output \ch0_dat[13] ;
    output \ch0_dat[14] ;
    output \ch0_dat[15] ;
    output [15:0]prox_dat;
    input GND_net;
    output n481;
    input n111990;
    output [3:0]cnt_read;
    input n64;
    output \cnt_write[3] ;
    output \cnt_main[2] ;
    input clk_c_enable_100;
    input n1991;
    output \cnt_main[0] ;
    output [3:0]cnt_mode1;
    input clk_c_enable_120;
    input clk_c_enable_124;
    input clk_c_enable_106;
    input n1990;
    input clk_c_enable_149;
    input n109208;
    input clk_c_enable_111;
    input n1989;
    output \cnt_main[1] ;
    output i2c_scl_c;
    output \cnt_start[3] ;
    output ack_flag;
    input n22026;
    input n111256;
    output n22070;
    output n45;
    input rst_n_c;
    input n111209;
    input n109219;
    output n111186;
    input n4;
    input n111202;
    input n109214;
    input n14;
    input n111195;
    output n109217;
    input n67;
    output n81685;
    output n111228;
    output n22;
    output n111217;
    output n111192;
    output n111237;
    output n111254;
    output n111243;
    input n2281;
    output n110126;
    output n111203;
    output n109229;
    output n4_adj_171;
    output n111158;
    output n110385;
    input n22079;
    output n111213;
    output n45_adj_172;
    input n19;
    input n2285;
    output n1984;
    output n324;
    output n110463;
    input n24;
    output n109724;
    output n25;
    input n83242;
    input n110467;
    output n45_adj_173;
    output n40;
    output n4_adj_174;
    input n4_adj_175;
    input n109269;
    output n15273;
    output i2c_sda_N_471;
    input n4_adj_176;
    input n109187;
    
    wire clk_400khz /* synthesis is_clock=1, SET_AS_NETWORK=\u1/clk_400khz */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(47[10:20])
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(19[12:15])
    wire dat_valid /* synthesis is_clock=1, SET_AS_NETWORK=dat_valid */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(31[6:15])
    
    wire i2c_sda_N_464;
    wire [7:0]dat_h;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[66:71])
    
    wire clk_c_enable_20;
    wire [7:0]data_r;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[51:57])
    wire [7:0]dat_l;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[59:64])
    
    wire clk_c_enable_27;
    wire [7:0]data_wr;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[12:19])
    
    wire clk_c_enable_28, n2, clk_c_enable_47, n111270, n111271, clk_c_enable_114, 
        n111279, n111280, n111281, n5;
    wire [3:0]cnt;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[12:15])
    
    wire n7;
    wire [9:0]cnt_400khz;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(48[14:24])
    wire [9:0]n8;
    
    wire clk_400khz_enable_1;
    wire [7:0]reg_data;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[41:49])
    
    wire clk_c_enable_119, n107583, n111248, n117, clk_c_enable_32, 
        n107469, clk_c_enable_11, clk_c_enable_12, clk_c_enable_13, 
        n110468, clk_c_enable_31, n110470, n110471, n110408, n2_adj_2724;
    wire [7:0]reg_addr;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(66[31:39])
    
    wire n112;
    wire [7:0]n91;
    
    wire clk_c_enable_123, n3, clk_c_enable_82, clk_c_enable_83, clk_c_enable_84, 
        clk_c_enable_85, n106844;
    wire [23:0]cnt_delay;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(67[13:22])
    wire [23:0]n483;
    
    wire n106845, n106843, n106842, n106841, n106840, n106839, n106838, 
        n106837, n106827, n106826;
    wire [3:0]cnt_stop;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[81:89])
    
    wire clk_c_enable_108, n7_adj_2725, n7_adj_2726, clk_c_enable_107, 
        n7_adj_2727, n7_adj_2728;
    wire [3:0]cnt_write;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[60:69])
    
    wire clk_c_enable_105, n109192, n109191, n109193, clk_c_enable_103, 
        n111266, n111263, clk_c_enable_116, n1;
    wire [3:0]state_back;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[20:30])
    
    wire i2c_sda_N_455, i2c_sda_N_486, i2c_sda_N_492, n22904, n22901, 
        n7_adj_2729, n109232;
    wire [3:0]cnt_start;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[49:58])
    
    wire n82209;
    wire [3:0]n232;
    
    wire n106825, n106824, n106823, n106822, n106821, n106820, n106819, 
        n107562, n63, n83350, n22875, clk_400khz_N_459, clk_c_enable_110, 
        n111510, n107518, n7_adj_2730;
    wire [3:0]n9;
    
    wire clk_400khz_enable_2, n7_adj_2733;
    wire [3:0]n145;
    
    wire n109178, clk_c_enable_131, clk_400khz_enable_3, n107619, ack, 
        clk_400khz_enable_4, n107512, n110461, n110460, n110462, n110407, 
        n110406, n109613, n109614, n109616, n111255, n110242, n110241, 
        n110474, n111508, n13, n12, n111221, n111618, n111620, 
        n109585, n111617, n111984, n111623, n109617, n5_adj_2734, 
        n110124, n111934, n5_adj_2735, n109239, n7_adj_2736, n111265, 
        n111933, n111931, n83073;
    wire [7:0]n4517;
    
    wire n111930, n111251, n6557, n6, n110317, n110144, n111250, 
        n6_adj_2737, n12_adj_2738, n110316, n110472, n110142, n110146, 
        n21326, n111264, n4536, n106853, n18, n15, n111247, n106852, 
        n106851, n106850, n22757, n7_adj_2739, n106849, n111168, 
        n111210, n6_adj_2740, n106848, n106847, n106846, n71, n111233, 
        n6_adj_2741, n111241, n111214, n22018, n111234, n110318, 
        n111235, n111227, n111238, n111226, n110335, n111253, n109148, 
        n111262, n111261, n111229, n6_adj_2743, n4_adj_2744, n110336, 
        n111231, n111205, n21634, n7_adj_2745, n6_adj_2746, n111245, 
        n109612, n109611, n15_adj_2748, n3_adj_2749, n111624, n110208, 
        n83429, n110337, n109615, n33, n35, n22_adj_2753, n111936, 
        n111935, n111932;
    
    FD1S3AY sda_257 (.D(i2c_sda_N_464), .CK(clk_400khz), .Q(i2c_sda_N_454)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam sda_257.GSR = "ENABLED";
    FD1P3AX dat_h_i0_i0 (.D(data_r[0]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i0.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i0 (.D(data_r[0]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i0.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i0 (.D(n2), .SP(clk_c_enable_28), .CK(clk_c), .Q(data_wr[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i0.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i1 (.D(dat_l[0]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\lux_31__N_657[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i1.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i1 (.D(dat_l[0]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\lux_31__N_754[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i1.GSR = "DISABLED";
    PFUMX i102160 (.BLUT(n111270), .ALUT(n111271), .C0(state[1]), .Z(clk_c_enable_114));
    PFUMX i102166 (.BLUT(n111279), .ALUT(n111280), .C0(cnt_mode2[1]), 
          .Z(n111281));
    FD1P3AX state_back_i0_i0 (.D(n5), .SP(clk_c_enable_99), .CK(clk_c), 
            .Q(\state_back[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_back_i0_i0.GSR = "ENABLED";
    FD1P3AX cnt_i0_i0 (.D(n7), .SP(clk_c_enable_114), .CK(clk_c), .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_i0_i0.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i0 (.D(n8[0]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[0])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i0.GSR = "ENABLED";
    FD1P3AX dat_valid_276 (.D(dat_valid_N_458), .SP(clk_400khz_enable_1), 
            .CK(clk_400khz), .Q(dat_valid)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_valid_276.GSR = "DISABLED";
    FD1S3IX cnt_400khz_2398__i1 (.D(n8[1]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[1])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i1.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i2 (.D(n8[2]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[2])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i2.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i3 (.D(n8[3]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[3])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i3.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i4 (.D(n8[4]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[4])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i4.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i5 (.D(n8[5]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[5])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i5.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i6 (.D(n8[6]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[6])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i6.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i7 (.D(n8[7]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[7])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i7.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i8 (.D(n8[8]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[8])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i8.GSR = "ENABLED";
    FD1S3IX cnt_400khz_2398__i9 (.D(n8[9]), .CK(clk_c), .CD(n22821), .Q(cnt_400khz[9])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398__i9.GSR = "ENABLED";
    FD1P3IX reg_data_i0_i3 (.D(n111248), .SP(clk_c_enable_119), .CD(n107583), 
            .CK(clk_c), .Q(reg_data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_data_i0_i3.GSR = "DISABLED";
    FD1P3JX reg_data_i0_i1 (.D(n111248), .SP(clk_c_enable_119), .PD(n117), 
            .CK(clk_c), .Q(reg_data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_data_i0_i1.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i7 (.D(n107469), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(data_wr[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i7.GSR = "DISABLED";
    FD1P3AX data_r_i0_i7 (.D(i2c_sda_out), .SP(clk_c_enable_11), .CK(clk_c), 
            .Q(data_r[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i7.GSR = "DISABLED";
    FD1P3AX data_r_i0_i6 (.D(i2c_sda_out), .SP(clk_c_enable_12), .CK(clk_c), 
            .Q(data_r[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i6.GSR = "DISABLED";
    FD1P3AX data_r_i0_i5 (.D(i2c_sda_out), .SP(clk_c_enable_13), .CK(clk_c), 
            .Q(data_r[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i5.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i1 (.D(data_r[1]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i1.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i2 (.D(data_r[2]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i2.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i3 (.D(data_r[3]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i3.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i4 (.D(data_r[4]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i4.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i5 (.D(data_r[5]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i5.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i6 (.D(data_r[6]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i6.GSR = "DISABLED";
    FD1P3AX dat_h_i0_i7 (.D(data_r[7]), .SP(clk_c_enable_20), .CK(clk_c), 
            .Q(dat_h[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_h_i0_i7.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i1 (.D(data_r[1]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i1.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i2 (.D(data_r[2]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i2.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i3 (.D(data_r[3]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i3.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i4 (.D(data_r[4]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i4.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i5 (.D(data_r[5]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i5.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i6 (.D(data_r[6]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i6.GSR = "DISABLED";
    FD1P3AX dat_l_i0_i7 (.D(data_r[7]), .SP(clk_c_enable_27), .CK(clk_c), 
            .Q(dat_l[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam dat_l_i0_i7.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i1 (.D(n110468), .SP(clk_c_enable_28), .CK(clk_c), 
            .Q(data_wr[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i1.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i2 (.D(n110470), .SP(clk_c_enable_31), .CK(clk_c), 
            .Q(data_wr[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i2.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i3 (.D(n110471), .SP(clk_c_enable_31), .CK(clk_c), 
            .Q(data_wr[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i3.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i4 (.D(n110408), .SP(clk_c_enable_31), .CK(clk_c), 
            .Q(data_wr[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i4.GSR = "DISABLED";
    FD1P3AX data_wr_i0_i6 (.D(n2_adj_2724), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(data_wr[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_wr_i0_i6.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i2 (.D(dat_l[1]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\lux_31__N_657[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i2.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i3 (.D(dat_l[2]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i3.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i4 (.D(dat_l[3]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i4.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i5 (.D(dat_l[4]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[4] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i5.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i6 (.D(dat_l[5]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[5] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i6.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i7 (.D(dat_l[6]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[6] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i7.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i8 (.D(dat_l[7]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[7] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i8.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i9 (.D(dat_h[0]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[8] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i9.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i10 (.D(dat_h[1]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[9] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i10.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i11 (.D(dat_h[2]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[10] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i11.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i12 (.D(dat_h[3]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[11] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i12.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i13 (.D(dat_h[4]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[12] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i13.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i14 (.D(dat_h[5]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[13] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i14.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i15 (.D(dat_h[6]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[14] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i15.GSR = "DISABLED";
    FD1P3AX ch1_dat_i0_i16 (.D(dat_h[7]), .SP(clk_c_enable_47), .CK(clk_c), 
            .Q(\ch1_dat[15] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch1_dat_i0_i16.GSR = "DISABLED";
    FD1P3AX reg_addr_i0_i1 (.D(n112), .SP(clk_c_enable_126), .CK(clk_c), 
            .Q(reg_addr[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_addr_i0_i1.GSR = "DISABLED";
    FD1P3AX reg_addr_i0_i2 (.D(n91[2]), .SP(clk_c_enable_126), .CK(clk_c), 
            .Q(reg_addr[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_addr_i0_i2.GSR = "DISABLED";
    FD1P3AX reg_addr_i0_i3 (.D(dat_valid_N_458), .SP(clk_c_enable_126), 
            .CK(clk_c), .Q(reg_addr[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_addr_i0_i3.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i2 (.D(dat_l[1]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\lux_31__N_625[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i2.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i3 (.D(dat_l[2]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\lux_31__N_625[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i3.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i4 (.D(dat_l[3]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i4.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i5 (.D(dat_l[4]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[4] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i5.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i6 (.D(dat_l[5]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[5] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i6.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i7 (.D(dat_l[6]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[6] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i7.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i8 (.D(dat_l[7]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[7] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i8.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i9 (.D(dat_h[0]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[8] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i9.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i10 (.D(dat_h[1]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[9] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i10.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i11 (.D(dat_h[2]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[10] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i11.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i12 (.D(dat_h[3]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[11] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i12.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i13 (.D(dat_h[4]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[12] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i13.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i14 (.D(dat_h[5]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[13] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i14.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i15 (.D(dat_h[6]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[14] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i15.GSR = "DISABLED";
    FD1P3AX ch0_dat_i0_i16 (.D(dat_h[7]), .SP(clk_c_enable_65), .CK(clk_c), 
            .Q(\ch0_dat[15] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ch0_dat_i0_i16.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i1 (.D(dat_l[1]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i1.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i2 (.D(dat_l[2]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i2.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i3 (.D(dat_l[3]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i3.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i4 (.D(dat_l[4]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i4.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i5 (.D(dat_l[5]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i5.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i6 (.D(dat_l[6]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i6.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i7 (.D(dat_l[7]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i7.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i8 (.D(dat_h[0]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i8.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i9 (.D(dat_h[1]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i9.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i10 (.D(dat_h[2]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i10.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i11 (.D(dat_h[3]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i11.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i12 (.D(dat_h[4]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i12.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i13 (.D(dat_h[5]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i13.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i14 (.D(dat_h[6]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i14.GSR = "DISABLED";
    FD1P3AX prox_dat_i0_i15 (.D(dat_h[7]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i15.GSR = "DISABLED";
    FD1P3AX reg_data_i0_i7 (.D(n3), .SP(clk_c_enable_119), .CK(clk_c), 
            .Q(reg_data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_data_i0_i7.GSR = "DISABLED";
    FD1P3AX data_r_i0_i4 (.D(i2c_sda_out), .SP(clk_c_enable_82), .CK(clk_c), 
            .Q(data_r[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i4.GSR = "DISABLED";
    FD1P3AX data_r_i0_i3 (.D(i2c_sda_out), .SP(clk_c_enable_83), .CK(clk_c), 
            .Q(data_r[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i3.GSR = "DISABLED";
    FD1P3AX data_r_i0_i2 (.D(i2c_sda_out), .SP(clk_c_enable_84), .CK(clk_c), 
            .Q(data_r[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i2.GSR = "DISABLED";
    FD1P3AX data_r_i0_i1 (.D(i2c_sda_out), .SP(clk_c_enable_85), .CK(clk_c), 
            .Q(data_r[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i1.GSR = "DISABLED";
    CCU2D add_159_7 (.A0(cnt_delay[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106844), .COUT(n106845), .S0(n483[5]), .S1(n483[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_7.INIT0 = 16'h5aaa;
    defparam add_159_7.INIT1 = 16'h5aaa;
    defparam add_159_7.INJECT1_0 = "NO";
    defparam add_159_7.INJECT1_1 = "NO";
    CCU2D add_159_5 (.A0(cnt_delay[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106843), .COUT(n106844), .S0(n483[3]), .S1(n483[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_5.INIT0 = 16'h5aaa;
    defparam add_159_5.INIT1 = 16'h5aaa;
    defparam add_159_5.INJECT1_0 = "NO";
    defparam add_159_5.INJECT1_1 = "NO";
    CCU2D add_159_3 (.A0(cnt_delay[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106842), .COUT(n106843), .S0(n483[1]), .S1(n483[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_3.INIT0 = 16'h5aaa;
    defparam add_159_3.INIT1 = 16'h5aaa;
    defparam add_159_3.INJECT1_0 = "NO";
    defparam add_159_3.INJECT1_1 = "NO";
    CCU2D add_159_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n106842), .S1(n483[0]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_1.INIT0 = 16'hF000;
    defparam add_159_1.INIT1 = 16'h5555;
    defparam add_159_1.INJECT1_0 = "NO";
    defparam add_159_1.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_11 (.A0(cnt_400khz[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106841), .S0(n8[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_11.INIT1 = 16'h0000;
    defparam cnt_400khz_2398_add_4_11.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_9 (.A0(cnt_400khz[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_400khz[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106840), .COUT(n106841), .S0(n8[7]), .S1(n8[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_9.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_7 (.A0(cnt_400khz[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_400khz[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106839), .COUT(n106840), .S0(n8[5]), .S1(n8[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_7.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_5 (.A0(cnt_400khz[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_400khz[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106838), .COUT(n106839), .S0(n8[3]), .S1(n8[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_5.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_3 (.A0(cnt_400khz[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_400khz[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106837), .COUT(n106838), .S0(n8[1]), .S1(n8[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_400khz_2398_add_4_3.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_400khz_2398_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_400khz[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n106837), .S1(n8[0]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(55[18:35])
    defparam cnt_400khz_2398_add_4_1.INIT0 = 16'hF000;
    defparam cnt_400khz_2398_add_4_1.INIT1 = 16'h0555;
    defparam cnt_400khz_2398_add_4_1.INJECT1_0 = "NO";
    defparam cnt_400khz_2398_add_4_1.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106827), .S0(n481));
    defparam sub_2097_add_2_cout.INIT0 = 16'h0000;
    defparam sub_2097_add_2_cout.INIT1 = 16'h0000;
    defparam sub_2097_add_2_cout.INJECT1_0 = "NO";
    defparam sub_2097_add_2_cout.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_18 (.A0(cnt_delay[22]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[23]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106826), .COUT(n106827));
    defparam sub_2097_add_2_18.INIT0 = 16'h5555;
    defparam sub_2097_add_2_18.INIT1 = 16'h5555;
    defparam sub_2097_add_2_18.INJECT1_0 = "NO";
    defparam sub_2097_add_2_18.INJECT1_1 = "NO";
    FD1P3AX cnt_stop_i0_i1 (.D(n7_adj_2725), .SP(clk_c_enable_108), .CK(clk_c), 
            .Q(cnt_stop[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_stop_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_stop_i0_i2 (.D(n7_adj_2726), .SP(clk_c_enable_108), .CK(clk_c), 
            .Q(cnt_stop[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_stop_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_stop_i0_i3 (.D(n111990), .SP(clk_c_enable_108), .CK(clk_c), 
            .Q(cnt_stop[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_stop_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_read_i0_i1 (.D(n64), .SP(clk_c_enable_107), .CK(clk_c), 
            .Q(cnt_read[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_read_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_read_i0_i2 (.D(n7_adj_2727), .SP(clk_c_enable_107), .CK(clk_c), 
            .Q(cnt_read[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_read_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_read_i0_i3 (.D(n7_adj_2728), .SP(clk_c_enable_107), .CK(clk_c), 
            .Q(cnt_read[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_read_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_write_i0_i1 (.D(n109192), .SP(clk_c_enable_105), .CK(clk_c), 
            .Q(cnt_write[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_write_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_write_i0_i2 (.D(n109191), .SP(clk_c_enable_105), .CK(clk_c), 
            .Q(cnt_write[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_write_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_write_i0_i3 (.D(n109193), .SP(clk_c_enable_105), .CK(clk_c), 
            .Q(\cnt_write[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_write_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_mode2_i0_i1 (.D(n111266), .SP(clk_c_enable_103), .CK(clk_c), 
            .Q(cnt_mode2[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode2_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_mode2_i0_i2 (.D(n111281), .SP(clk_c_enable_103), .CK(clk_c), 
            .Q(cnt_mode2[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode2_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_mode2_i0_i3 (.D(n111263), .SP(clk_c_enable_103), .CK(clk_c), 
            .Q(cnt_mode2[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode2_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_main_i0_i2 (.D(n1), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(\cnt_main[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_main_i0_i2.GSR = "ENABLED";
    FD1P3AX state_back_i0_i1 (.D(state[1]), .SP(clk_c_enable_99), .CK(clk_c), 
            .Q(state_back[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_back_i0_i1.GSR = "ENABLED";
    FD1P3AX state_i0_i0 (.D(n1991), .SP(clk_c_enable_100), .CK(clk_c), 
            .Q(state[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_i0_i0.GSR = "ENABLED";
    FD1P3AY i249_283 (.D(i2c_sda_N_492), .SP(i2c_sda_N_486), .CK(clk_400khz), 
            .Q(i2c_sda_N_455)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i249_283.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i0 (.D(n111248), .SP(clk_c_enable_116), .CD(n22904), 
            .CK(clk_c), .Q(\cnt_main[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_main_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_mode1_i0_i0 (.D(n7_adj_2729), .SP(clk_c_enable_120), .CD(n22901), 
            .CK(clk_c), .Q(cnt_mode1[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode1_i0_i0.GSR = "ENABLED";
    FD1P3AX cnt_mode2_i0_i0 (.D(n109232), .SP(clk_c_enable_103), .CK(clk_c), 
            .Q(cnt_mode2[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode2_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_start_i0_i0 (.D(n232[0]), .SP(clk_c_enable_124), .CD(n82209), 
            .CK(clk_c), .Q(cnt_start[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_start_i0_i0.GSR = "ENABLED";
    CCU2D sub_2097_add_2_16 (.A0(cnt_delay[20]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[21]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106825), .COUT(n106826));
    defparam sub_2097_add_2_16.INIT0 = 16'h5555;
    defparam sub_2097_add_2_16.INIT1 = 16'h5555;
    defparam sub_2097_add_2_16.INJECT1_0 = "NO";
    defparam sub_2097_add_2_16.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_14 (.A0(cnt_delay[18]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[19]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106824), .COUT(n106825));
    defparam sub_2097_add_2_14.INIT0 = 16'h5555;
    defparam sub_2097_add_2_14.INIT1 = 16'h5555;
    defparam sub_2097_add_2_14.INJECT1_0 = "NO";
    defparam sub_2097_add_2_14.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_12 (.A0(cnt_delay[16]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[17]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106823), .COUT(n106824));
    defparam sub_2097_add_2_12.INIT0 = 16'h5555;
    defparam sub_2097_add_2_12.INIT1 = 16'h5555;
    defparam sub_2097_add_2_12.INJECT1_0 = "NO";
    defparam sub_2097_add_2_12.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_10 (.A0(cnt_delay[14]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[15]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106822), .COUT(n106823));
    defparam sub_2097_add_2_10.INIT0 = 16'h5555;
    defparam sub_2097_add_2_10.INIT1 = 16'h5555;
    defparam sub_2097_add_2_10.INJECT1_0 = "NO";
    defparam sub_2097_add_2_10.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_8 (.A0(cnt_delay[12]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[13]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106821), .COUT(n106822));
    defparam sub_2097_add_2_8.INIT0 = 16'h5aaa;
    defparam sub_2097_add_2_8.INIT1 = 16'h5555;
    defparam sub_2097_add_2_8.INJECT1_0 = "NO";
    defparam sub_2097_add_2_8.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_6 (.A0(cnt_delay[10]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[11]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106820), .COUT(n106821));
    defparam sub_2097_add_2_6.INIT0 = 16'h5555;
    defparam sub_2097_add_2_6.INIT1 = 16'h5555;
    defparam sub_2097_add_2_6.INJECT1_0 = "NO";
    defparam sub_2097_add_2_6.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_4 (.A0(cnt_delay[8]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[9]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106819), .COUT(n106820));
    defparam sub_2097_add_2_4.INIT0 = 16'h5555;
    defparam sub_2097_add_2_4.INIT1 = 16'h5aaa;
    defparam sub_2097_add_2_4.INJECT1_0 = "NO";
    defparam sub_2097_add_2_4.INJECT1_1 = "NO";
    CCU2D sub_2097_add_2_2 (.A0(cnt_delay[6]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[7]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n106819));
    defparam sub_2097_add_2_2.INIT0 = 16'h5000;
    defparam sub_2097_add_2_2.INIT1 = 16'h5aaa;
    defparam sub_2097_add_2_2.INJECT1_0 = "NO";
    defparam sub_2097_add_2_2.INJECT1_1 = "NO";
    FD1P3AX cnt_write_i0_i0 (.D(n107562), .SP(clk_c_enable_105), .CK(clk_c), 
            .Q(cnt_write[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_write_i0_i0.GSR = "ENABLED";
    FD1P3AX state_i0_i1 (.D(n1990), .SP(clk_c_enable_106), .CK(clk_c), 
            .Q(state[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_read_i0_i0 (.D(n63), .SP(clk_c_enable_107), .CK(clk_c), 
            .Q(cnt_read[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_read_i0_i0.GSR = "ENABLED";
    FD1P3AX cnt_stop_i0_i0 (.D(n83350), .SP(clk_c_enable_108), .CK(clk_c), 
            .Q(cnt_stop[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_stop_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i0 (.D(n483[0]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i0.GSR = "ENABLED";
    FD1S3AX clk_400khz_254 (.D(clk_400khz_N_459), .CK(clk_c), .Q(clk_400khz)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(60[8] 61[30])
    defparam clk_400khz_254.GSR = "ENABLED";
    FD1P3AX state_i0_i3 (.D(n109208), .SP(clk_c_enable_110), .CK(clk_c), 
            .Q(state[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_i0_i3.GSR = "ENABLED";
    FD1P3AX state_i0_i2 (.D(n1989), .SP(clk_c_enable_111), .CK(clk_c), 
            .Q(state[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam state_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_i0_i3 (.D(n111510), .SP(clk_c_enable_114), .CK(clk_c), 
            .Q(cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_i0_i2 (.D(n107518), .SP(clk_c_enable_114), .CK(clk_c), 
            .Q(cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt_i0_i1 (.D(n7_adj_2730), .SP(clk_c_enable_114), .CK(clk_c), 
            .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i3 (.D(n9[3]), .SP(clk_c_enable_116), .CD(n22904), 
            .CK(clk_c), .Q(dat_valid_N_458)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_main_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i1 (.D(n9[1]), .SP(clk_c_enable_116), .CD(n22904), 
            .CK(clk_c), .Q(\cnt_main[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_main_i0_i1.GSR = "ENABLED";
    FD1P3AY scl_256 (.D(n7_adj_2733), .SP(clk_400khz_enable_2), .CK(clk_400khz), 
            .Q(i2c_scl_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam scl_256.GSR = "ENABLED";
    FD1P3IX cnt_mode1_i0_i3 (.D(n145[3]), .SP(clk_c_enable_120), .CD(n22901), 
            .CK(clk_c), .Q(cnt_mode1[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode1_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_mode1_i0_i2 (.D(n145[2]), .SP(clk_c_enable_120), .CD(n22901), 
            .CK(clk_c), .Q(cnt_mode1[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode1_i0_i2.GSR = "ENABLED";
    FD1P3IX reg_data_i0_i0 (.D(\cnt_main[0] ), .SP(clk_c_enable_119), .CD(n117), 
            .CK(clk_c), .Q(reg_data[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_data_i0_i0.GSR = "DISABLED";
    FD1P3IX cnt_mode1_i0_i1 (.D(n145[1]), .SP(clk_c_enable_120), .CD(n22901), 
            .CK(clk_c), .Q(cnt_mode1[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_mode1_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_start_i0_i3 (.D(n232[3]), .SP(clk_c_enable_124), .CD(n82209), 
            .CK(clk_c), .Q(\cnt_start[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_start_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_start_i0_i2 (.D(n232[2]), .SP(clk_c_enable_124), .CD(n82209), 
            .CK(clk_c), .Q(cnt_start[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_start_i0_i2.GSR = "ENABLED";
    FD1P3AX prox_dat_i0_i0 (.D(dat_l[0]), .SP(clk_c_enable_123), .CK(clk_c), 
            .Q(prox_dat[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam prox_dat_i0_i0.GSR = "DISABLED";
    FD1P3IX cnt_start_i0_i1 (.D(n232[1]), .SP(clk_c_enable_124), .CD(n82209), 
            .CK(clk_c), .Q(cnt_start[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_start_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i23 (.D(n483[23]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[23])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i23.GSR = "ENABLED";
    FD1P3AX reg_addr_i0_i0 (.D(n109178), .SP(clk_c_enable_126), .CK(clk_c), 
            .Q(reg_addr[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam reg_addr_i0_i0.GSR = "DISABLED";
    FD1P3IX cnt_delay_i0_i22 (.D(n483[22]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[22])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i22.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i21 (.D(n483[21]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[21])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i21.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i20 (.D(n483[20]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[20])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i20.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i19 (.D(n483[19]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[19])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i19.GSR = "ENABLED";
    FD1P3AX data_r_i0_i0 (.D(i2c_sda_out), .SP(clk_c_enable_131), .CK(clk_c), 
            .Q(data_r[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam data_r_i0_i0.GSR = "DISABLED";
    FD1P3AX ack_flag_259 (.D(n107619), .SP(clk_400khz_enable_3), .CK(clk_400khz), 
            .Q(ack_flag)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ack_flag_259.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i18 (.D(n483[18]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[18])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i18.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i17 (.D(n483[17]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[17])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i17.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i16 (.D(n483[16]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[16])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i16.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i15 (.D(n483[15]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i15.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i14 (.D(n483[14]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i14.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i13 (.D(n483[13]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i13.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i12 (.D(n483[12]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i12.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i11 (.D(n483[11]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i11.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i10 (.D(n483[10]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i10.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i9 (.D(n483[9]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i9.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i8 (.D(n483[8]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i8.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i7 (.D(n483[7]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i7.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i6 (.D(n483[6]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i6.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i5 (.D(n483[5]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i5.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i4 (.D(n483[4]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i4.GSR = "ENABLED";
    FD1P3AX ack_258 (.D(n107512), .SP(clk_400khz_enable_4), .CK(clk_400khz), 
            .Q(ack)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam ack_258.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i3 (.D(n483[3]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i2 (.D(n483[2]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i1 (.D(n483[1]), .SP(clk_c_enable_149), .CD(n22875), 
            .CK(clk_c), .Q(cnt_delay[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam cnt_delay_i0_i1.GSR = "ENABLED";
    PFUMX i102148 (.BLUT(n110461), .ALUT(n110460), .C0(cnt_mode2[0]), 
          .Z(n110462));
    PFUMX i102129 (.BLUT(n110407), .ALUT(n110406), .C0(state[0]), .Z(n110408));
    PFUMX i101528 (.BLUT(n109613), .ALUT(n109614), .C0(cnt[1]), .Z(n109616));
    LUT4 i101896_4_lut (.A(cnt_mode2[3]), .B(n22026), .C(n111256), .D(n111255), 
         .Z(clk_c_enable_20)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
    defparam i101896_4_lut.init = 16'h0020;
    LUT4 n110242_bdd_4_lut (.A(n110242), .B(n110241), .C(state[0]), .D(n22070), 
         .Z(n110474)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam n110242_bdd_4_lut.init = 16'hca00;
    LUT4 cnt_3__bdd_4_lut_102548 (.A(cnt[3]), .B(cnt[0]), .C(cnt[1]), 
         .D(cnt[2]), .Z(n111508)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;
    defparam cnt_3__bdd_4_lut_102548.init = 16'h6aaa;
    LUT4 i101764_4_lut (.A(n13), .B(cnt_400khz[9]), .C(n12), .D(cnt_400khz[4]), 
         .Z(n22821)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(60[11:34])
    defparam i101764_4_lut.init = 16'h0001;
    LUT4 i5_4_lut (.A(cnt_400khz[0]), .B(cnt_400khz[7]), .C(cnt_400khz[8]), 
         .D(cnt_400khz[5]), .Z(n13)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5_4_lut.init = 16'hfffe;
    LUT4 i4_4_lut (.A(cnt_400khz[6]), .B(cnt_400khz[1]), .C(cnt_400khz[3]), 
         .D(cnt_400khz[2]), .Z(n12)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
    defparam i4_4_lut.init = 16'hbfff;
    LUT4 i3_4_lut (.A(cnt_mode2[3]), .B(n22026), .C(n111221), .D(state[1]), 
         .Z(clk_c_enable_27)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i3_4_lut.init = 16'h1000;
    LUT4 n109617_bdd_4_lut_102373 (.A(cnt_write[0]), .B(cnt_write[1]), .C(\cnt_write[3] ), 
         .D(cnt_write[2]), .Z(n111618)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam n109617_bdd_4_lut_102373.init = 16'h0001;
    LUT4 cnt_start_1__bdd_3_lut_102541 (.A(cnt_start[1]), .B(\cnt_start[3] ), 
         .C(cnt_start[2]), .Z(n111620)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;
    defparam cnt_start_1__bdd_3_lut_102541.init = 16'h0101;
    LUT4 cnt_start_1__bdd_2_lut (.A(state[2]), .B(n109585), .Z(n111617)) /* synthesis lut_function=(A (B)) */ ;
    defparam cnt_start_1__bdd_2_lut.init = 16'h8888;
    LUT4 n111622_bdd_3_lut_3_lut (.A(state[0]), .B(state[2]), .C(n111984), 
         .Z(n111623)) /* synthesis lut_function=(A (B (C))+!A ((C)+!B)) */ ;
    defparam n111622_bdd_3_lut_3_lut.init = 16'hd1d1;
    LUT4 n111618_bdd_4_lut (.A(n111618), .B(n109617), .C(n111620), .D(state[0]), 
         .Z(n111984)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
    defparam n111618_bdd_4_lut.init = 16'h88f0;
    LUT4 n15274_bdd_2_lut_102317_3_lut (.A(n111508), .B(state[2]), .C(n5_adj_2734), 
         .Z(n111510)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n15274_bdd_2_lut_102317_3_lut.init = 16'h8080;
    LUT4 state_2__bdd_4_lut_101993 (.A(cnt_mode2[0]), .B(cnt_mode2[1]), 
         .C(cnt_mode2[3]), .D(cnt_mode2[2]), .Z(n110124)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (B (C+(D))+!B (C))) */ ;
    defparam state_2__bdd_4_lut_101993.init = 16'hf4d0;
    LUT4 cnt_start_2__bdd_2_lut (.A(cnt_start[2]), .B(cnt_start[1]), .Z(n111934)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam cnt_start_2__bdd_2_lut.init = 16'h1111;
    LUT4 i1_2_lut (.A(ack), .B(cnt_read[0]), .Z(n5_adj_2735)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut.init = 16'h2222;
    LUT4 i1_2_lut_adj_207 (.A(cnt_start[2]), .B(cnt_start[1]), .Z(n45)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[49:58])
    defparam i1_2_lut_adj_207.init = 16'h8888;
    LUT4 i1_2_lut_adj_208 (.A(\cnt_write[3] ), .B(cnt_write[1]), .Z(n109239)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_adj_208.init = 16'heeee;
    LUT4 i101822_4_lut (.A(state[3]), .B(n7_adj_2736), .C(rst_n_c), .D(n110474), 
         .Z(clk_c_enable_28)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i101822_4_lut.init = 16'h1000;
    LUT4 i1_2_lut_3_lut_4_lut_then_4_lut (.A(cnt_mode2[1]), .B(cnt_mode2[0]), 
         .C(state[1]), .D(cnt_mode2[2]), .Z(n111265)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i1_2_lut_3_lut_4_lut_then_4_lut.init = 16'h0040;
    LUT4 cnt_start_2__bdd_3_lut (.A(cnt_write[1]), .B(cnt_write[2]), .C(cnt_write[0]), 
         .Z(n111933)) /* synthesis lut_function=(!(A (B+(C))+!A !(B+(C)))) */ ;
    defparam cnt_start_2__bdd_3_lut.init = 16'h5656;
    LUT4 cnt_stop_1__bdd_3_lut (.A(cnt_read[0]), .B(cnt_read[2]), .C(cnt_read[1]), 
         .Z(n111931)) /* synthesis lut_function=(!(A (B+(C))+!A !(B (C)))) */ ;
    defparam cnt_stop_1__bdd_3_lut.init = 16'h4242;
    LUT4 reg_addr_1__bdd_4_lut (.A(reg_addr[1]), .B(n83073), .C(n4517[1]), 
         .D(state[0]), .Z(n110468)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
    defparam reg_addr_1__bdd_4_lut.init = 16'h88f0;
    LUT4 cnt_stop_1__bdd_3_lut_102530 (.A(cnt_stop[1]), .B(cnt_stop[3]), 
         .C(cnt_stop[2]), .Z(n111930)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam cnt_stop_1__bdd_3_lut_102530.init = 16'h0202;
    LUT4 i101526_3_lut (.A(data_wr[1]), .B(data_wr[0]), .C(cnt[0]), .Z(n109614)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101526_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut (.A(cnt_mode2[2]), .B(n111209), .C(n111251), .D(state[0]), 
         .Z(n7_adj_2736)) /* synthesis lut_function=(A (B)+!A (B+(C (D)))) */ ;
    defparam i1_4_lut.init = 16'hdccc;
    LUT4 i1_2_lut_adj_209 (.A(state[1]), .B(state[2]), .Z(n22070)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_adj_209.init = 16'h2222;
    LUT4 n6557_bdd_4_lut (.A(n6557), .B(n6), .C(\cnt_write[3] ), .D(state[0]), 
         .Z(n110317)) /* synthesis lut_function=(A (B (D)+!B (C (D)))) */ ;
    defparam n6557_bdd_4_lut.init = 16'ha800;
    LUT4 n109239_bdd_2_lut_101994 (.A(cnt_start[2]), .B(\cnt_start[3] ), 
         .Z(n110144)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam n109239_bdd_2_lut_101994.init = 16'h1111;
    LUT4 i3_4_lut_adj_210 (.A(dat_valid_N_458), .B(n111250), .C(\cnt_main[2] ), 
         .D(n109219), .Z(clk_c_enable_47)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i3_4_lut_adj_210.init = 16'h0800;
    LUT4 n6557_bdd_4_lut_102075 (.A(n6_adj_2737), .B(cnt_read[3]), .C(state[0]), 
         .D(n12_adj_2738), .Z(n110316)) /* synthesis lut_function=(!(A (C+!(D))+!A ((C+!(D))+!B))) */ ;
    defparam n6557_bdd_4_lut_102075.init = 16'h0e00;
    LUT4 i101525_3_lut (.A(data_wr[3]), .B(data_wr[2]), .C(cnt[0]), .Z(n109613)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101525_3_lut.init = 16'hcaca;
    LUT4 n110145_bdd_3_lut (.A(n110472), .B(n110142), .C(state[1]), .Z(n110146)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n110145_bdd_3_lut.init = 16'hcaca;
    LUT4 i13944_4_lut_4_lut (.A(cnt_mode2[0]), .B(cnt_mode2[1]), .C(cnt_mode2[3]), 
         .D(cnt_mode2[2]), .Z(n21326)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B (C+(D))+!B (C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(123[7] 136[14])
    defparam i13944_4_lut_4_lut.init = 16'h0106;
    LUT4 mux_2076_i1_4_lut (.A(reg_addr[0]), .B(reg_data[0]), .C(cnt_mode1[0]), 
         .D(cnt_mode1[1]), .Z(n4517[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_2076_i1_4_lut.init = 16'hca0a;
    LUT4 i1_2_lut_3_lut_4_lut_else_4_lut (.A(cnt_mode2[1]), .B(cnt_mode2[0]), 
         .C(state[1]), .Z(n111264)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_else_4_lut.init = 16'h6060;
    LUT4 mux_2076_i4_4_lut (.A(reg_addr[3]), .B(reg_data[3]), .C(cnt_mode1[0]), 
         .D(cnt_mode1[1]), .Z(n4517[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_2076_i4_4_lut.init = 16'hca0a;
    LUT4 mux_2076_i3_4_lut (.A(reg_addr[2]), .B(reg_data[7]), .C(cnt_mode1[0]), 
         .D(cnt_mode1[1]), .Z(n4517[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_2076_i3_4_lut.init = 16'hca0a;
    LUT4 i2_3_lut (.A(dat_valid_N_458), .B(n111186), .C(\cnt_main[1] ), 
         .Z(n107583)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_3_lut.init = 16'h1010;
    LUT4 i2_4_lut (.A(n4536), .B(n4), .C(n21326), .D(state[0]), .Z(clk_c_enable_32)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;
    defparam i2_4_lut.init = 16'hc088;
    CCU2D add_159_25 (.A0(cnt_delay[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106853), .S0(n483[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_25.INIT0 = 16'h5aaa;
    defparam add_159_25.INIT1 = 16'h0000;
    defparam add_159_25.INJECT1_0 = "NO";
    defparam add_159_25.INJECT1_1 = "NO";
    LUT4 i3_4_lut_adj_211 (.A(n22070), .B(n111202), .C(state[3]), .D(n18), 
         .Z(clk_c_enable_31)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i3_4_lut_adj_211.init = 16'h0800;
    LUT4 i31_4_lut (.A(n4536), .B(cnt_mode2[3]), .C(state[0]), .D(n15), 
         .Z(n18)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;
    defparam i31_4_lut.init = 16'h3a0a;
    LUT4 mux_178_Mux_6_i2_4_lut (.A(reg_data[7]), .B(n21326), .C(state[0]), 
         .D(n111247), .Z(n2_adj_2724)) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam mux_178_Mux_6_i2_4_lut.init = 16'hcacf;
    LUT4 i1_2_lut_adj_212 (.A(\cnt_main[1] ), .B(dat_valid_N_458), .Z(n112)) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_adj_212.init = 16'h2222;
    LUT4 i75601_2_lut (.A(\cnt_main[2] ), .B(dat_valid_N_458), .Z(n91[2])) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(89[7] 103[14])
    defparam i75601_2_lut.init = 16'h2222;
    LUT4 i75617_2_lut (.A(\cnt_main[0] ), .B(\cnt_main[1] ), .Z(n3)) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(89[7] 103[14])
    defparam i75617_2_lut.init = 16'h2222;
    CCU2D add_159_23 (.A0(cnt_delay[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106852), .COUT(n106853), .S0(n483[21]), 
          .S1(n483[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_23.INIT0 = 16'h5aaa;
    defparam add_159_23.INIT1 = 16'h5aaa;
    defparam add_159_23.INJECT1_0 = "NO";
    defparam add_159_23.INJECT1_1 = "NO";
    CCU2D add_159_21 (.A0(cnt_delay[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106851), .COUT(n106852), .S0(n483[19]), 
          .S1(n483[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_21.INIT0 = 16'h5aaa;
    defparam add_159_21.INIT1 = 16'h5aaa;
    defparam add_159_21.INJECT1_0 = "NO";
    defparam add_159_21.INJECT1_1 = "NO";
    CCU2D add_159_19 (.A0(cnt_delay[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106850), .COUT(n106851), .S0(n483[17]), 
          .S1(n483[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_19.INIT0 = 16'h5aaa;
    defparam add_159_19.INIT1 = 16'h5aaa;
    defparam add_159_19.INJECT1_0 = "NO";
    defparam add_159_19.INJECT1_1 = "NO";
    LUT4 i75540_3_lut (.A(cnt_stop[1]), .B(n22757), .C(cnt_stop[0]), .Z(n7_adj_2725)) /* synthesis lut_function=(!(A (B+(C))+!A (B+!(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i75540_3_lut.init = 16'h1212;
    LUT4 i4_4_lut_adj_213 (.A(n7_adj_2739), .B(state[1]), .C(state[0]), 
         .D(state[2]), .Z(n22757)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
    defparam i4_4_lut_adj_213.init = 16'hbfff;
    PFUMX i102156 (.BLUT(n111264), .ALUT(n111265), .C0(cnt_mode2[3]), 
          .Z(n111266));
    CCU2D add_159_17 (.A0(cnt_delay[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106849), .COUT(n106850), .S0(n483[15]), 
          .S1(n483[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_17.INIT0 = 16'h5aaa;
    defparam add_159_17.INIT1 = 16'h5aaa;
    defparam add_159_17.INJECT1_0 = "NO";
    defparam add_159_17.INJECT1_1 = "NO";
    LUT4 i101816_2_lut_2_lut (.A(n111168), .B(clk_c_enable_106), .Z(clk_c_enable_110)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i101816_2_lut_2_lut.init = 16'h4444;
    LUT4 i1_4_lut_rep_1110 (.A(n109214), .B(n14), .C(state[2]), .D(cnt_mode2[0]), 
         .Z(n111168)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i1_4_lut_rep_1110.init = 16'h0008;
    LUT4 reg_addr_2__bdd_4_lut (.A(reg_addr[2]), .B(n83073), .C(n4517[2]), 
         .D(state[0]), .Z(n110470)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
    defparam reg_addr_2__bdd_4_lut.init = 16'h88f0;
    LUT4 reg_addr_3__bdd_4_lut (.A(reg_addr[3]), .B(n83073), .C(n4517[3]), 
         .D(state[0]), .Z(n110471)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
    defparam reg_addr_3__bdd_4_lut.init = 16'h88f0;
    LUT4 i101497_4_lut (.A(n5_adj_2735), .B(n111210), .C(state[0]), .D(n6_adj_2740), 
         .Z(n109585)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C)))) */ ;
    defparam i101497_4_lut.init = 16'h3a30;
    LUT4 i2_4_lut_adj_214 (.A(cnt_stop[0]), .B(cnt_stop[3]), .C(cnt_stop[2]), 
         .D(cnt_stop[1]), .Z(n7_adj_2739)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2_4_lut_adj_214.init = 16'hfcec;
    LUT4 i1_2_lut_3_lut (.A(state[2]), .B(n5_adj_2734), .C(cnt[0]), .Z(n7)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i1_2_lut_3_lut.init = 16'h0808;
    LUT4 i1_3_lut_4_lut (.A(state[2]), .B(n5_adj_2734), .C(cnt[1]), .D(cnt[0]), 
         .Z(n7_adj_2730)) /* synthesis lut_function=(!(((C (D)+!C !(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i1_3_lut_4_lut.init = 16'h0880;
    CCU2D add_159_15 (.A0(cnt_delay[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106848), .COUT(n106849), .S0(n483[13]), 
          .S1(n483[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_15.INIT0 = 16'h5aaa;
    defparam add_159_15.INIT1 = 16'h5aaa;
    defparam add_159_15.INJECT1_0 = "NO";
    defparam add_159_15.INJECT1_1 = "NO";
    CCU2D add_159_13 (.A0(cnt_delay[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106847), .COUT(n106848), .S0(n483[11]), 
          .S1(n483[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_13.INIT0 = 16'h5aaa;
    defparam add_159_13.INIT1 = 16'h5aaa;
    defparam add_159_13.INJECT1_0 = "NO";
    defparam add_159_13.INJECT1_1 = "NO";
    CCU2D add_159_11 (.A0(cnt_delay[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106846), .COUT(n106847), .S0(n483[9]), .S1(n483[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_11.INIT0 = 16'h5aaa;
    defparam add_159_11.INIT1 = 16'h5aaa;
    defparam add_159_11.INJECT1_0 = "NO";
    defparam add_159_11.INJECT1_1 = "NO";
    CCU2D add_159_9 (.A0(cnt_delay[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106845), .COUT(n106846), .S0(n483[7]), .S1(n483[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(212[29:45])
    defparam add_159_9.INIT0 = 16'h5aaa;
    defparam add_159_9.INIT1 = 16'h5aaa;
    defparam add_159_9.INJECT1_0 = "NO";
    defparam add_159_9.INJECT1_1 = "NO";
    LUT4 i1_3_lut_4_lut_4_lut_then_4_lut (.A(state[2]), .B(state[0]), .C(n111195), 
         .D(n12_adj_2738), .Z(n111271)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i1_3_lut_4_lut_4_lut_then_4_lut.init = 16'h0200;
    LUT4 i101893_2_lut_3_lut (.A(dat_valid_N_458), .B(n111186), .C(\cnt_main[1] ), 
         .Z(n117)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;
    defparam i101893_2_lut_3_lut.init = 16'h0101;
    LUT4 i75541_4_lut (.A(cnt_stop[2]), .B(n22757), .C(cnt_stop[1]), .D(cnt_stop[0]), 
         .Z(n7_adj_2726)) /* synthesis lut_function=(!(A (B+(C (D)))+!A (B+!(C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i75541_4_lut.init = 16'h1222;
    LUT4 i2_3_lut_rep_1128 (.A(\cnt_main[2] ), .B(n22026), .C(state[1]), 
         .Z(n111186)) /* synthesis lut_function=(A+(B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_3_lut_rep_1128.init = 16'hfefe;
    LUT4 i101890_2_lut_rep_1123_4_lut (.A(\cnt_main[2] ), .B(n22026), .C(state[1]), 
         .D(dat_valid_N_458), .Z(clk_c_enable_119)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101890_2_lut_rep_1123_4_lut.init = 16'h0001;
    LUT4 i2_3_lut_4_lut_4_lut_4_lut (.A(n111195), .B(n109217), .C(cnt_mode1[2]), 
         .D(n67), .Z(n81685)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i2_3_lut_4_lut_4_lut_4_lut.init = 16'h4000;
    LUT4 i1_3_lut_4_lut_4_lut (.A(n111195), .B(state[2]), .C(n71), .D(n111228), 
         .Z(n82209)) /* synthesis lut_function=(!(A+(B ((D)+!C)+!B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_3_lut_4_lut_4_lut.init = 16'h0051;
    LUT4 i1_3_lut_4_lut_adj_215 (.A(state[2]), .B(n6557), .C(n111233), 
         .D(cnt_write[2]), .Z(n109191)) /* synthesis lut_function=(!((B+(C (D)+!C !(D)))+!A)) */ ;
    defparam i1_3_lut_4_lut_adj_215.init = 16'h0220;
    LUT4 i1_3_lut_4_lut_adj_216 (.A(state[2]), .B(n6557), .C(n6_adj_2741), 
         .D(\cnt_write[3] ), .Z(n109193)) /* synthesis lut_function=(!((B+(C (D)+!C !(D)))+!A)) */ ;
    defparam i1_3_lut_4_lut_adj_216.init = 16'h0220;
    LUT4 i101905_2_lut_4_lut (.A(n111241), .B(n12_adj_2738), .C(state[2]), 
         .D(cnt_read[0]), .Z(n63)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i101905_2_lut_4_lut.init = 16'h0010;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt_stop[0]), .B(n111210), .C(state[1]), 
         .D(state[2]), .Z(n22)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C))+!A ((D)+!C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(204[8:12])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h20f0;
    LUT4 i15394_3_lut_4_lut_4_lut (.A(n111217), .B(n111214), .C(state[0]), 
         .D(n111209), .Z(n22904)) /* synthesis lut_function=(!(A+(B (D)+!B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i15394_3_lut_4_lut_4_lut.init = 16'h0045;
    LUT4 i101900_3_lut_4_lut_4_lut_4_lut (.A(state[0]), .B(state[1]), .C(state[2]), 
         .D(n111195), .Z(clk_c_enable_108)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B+(C+(D))))) */ ;
    defparam i101900_3_lut_4_lut_4_lut_4_lut.init = 16'h0081;
    LUT4 n109239_bdd_4_lut_102351 (.A(n109239), .B(cnt_write[0]), .C(n110144), 
         .D(state[0]), .Z(n110472)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ;
    defparam n109239_bdd_4_lut_102351.init = 16'h11f0;
    LUT4 i1_3_lut_4_lut_4_lut_else_4_lut (.A(state[2]), .B(state[0]), .C(n6557), 
         .D(n111195), .Z(n111270)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B+(D)))) */ ;
    defparam i1_3_lut_4_lut_4_lut_else_4_lut.init = 16'h0091;
    LUT4 i101770_4_lut_4_lut (.A(n111228), .B(state[2]), .C(n22018), .D(state[3]), 
         .Z(clk_400khz_enable_3)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B (C+(D))+!B (D)))) */ ;
    defparam i101770_4_lut_4_lut.init = 16'h001d;
    LUT4 i1_2_lut_3_lut_4_lut_adj_217 (.A(cnt[2]), .B(n111234), .C(n110318), 
         .D(cnt[3]), .Z(n5_adj_2734)) /* synthesis lut_function=(!(A (B+((D)+!C))+!A ((D)+!C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[12:15])
    defparam i1_2_lut_3_lut_4_lut_adj_217.init = 16'h0070;
    LUT4 i75591_3_lut_4_lut (.A(n111235), .B(cnt_read[2]), .C(cnt_read[3]), 
         .D(n111192), .Z(n7_adj_2728)) /* synthesis lut_function=(!(A (B (C+(D))+!B ((D)+!C))+!A ((D)+!C))) */ ;
    defparam i75591_3_lut_4_lut.init = 16'h0078;
    LUT4 i75500_4_lut_4_lut (.A(state[2]), .B(n111228), .C(n110146), .D(state[3]), 
         .Z(i2c_sda_N_486)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B+(D)))) */ ;
    defparam i75500_4_lut_4_lut.init = 16'h00b1;
    LUT4 i3_3_lut_4_lut (.A(\cnt_write[3] ), .B(n111227), .C(cnt_write[0]), 
         .D(n111237), .Z(n22018)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(159[7] 171[14])
    defparam i3_3_lut_4_lut.init = 16'hfffb;
    LUT4 i75353_4_lut_4_lut (.A(n111238), .B(dat_valid_N_458), .C(\cnt_main[2] ), 
         .D(state[0]), .Z(n1)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (C (D))) */ ;
    defparam i75353_4_lut_4_lut.init = 16'hda00;
    LUT4 i2_3_lut_4_lut (.A(\cnt_main[2] ), .B(n111250), .C(dat_valid_N_458), 
         .D(n109219), .Z(clk_c_enable_123)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_3_lut_4_lut.init = 16'h0800;
    LUT4 i101846_2_lut_rep_1141_2_lut_3_lut_4_lut (.A(state[1]), .B(n111254), 
         .C(n22821), .D(clk_400khz), .Z(clk_c_enable_116)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101846_2_lut_rep_1141_2_lut_3_lut_4_lut.init = 16'h0010;
    LUT4 n109239_bdd_3_lut_102115_4_lut (.A(cnt_read[1]), .B(n111243), .C(state[0]), 
         .D(n111226), .Z(n110142)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D))))) */ ;
    defparam n109239_bdd_3_lut_102115_4_lut.init = 16'h01f1;
    LUT4 n83370_bdd_3_lut_102085_4_lut (.A(cnt_read[1]), .B(n111243), .C(state[0]), 
         .D(cnt_read[2]), .Z(n110335)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam n83370_bdd_3_lut_102085_4_lut.init = 16'hfffe;
    LUT4 n15274_bdd_2_lut_102024_3_lut (.A(n110124), .B(state[2]), .C(n2281), 
         .Z(n110126)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;
    defparam n15274_bdd_2_lut_102024_3_lut.init = 16'he0e0;
    LUT4 i1_3_lut_4_lut_adj_218 (.A(cnt_mode2[0]), .B(n111253), .C(state[2]), 
         .D(cnt_mode2[3]), .Z(n109148)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i1_3_lut_4_lut_adj_218.init = 16'h0004;
    LUT4 i1_4_lut_then_3_lut (.A(state[1]), .B(cnt_mode2[1]), .C(cnt_mode2[2]), 
         .Z(n111262)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i1_4_lut_then_3_lut.init = 16'h0202;
    LUT4 i1_4_lut_else_3_lut (.A(state[1]), .B(cnt_mode2[1]), .C(cnt_mode2[2]), 
         .D(cnt_mode2[0]), .Z(n111261)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i1_4_lut_else_3_lut.init = 16'h8000;
    LUT4 i1_2_lut_3_lut_adj_219 (.A(\cnt_main[0] ), .B(\cnt_main[2] ), .C(dat_valid_N_458), 
         .Z(n109178)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i1_2_lut_3_lut_adj_219.init = 16'h0202;
    LUT4 i75370_2_lut_rep_1168 (.A(cnt_stop[3]), .B(cnt_stop[1]), .Z(n111226)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i75370_2_lut_rep_1168.init = 16'heeee;
    LUT4 i2_2_lut_rep_1152_3_lut (.A(cnt_stop[3]), .B(cnt_stop[1]), .C(cnt_stop[2]), 
         .Z(n111210)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i2_2_lut_rep_1152_3_lut.init = 16'hefef;
    LUT4 i1_2_lut_rep_1145_3_lut_4_lut (.A(cnt_stop[3]), .B(cnt_stop[1]), 
         .C(cnt_stop[0]), .D(cnt_stop[2]), .Z(n111203)) /* synthesis lut_function=(A+(B+!(C (D)))) */ ;
    defparam i1_2_lut_rep_1145_3_lut_4_lut.init = 16'hefff;
    LUT4 i75721_2_lut_rep_1169 (.A(cnt_write[2]), .B(cnt_write[1]), .Z(n111227)) /* synthesis lut_function=(A (B)) */ ;
    defparam i75721_2_lut_rep_1169.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_4_lut_adj_220 (.A(cnt_write[2]), .B(cnt_write[1]), 
         .C(cnt_write[0]), .D(\cnt_write[3] ), .Z(n109229)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_220.init = 16'hff7f;
    LUT4 i101213_3_lut_4_lut (.A(cnt_write[2]), .B(cnt_write[1]), .C(\cnt_write[3] ), 
         .D(cnt_write[0]), .Z(n4_adj_171)) /* synthesis lut_function=(!(A (B (C+(D))+!B (C))+!A (C))) */ ;
    defparam i101213_3_lut_4_lut.init = 16'h070f;
    LUT4 i11406_2_lut_rep_1170 (.A(state[0]), .B(state[1]), .Z(n111228)) /* synthesis lut_function=(A+(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i11406_2_lut_rep_1170.init = 16'heeee;
    LUT4 i1_2_lut_rep_1100_3_lut (.A(state[0]), .B(state[1]), .C(n481), 
         .Z(n111158)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i1_2_lut_rep_1100_3_lut.init = 16'hefef;
    LUT4 i74747_3_lut_4_lut (.A(cnt_start[1]), .B(cnt_start[0]), .C(cnt_start[2]), 
         .D(\cnt_start[3] ), .Z(n232[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i74747_3_lut_4_lut.init = 16'h7f80;
    LUT4 i20_2_lut_3_lut (.A(cnt_start[1]), .B(cnt_start[0]), .C(cnt_start[2]), 
         .Z(n232[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i20_2_lut_3_lut.init = 16'h7878;
    LUT4 i1_2_lut_rep_1171 (.A(\cnt_start[3] ), .B(cnt_start[1]), .Z(n111229)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_1171.init = 16'heeee;
    LUT4 n6_bdd_3_lut_4_lut (.A(\cnt_start[3] ), .B(cnt_start[1]), .C(cnt_start[2]), 
         .D(cnt_start[0]), .Z(n110385)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam n6_bdd_3_lut_4_lut.init = 16'h1000;
    LUT4 i2_2_lut_4_lut (.A(cnt_stop[1]), .B(cnt_stop[3]), .C(cnt_stop[2]), 
         .D(state[2]), .Z(n6_adj_2743)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (D)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i2_2_lut_4_lut.init = 16'hfd00;
    LUT4 cnt_mode2_0__bdd_2_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .Z(n110407)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam cnt_mode2_0__bdd_2_lut.init = 16'h4444;
    LUT4 i1_2_lut_3_lut_adj_221 (.A(cnt_write[0]), .B(cnt_write[2]), .C(\cnt_write[3] ), 
         .Z(n4_adj_2744)) /* synthesis lut_function=(!(A (C)+!A (B+(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_adj_221.init = 16'h0b0b;
    LUT4 n83370_bdd_3_lut_4_lut (.A(cnt_write[0]), .B(cnt_write[2]), .C(state[0]), 
         .D(n109239), .Z(n110336)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam n83370_bdd_3_lut_4_lut.init = 16'hffbf;
    LUT4 i1_2_lut_rep_1173 (.A(cnt_read[2]), .B(cnt_read[1]), .Z(n111231)) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i1_2_lut_rep_1173.init = 16'h2222;
    LUT4 i2_2_lut_3_lut (.A(cnt_read[2]), .B(cnt_read[1]), .C(cnt_read[3]), 
         .Z(n6_adj_2740)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i2_2_lut_3_lut.init = 16'h0202;
    LUT4 i3359_2_lut_rep_1175 (.A(cnt_write[0]), .B(cnt_write[1]), .Z(n111233)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3359_2_lut_rep_1175.init = 16'h8888;
    LUT4 i3355_2_lut_3_lut (.A(cnt_write[0]), .B(cnt_write[1]), .C(cnt_write[2]), 
         .Z(n6_adj_2741)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i3355_2_lut_3_lut.init = 16'h8080;
    LUT4 i3042_2_lut_3_lut (.A(cnt_write[0]), .B(cnt_write[1]), .C(cnt_write[2]), 
         .Z(n6)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ;
    defparam i3042_2_lut_3_lut.init = 16'hf8f8;
    LUT4 i1_2_lut_rep_1176 (.A(cnt[0]), .B(cnt[1]), .Z(n111234)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_rep_1176.init = 16'h8888;
    LUT4 i1_2_lut_rep_1147_3_lut_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cnt[3]), 
         .D(cnt[2]), .Z(n111205)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_rep_1147_3_lut_4_lut.init = 16'hf8f0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_222 (.A(cnt[0]), .B(cnt[1]), .C(n22079), 
         .D(cnt[2]), .Z(clk_c_enable_131)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_222.init = 16'h8000;
    LUT4 i2_4_lut_adj_223 (.A(state[1]), .B(state[2]), .C(n111195), .D(state[0]), 
         .Z(clk_c_enable_105)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B (C+(D))))) */ ;
    defparam i2_4_lut_adj_223.init = 16'h0401;
    LUT4 i3446_2_lut_rep_1177 (.A(cnt_read[0]), .B(cnt_read[1]), .Z(n111235)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3446_2_lut_rep_1177.init = 16'h8888;
    LUT4 i3445_2_lut_rep_1155_3_lut (.A(cnt_read[0]), .B(cnt_read[1]), .C(cnt_read[2]), 
         .Z(n111213)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i3445_2_lut_rep_1155_3_lut.init = 16'h8080;
    LUT4 i2801_2_lut_3_lut (.A(cnt_read[0]), .B(cnt_read[1]), .C(cnt_read[2]), 
         .Z(n6_adj_2737)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ;
    defparam i2801_2_lut_3_lut.init = 16'hf8f8;
    LUT4 i75586_3_lut_4_lut (.A(cnt_read[0]), .B(cnt_read[1]), .C(n111192), 
         .D(cnt_read[2]), .Z(n7_adj_2727)) /* synthesis lut_function=(!(A (B (C+(D))+!B (C+!(D)))+!A (C+!(D)))) */ ;
    defparam i75586_3_lut_4_lut.init = 16'h0708;
    LUT4 i1_2_lut_rep_1179 (.A(state[0]), .B(state[1]), .Z(n111237)) /* synthesis lut_function=((B)+!A) */ ;
    defparam i1_2_lut_rep_1179.init = 16'hdddd;
    LUT4 i101767_4_lut_4_lut (.A(state[0]), .B(state[1]), .C(n21634), 
         .D(n111254), .Z(clk_400khz_enable_4)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B ((D)+!C)+!B (D)))) */ ;
    defparam i101767_4_lut_4_lut.init = 16'h00d1;
    LUT4 i3361_2_lut_rep_1180 (.A(\cnt_main[0] ), .B(\cnt_main[1] ), .Z(n111238)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3361_2_lut_rep_1180.init = 16'h8888;
    LUT4 i3360_3_lut_rep_1156_4_lut (.A(\cnt_main[0] ), .B(\cnt_main[1] ), 
         .C(\cnt_main[2] ), .D(dat_valid_N_458), .Z(n111214)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
    defparam i3360_3_lut_rep_1156_4_lut.init = 16'hf800;
    LUT4 i3505_3_lut_4_lut (.A(\cnt_main[0] ), .B(\cnt_main[1] ), .C(\cnt_main[2] ), 
         .D(dat_valid_N_458), .Z(n9[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;
    defparam i3505_3_lut_4_lut.init = 16'h7f80;
    LUT4 i101825_2_lut_3_lut (.A(cnt_mode2[0]), .B(cnt_mode2[1]), .C(cnt_mode2[2]), 
         .Z(n83073)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101825_2_lut_3_lut.init = 16'h0404;
    LUT4 i75486_3_lut_4_lut (.A(cnt_mode2[0]), .B(cnt_mode2[1]), .C(cnt_mode2[2]), 
         .D(reg_addr[0]), .Z(n7_adj_2745)) /* synthesis lut_function=(A (C)+!A (B (C+(D))+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i75486_3_lut_4_lut.init = 16'hf4f0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_224 (.A(cnt_write[1]), .B(cnt_write[0]), 
         .C(n6557), .D(state[2]), .Z(n109192)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A ((C+!(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(157[32:48])
    defparam i1_2_lut_3_lut_4_lut_adj_224.init = 16'h0600;
    LUT4 i11335_2_lut_rep_1183 (.A(state[0]), .B(state[1]), .Z(n111241)) /* synthesis lut_function=(A+!(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i11335_2_lut_rep_1183.init = 16'hbbbb;
    LUT4 i2_3_lut_rep_1134_4_lut (.A(state[0]), .B(state[1]), .C(state[2]), 
         .D(n12_adj_2738), .Z(n111192)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i2_3_lut_rep_1134_4_lut.init = 16'hffbf;
    LUT4 i2_2_lut_3_lut_4_lut (.A(cnt[1]), .B(cnt[2]), .C(cnt[0]), .D(n22079), 
         .Z(clk_c_enable_85)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[12:15])
    defparam i2_2_lut_3_lut_4_lut.init = 16'h0800;
    LUT4 i1_2_lut_3_lut_4_lut_adj_225 (.A(cnt[2]), .B(cnt[1]), .C(n22079), 
         .D(cnt[0]), .Z(clk_c_enable_84)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_225.init = 16'h2000;
    LUT4 i1_2_lut_3_lut_4_lut_adj_226 (.A(cnt[2]), .B(cnt[1]), .C(cnt[0]), 
         .D(n22079), .Z(clk_c_enable_83)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_226.init = 16'h0200;
    LUT4 i1_2_lut_3_lut_4_lut_adj_227 (.A(cnt[1]), .B(cnt[2]), .C(n22079), 
         .D(cnt[0]), .Z(clk_c_enable_82)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_227.init = 16'h2000;
    LUT4 i1_2_lut_3_lut_4_lut_adj_228 (.A(cnt[1]), .B(cnt[2]), .C(cnt[0]), 
         .D(n22079), .Z(clk_c_enable_13)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_3_lut_4_lut_adj_228.init = 16'h0200;
    LUT4 i75693_2_lut_rep_1185 (.A(cnt_read[0]), .B(cnt_read[3]), .Z(n111243)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i75693_2_lut_rep_1185.init = 16'heeee;
    LUT4 cnt_mode2_0__bdd_3_lut (.A(cnt_mode2[0]), .B(cnt_mode2[2]), .C(cnt_mode2[1]), 
         .Z(n110406)) /* synthesis lut_function=(A (B+!(C))+!A (B)) */ ;
    defparam cnt_mode2_0__bdd_3_lut.init = 16'hcece;
    LUT4 i1_2_lut_3_lut_4_lut_adj_229 (.A(cnt[1]), .B(cnt[2]), .C(n22079), 
         .D(cnt[0]), .Z(clk_c_enable_12)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_229.init = 16'h1000;
    LUT4 i1_2_lut_3_lut_4_lut_adj_230 (.A(cnt[1]), .B(cnt[2]), .C(cnt[0]), 
         .D(n22079), .Z(clk_c_enable_11)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_230.init = 16'h0100;
    LUT4 i1_4_lut_adj_231 (.A(n111209), .B(state[1]), .C(n111254), .D(state[0]), 
         .Z(clk_c_enable_103)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B (C+(D))))) */ ;
    defparam i1_4_lut_adj_231.init = 16'h0401;
    LUT4 n6_bdd_3_lut_102131_4_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), 
         .C(cnt_mode1[3]), .D(cnt_mode1[2]), .Z(n110242)) /* synthesis lut_function=(!(A (C+(D))+!A ((C+(D))+!B))) */ ;
    defparam n6_bdd_3_lut_102131_4_lut.init = 16'h000e;
    LUT4 i1_2_lut_3_lut_4_lut_adj_232 (.A(cnt_mode1[1]), .B(cnt_mode1[0]), 
         .C(cnt_mode1[2]), .D(cnt_mode1[3]), .Z(n4536)) /* synthesis lut_function=(!(A (C+(D))+!A ((C+(D))+!B))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_232.init = 16'h000e;
    LUT4 i3358_2_lut_3_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .C(cnt_mode1[2]), 
         .Z(n6_adj_2746)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;
    defparam i3358_2_lut_3_lut.init = 16'he0e0;
    LUT4 i75832_2_lut_rep_1187 (.A(cnt_mode2[0]), .B(cnt_mode2[1]), .Z(n111245)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i75832_2_lut_rep_1187.init = 16'heeee;
    LUT4 n6_bdd_3_lut_102032_4_lut (.A(cnt_mode2[0]), .B(cnt_mode2[1]), 
         .C(cnt_mode2[2]), .D(cnt_mode2[3]), .Z(n110241)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C+(D))+!B ((D)+!C)))) */ ;
    defparam n6_bdd_3_lut_102032_4_lut.init = 16'h001e;
    LUT4 i13950_2_lut_rep_1189 (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .Z(n111247)) /* synthesis lut_function=(A (B)) */ ;
    defparam i13950_2_lut_rep_1189.init = 16'h8888;
    LUT4 i2_3_lut_4_lut_adj_233 (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .C(reg_data[7]), 
         .D(state[0]), .Z(n107469)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i2_3_lut_4_lut_adj_233.init = 16'h0080;
    LUT4 i3534_3_lut_4_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .C(cnt_mode1[2]), 
         .D(cnt_mode1[3]), .Z(n145[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;
    defparam i3534_3_lut_4_lut.init = 16'h7f80;
    LUT4 i3527_2_lut_3_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .C(cnt_mode1[2]), 
         .Z(n145[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;
    defparam i3527_2_lut_3_lut.init = 16'h7878;
    LUT4 i9367_1_lut_rep_1190 (.A(\cnt_main[0] ), .Z(n111248)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(89[7] 103[14])
    defparam i9367_1_lut_rep_1190.init = 16'h5555;
    LUT4 i47_4_lut_4_lut_4_lut (.A(\cnt_main[0] ), .B(\cnt_main[1] ), .C(dat_valid_N_458), 
         .D(\cnt_main[2] ), .Z(n45_adj_172)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (C+(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(89[7] 103[14])
    defparam i47_4_lut_4_lut_4_lut.init = 16'hf5d0;
    LUT4 i1_2_lut_rep_1192 (.A(\cnt_main[1] ), .B(\cnt_main[0] ), .Z(n111250)) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i1_2_lut_rep_1192.init = 16'h2222;
    LUT4 i3551_2_lut_rep_1193 (.A(cnt_mode2[1]), .B(cnt_mode2[0]), .Z(n111251)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(121[25:41])
    defparam i3551_2_lut_rep_1193.init = 16'h8888;
    LUT4 i32_3_lut_4_lut_3_lut (.A(cnt_mode2[1]), .B(cnt_mode2[0]), .C(cnt_mode2[2]), 
         .Z(n15)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C)+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(121[25:41])
    defparam i32_3_lut_4_lut_3_lut.init = 16'h1616;
    LUT4 i1_2_lut_rep_1195 (.A(cnt_mode2[2]), .B(cnt_mode2[1]), .Z(n111253)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_1195.init = 16'h8888;
    LUT4 i1_2_lut_rep_1163_3_lut (.A(cnt_mode2[2]), .B(cnt_mode2[1]), .C(cnt_mode2[0]), 
         .Z(n111221)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i1_2_lut_rep_1163_3_lut.init = 16'h0808;
    LUT4 i101623_3_lut_4_lut_4_lut (.A(ack_flag), .B(n19), .C(n2285), 
         .D(state_back[1]), .Z(n1984)) /* synthesis lut_function=(!(A ((C)+!B)+!A !(B ((D)+!C)+!B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i101623_3_lut_4_lut_4_lut.init = 16'h5c0c;
    LUT4 i75344_2_lut_2_lut (.A(ack_flag), .B(\state_back[0] ), .Z(n324)) /* synthesis lut_function=(!(A+!(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i75344_2_lut_2_lut.init = 16'h4444;
    LUT4 i10657_2_lut_rep_1196 (.A(state[2]), .B(state[3]), .Z(n111254)) /* synthesis lut_function=(A+(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i10657_2_lut_rep_1196.init = 16'heeee;
    LUT4 i1_2_lut_rep_1159_3_lut (.A(state[2]), .B(state[3]), .C(state[1]), 
         .Z(n111217)) /* synthesis lut_function=(A+(B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i1_2_lut_rep_1159_3_lut.init = 16'hfefe;
    PFUMX mux_178_Mux_0_i2 (.BLUT(n4517[0]), .ALUT(n7_adj_2745), .C0(state[0]), 
          .Z(n2)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=18, LSE_RCOL=3, LSE_LLINE=34, LSE_RLINE=44 */ ;
    LUT4 i1_2_lut_rep_1197 (.A(cnt_mode2[0]), .B(state[1]), .Z(n111255)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i1_2_lut_rep_1197.init = 16'hbbbb;
    LUT4 i101854_2_lut_2_lut_3_lut_4_lut (.A(cnt_mode2[0]), .B(state[1]), 
         .C(cnt_mode2[3]), .D(n111256), .Z(n109232)) /* synthesis lut_function=(!(A+!(B ((D)+!C)))) */ ;
    defparam i101854_2_lut_2_lut_3_lut_4_lut.init = 16'h4404;
    LUT4 i101524_2_lut (.A(data_wr[4]), .Z(n109612)) /* synthesis lut_function=(A) */ ;
    defparam i101524_2_lut.init = 16'haaaa;
    LUT4 mux_2076_i2_4_lut (.A(reg_addr[1]), .B(reg_data[1]), .C(cnt_mode1[0]), 
         .D(cnt_mode1[1]), .Z(n4517[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_2076_i2_4_lut.init = 16'hca0a;
    LUT4 n110462_bdd_3_lut (.A(n110462), .B(state_back[1]), .C(state[2]), 
         .Z(n110463)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n110462_bdd_3_lut.init = 16'hcaca;
    LUT4 i101523_3_lut (.A(data_wr[7]), .B(data_wr[6]), .C(cnt[0]), .Z(n109611)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101523_3_lut.init = 16'hcaca;
    LUT4 i101797_4_lut (.A(n24), .B(n15_adj_2748), .C(ack_flag), .D(n2285), 
         .Z(n109724)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B (C (D))))) */ ;
    defparam i101797_4_lut.init = 16'h0511;
    LUT4 i1_4_lut_adj_234 (.A(n25), .B(n3_adj_2749), .C(n109214), .D(n109148), 
         .Z(n15_adj_2748)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_234.init = 16'hfaea;
    LUT4 i2_4_lut_adj_235 (.A(cnt_mode2[3]), .B(n111245), .C(state[2]), 
         .D(cnt_mode2[2]), .Z(n3_adj_2749)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i2_4_lut_adj_235.init = 16'h0002;
    LUT4 cnt_mode2_2__bdd_4_lut_102388 (.A(cnt_mode2[2]), .B(cnt_mode2[3]), 
         .C(state[1]), .D(cnt_mode2[1]), .Z(n110461)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (((D)+!C)+!B))) */ ;
    defparam cnt_mode2_2__bdd_4_lut_102388.init = 16'h2040;
    LUT4 i2c_sda_I_0_4_lut (.A(i2c_sda_out), .B(n111624), .C(i2c_sda_N_486), 
         .D(state[3]), .Z(i2c_sda_N_464)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2c_sda_I_0_4_lut.init = 16'h0aca;
    LUT4 i1_2_lut_adj_236 (.A(state[1]), .B(state[0]), .Z(n5)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i1_2_lut_adj_236.init = 16'h8888;
    LUT4 cnt_mode2_2__bdd_3_lut_102387 (.A(cnt_mode2[2]), .B(cnt_mode2[3]), 
         .C(cnt_mode2[1]), .Z(n110460)) /* synthesis lut_function=(!(A (B)+!A ((C)+!B))) */ ;
    defparam cnt_mode2_2__bdd_3_lut_102387.init = 16'h2626;
    LUT4 i2_4_lut_adj_237 (.A(n110208), .B(state[0]), .C(n111195), .D(n83242), 
         .Z(n25)) /* synthesis lut_function=(A (B (C+!(D)))) */ ;
    defparam i2_4_lut_adj_237.init = 16'h8088;
    LUT4 i74725_3_lut (.A(n83429), .B(n110467), .C(state[0]), .Z(n45_adj_173)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i74725_3_lut.init = 16'hc5c5;
    LUT4 i74724_4_lut (.A(n71), .B(n111213), .C(state[1]), .D(cnt_read[3]), 
         .Z(n83429)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(68[13:18])
    defparam i74724_4_lut.init = 16'hfaca;
    PFUMX i102086 (.BLUT(n110336), .ALUT(n110335), .C0(state[1]), .Z(n110337));
    LUT4 i1_4_lut_adj_238 (.A(\cnt_start[3] ), .B(cnt_start[2]), .C(cnt_start[1]), 
         .D(cnt_start[0]), .Z(n71)) /* synthesis lut_function=(A+(B (C+(D)))) */ ;
    defparam i1_4_lut_adj_238.init = 16'heeea;
    LUT4 i2_3_lut_adj_239 (.A(state[3]), .B(n110337), .C(state[2]), .Z(i2c_sda_N_492)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i2_3_lut_adj_239.init = 16'hefef;
    LUT4 i15392_4_lut (.A(clk_c_enable_120), .B(cnt_mode1[3]), .C(n6_adj_2746), 
         .D(state[1]), .Z(n22901)) /* synthesis lut_function=(A (B+(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i15392_4_lut.init = 16'ha8aa;
    LUT4 cnt_main_1__bdd_4_lut_102016 (.A(\cnt_main[1] ), .B(\cnt_main[0] ), 
         .C(dat_valid_N_458), .D(\cnt_main[2] ), .Z(n110208)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B+((D)+!C)))) */ ;
    defparam cnt_main_1__bdd_4_lut_102016.init = 16'h02b0;
    LUT4 i3518_1_lut (.A(cnt_mode1[0]), .Z(n7_adj_2729)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(107[25:41])
    defparam i3518_1_lut.init = 16'h5555;
    LUT4 i3576_1_lut (.A(cnt_start[0]), .Z(n232[0])) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(140[25:41])
    defparam i3576_1_lut.init = 16'h5555;
    LUT4 i9523_4_lut (.A(\cnt_write[3] ), .B(n6_adj_2741), .C(n6), .D(n111205), 
         .Z(n6557)) /* synthesis lut_function=(A+(B (C+(D))+!B !((D)+!C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(155[16] 158[10])
    defparam i9523_4_lut.init = 16'heefa;
    LUT4 i101909_3_lut (.A(state[2]), .B(cnt_write[0]), .C(n6557), .Z(n107562)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i101909_3_lut.init = 16'h0202;
    LUT4 i101802_2_lut (.A(cnt_stop[0]), .B(n22757), .Z(n83350)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i101802_2_lut.init = 16'h1111;
    LUT4 i15386_3_lut (.A(clk_c_enable_149), .B(n481), .C(state[3]), .Z(n22875)) /* synthesis lut_function=(A (B+!(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i15386_3_lut.init = 16'h8a8a;
    LUT4 i1_2_lut_adj_240 (.A(clk_400khz), .B(n22821), .Z(clk_400khz_N_459)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i1_2_lut_adj_240.init = 16'h6666;
    LUT4 i1_4_lut_adj_241 (.A(n111213), .B(cnt_read[3]), .C(n6_adj_2737), 
         .D(n111205), .Z(n12_adj_2738)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+!((D)+!C))) */ ;
    defparam i1_4_lut_adj_241.init = 16'heefc;
    L6MUX21 i101529 (.D0(n109615), .D1(n109616), .SD(cnt[2]), .Z(n109617));
    PFUMX i102076 (.BLUT(n110317), .ALUT(n110316), .C0(state[1]), .Z(n110318));
    LUT4 i44_4_lut (.A(n111168), .B(ack_flag), .C(n2285), .D(n25), .Z(n40)) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
    defparam i44_4_lut.init = 16'hcfca;
    LUT4 i1_4_lut_adj_242 (.A(state[2]), .B(state[3]), .C(n45_adj_173), 
         .D(n111158), .Z(n4_adj_174)) /* synthesis lut_function=(A (B+(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_242.init = 16'heca8;
    LUT4 i2_4_lut_adj_243 (.A(n22070), .B(state[0]), .C(cnt_mode1[0]), 
         .D(n4_adj_175), .Z(n109217)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i2_4_lut_adj_243.init = 16'h0002;
    LUT4 i2_4_lut_adj_244 (.A(state[2]), .B(n5_adj_2734), .C(n111234), 
         .D(cnt[2]), .Z(n107518)) /* synthesis lut_function=(!(((C (D)+!C !(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(77[12] 216[6])
    defparam i2_4_lut_adj_244.init = 16'h0880;
    LUT4 i3491_2_lut (.A(\cnt_main[1] ), .B(\cnt_main[0] ), .Z(n9[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(88[24:39])
    defparam i3491_2_lut.init = 16'h6666;
    LUT4 i101773_4_lut (.A(state[3]), .B(n5), .C(n33), .D(n6_adj_2743), 
         .Z(clk_400khz_enable_2)) /* synthesis lut_function=(!(A+(B ((D)+!C)+!B !(C)))) */ ;
    defparam i101773_4_lut.init = 16'h1050;
    LUT4 i1_4_lut_adj_245 (.A(state[2]), .B(n35), .C(n111228), .D(n111229), 
         .Z(n33)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(C)) */ ;
    defparam i1_4_lut_adj_245.init = 16'h8d8f;
    LUT4 i1_4_lut_adj_246 (.A(state[0]), .B(state[1]), .C(n4_adj_2744), 
         .D(n22_adj_2753), .Z(n35)) /* synthesis lut_function=(A (B+(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_246.init = 16'heca8;
    LUT4 i1_4_lut_adj_247 (.A(cnt_read[3]), .B(cnt_read[0]), .C(cnt_read[2]), 
         .D(cnt_read[1]), .Z(n22_adj_2753)) /* synthesis lut_function=(!(A+!(B+(C (D)+!C !(D))))) */ ;
    defparam i1_4_lut_adj_247.init = 16'h5445;
    LUT4 i75492_4_lut (.A(n111936), .B(n111231), .C(state[2]), .D(n109269), 
         .Z(n7_adj_2733)) /* synthesis lut_function=(A+(B ((D)+!C)+!B !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i75492_4_lut.init = 16'hefaf;
    LUT4 i3520_2_lut (.A(cnt_mode1[1]), .B(cnt_mode1[0]), .Z(n145[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(107[25:41])
    defparam i3520_2_lut.init = 16'h6666;
    LUT4 i27_2_lut (.A(cnt_start[0]), .B(cnt_start[1]), .Z(n232[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(65[49:58])
    defparam i27_2_lut.init = 16'h6666;
    LUT4 i2_3_lut_adj_248 (.A(state[2]), .B(i2c_sda_out), .C(n22018), 
         .Z(n107619)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i2_3_lut_adj_248.init = 16'h0808;
    LUT4 i2_3_lut_adj_249 (.A(state[1]), .B(cnt_mode2[1]), .C(n21634), 
         .Z(n107512)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut_adj_249.init = 16'h8080;
    LUT4 i3_4_lut_adj_250 (.A(cnt_mode2[0]), .B(state[0]), .C(cnt_mode2[3]), 
         .D(cnt_mode2[2]), .Z(n21634)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(78[4] 215[11])
    defparam i3_4_lut_adj_250.init = 16'h0800;
    LUT4 i101902_3_lut_4_lut_4_lut_4_lut (.A(state[0]), .B(state[1]), .C(state[2]), 
         .D(n111195), .Z(clk_c_enable_107)) /* synthesis lut_function=(!(A+(B ((D)+!C)+!B (C+(D))))) */ ;
    defparam i101902_3_lut_4_lut_4_lut_4_lut.init = 16'h0041;
    L6MUX21 i102535 (.D0(n111935), .D1(n111932), .SD(state[1]), .Z(n111936));
    PFUMX i102533 (.BLUT(n111934), .ALUT(n111933), .C0(state[0]), .Z(n111935));
    LUT4 i9175_1_lut (.A(i2c_sda_N_455), .Z(n15273)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(70[2] 217[5])
    defparam i9175_1_lut.init = 16'h5555;
    PFUMX i102531 (.BLUT(n111931), .ALUT(n111930), .C0(state[0]), .Z(n111932));
    PFUMX i102154 (.BLUT(n111261), .ALUT(n111262), .C0(cnt_mode2[3]), 
          .Z(n111263));
    LUT4 i1_3_lut_4_lut_then_4_lut (.A(state[1]), .B(cnt_mode2[3]), .C(cnt_mode2[0]), 
         .D(cnt_mode2[2]), .Z(n111280)) /* synthesis lut_function=(!((B+(C (D)+!C !(D)))+!A)) */ ;
    defparam i1_3_lut_4_lut_then_4_lut.init = 16'h0220;
    LUT4 i1_3_lut (.A(cnt_stop[3]), .B(cnt_stop[2]), .C(cnt_stop[1]), 
         .Z(i2c_sda_N_471)) /* synthesis lut_function=(A+(B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/rpr0521rs_driver.v(198[7] 206[14])
    defparam i1_3_lut.init = 16'heaea;
    LUT4 i1_3_lut_4_lut_else_4_lut (.A(state[1]), .B(cnt_mode2[3]), .C(cnt_mode2[2]), 
         .Z(n111279)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i1_3_lut_4_lut_else_4_lut.init = 16'h2020;
    PFUMX i102363 (.BLUT(n111623), .ALUT(n111617), .C0(state[1]), .Z(n111624));
    LUT4 i3_4_lut_adj_251 (.A(n4_adj_176), .B(rst_n_c), .C(state[3]), 
         .D(n109187), .Z(clk_400khz_enable_1)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i3_4_lut_adj_251.init = 16'h0800;
    PFUMX i101527 (.BLUT(n109611), .ALUT(n109612), .C0(cnt[1]), .Z(n109615));
    
endmodule
//
// Verilog Description of module decoder
//

module decoder (dat_valid, prox_dat, \ch0_dat[13] , \ch0_dat[12] , GND_net, 
            \ch0_dat[14] , \ch0_dat[11] , \ch0_dat[10] , \ch0_dat[3] , 
            \lux_31__N_754[0] , \ch0_dat[4] , \lux_31__N_625[2] , \ch0_dat[9] , 
            \ch0_dat[8] , \lux_31__N_576[16] , \lux_31__N_576[17] , \lux_31__N_511[25] , 
            \lux_31__N_543[25] , lux_31__N_575, \lux[25] , \lux_31__N_511[17] , 
            \lux_31__N_543[17] , \lux[17] , \ch0_dat[7] , \ch0_dat[6] , 
            \ch0_dat[5] , \lux_31__N_625[3] , \lux_31__N_657[0] , \lux_31__N_657[1] , 
            \ch1_dat[15] , \ch1_dat[14] , \ch1_dat[13] , \ch1_dat[12] , 
            \ch1_dat[11] , \ch1_dat[10] , \ch1_dat[8] , \ch1_dat[9] , 
            \ch1_dat[6] , \ch1_dat[7] , \ch1_dat[4] , \ch1_dat[5] , 
            \ch1_dat[2] , \ch1_dat[3] , \ch0_dat[15] , \lux_31__N_576[14] , 
            \lux_31__N_576[15] , \lux_31__N_576[12] , \lux_31__N_576[13] , 
            \lux_31__N_576[10] , \lux_31__N_576[11] , \lux_31__N_576[8] , 
            \lux_31__N_576[9] , \lux_31__N_576[7] , \lux_31__N_754[24] , 
            \lux_31__N_754[25] , \lux_31__N_754[22] , \lux_31__N_754[23] , 
            \lux_31__N_754[20] , \lux_31__N_754[21] , \lux_31__N_754[18] , 
            \lux_31__N_754[19] , \lux_31__N_754[16] , \lux_31__N_754[17] , 
            \lux_31__N_754[14] , \lux_31__N_754[15] , \lux_31__N_754[12] , 
            \lux_31__N_754[13] , \lux_31__N_754[10] , \lux_31__N_754[11] , 
            \lux_31__N_754[9] , lux_31__N_753, \lux_31__N_754[6] , \lux_31__N_754[7] , 
            \lux_31__N_754[5] , n15077, n15075, n15076, n15073, n15074, 
            \lux_31__N_543[27] , \lux_31__N_543[26] , n15072, \lux_31__N_543[23] , 
            \lux_31__N_543[24] , \lux_31__N_543[21] , \lux_31__N_543[22] , 
            \lux_31__N_543[19] , \lux_31__N_543[20] , \lux_31__N_543[18] , 
            \lux_31__N_543[15] , \lux_31__N_543[16] , \lux_31__N_543[13] , 
            \lux_31__N_543[14] , \lux_31__N_543[11] , \lux_31__N_543[12] , 
            \lux_31__N_543[9] , \lux_31__N_543[10] , \lux_31__N_543[7] , 
            \lux_31__N_543[8] , n15066, n15065, \lux_31__N_543[5] , 
            \lux_31__N_543[6] , \lux_31__N_543[3] , \lux_31__N_543[4] , 
            \lux_31__N_543[2] , n15069, n15070, n15068, \lux_31__N_511[18] , 
            led_c_4, led_c_3, led_c_2, \lux_31__N_511[27] , n486, 
            n2359, \lux_31__N_576[5] , \lux_31__N_576[3] , \lux_31__N_576[4] , 
            \lux_31__N_576[2] , \lux_31__N_511[10] , n2356, n21676, 
            \lux_31__N_511[19] , \lux[19] , \lux_31__N_511[26] , \lux[26] , 
            n15187, n15185, n15186, \lux[18] , n15183, n15184, n15181, 
            n15182, n111166, n8, n16, n111170, n12, n14, n15179, 
            n15180, n15177, n15178, n15175, n15176, n15173, n15174, 
            n13, n12_adj_111, n111197, n10, n111190, n111191, n15171, 
            n15172, n15169, n15170, \lux_31__N_754[3] , n8_adj_112, 
            n15168, n111222, led_c_7, n6, n5, n111219, n12_adj_113, 
            \lux_31__N_754[2] , \lux_31__N_511[9] , \lux[9] , led_c_1, 
            led_c_5, \lux_31__N_511[8] , \lux[8] , \lux_31__N_511[7] , 
            \lux[7] , \lux_31__N_511[6] , \lux[6] , \lux_31__N_511[5] , 
            \lux[5] , \lux_31__N_511[4] , \lux[4] , \lux_31__N_511[3] , 
            \lux[3] , \lux_31__N_576[24] , \lux_31__N_576[25] , \lux_31__N_576[22] , 
            \lux_31__N_576[23] , \lux_31__N_576[20] , \lux_31__N_576[21] , 
            \lux_31__N_511[2] , \lux[2] , \lux_31__N_511[20] , \lux[20] , 
            \lux_31__N_511[21] , \lux[21] , \lux_31__N_511[22] , \lux[22] , 
            \lux_31__N_511[23] , \lux[23] , \lux_31__N_511[24] , \lux[24] , 
            \lux_31__N_576[18] , \lux_31__N_576[19] , \lux[10] , \lux_31__N_511[11] , 
            \lux[11] , \lux_31__N_511[12] , \lux[12] , \lux_31__N_511[13] , 
            \lux[13] , \lux_31__N_511[14] , \lux[14] , \lux_31__N_511[15] , 
            \lux[15] , \lux_31__N_511[16] , \lux[16] , bcd_code_31__N_965, 
            n110806, n5695, n110905, n6295, bcd_code_31__N_960, n111044, 
            n110966, n110278, bcd_code_31__N_1130, bcd_code_31__N_1134, 
            n111067, n5740, n6358, n6354, rst_n_c, n110534, bcd_code_31__N_841, 
            bcd_code_31__N_855, bcd_code_31__N_851, bcd_code_31__N_859, 
            n6264, n5653, bcd_code_31__N_797, n110788, n6268, n110521, 
            n110506, n110515, n110514, n110491, n110497, n110490, 
            n16726, bcd_code_31__N_2024, n110559, n110530, n110533, 
            n110545, n110547, n14_adj_114, n14_adj_115, bcd_code_31__N_1042, 
            n110980, n110885, n14_adj_116, n83313, n110532, n7, 
            n110481, n14_adj_117, bcd_code_31__N_1180, n14_adj_118, 
            bcd_code_31__N_1129, n107666, bcd_code_31__N_961, n14_adj_119, 
            n111031, n23, n16565, n7_adj_120, n5948, bcd_code_31__N_1078, 
            n110476, n110546, n14_adj_121, bcd_code_31__N_1079, bcd_code_31__N_1083, 
            n111075, n5845, n5465, bcd_code_31__N_1029, n111092, \lux_data[15] , 
            n110513, bcd_code_31__N_895, n110282, n14_adj_122, n110480, 
            n110487, n16456, bcd_code_31__N_900, n14_adj_123, n14_adj_124, 
            n7_adj_125, bcd_code_31__N_987, n14_adj_126, bcd_code_31__N_896, 
            n107670, n16625, n111113, n14_adj_127, bcd_code_31__N_951, 
            n14_adj_128, n23_adj_129, n7_adj_130, bcd_code_31__N_850, 
            n111082, n110522, n110485, n110520, bcd_code_31__N_913, 
            n110484, n110281, bcd_code_31__N_886, n110285, n110284, 
            n110289, n110720, n110568, n110582, n110567, n16700, 
            bcd_code_31__N_1519, \lux[27] , n83413, n110486, n110478, 
            n110930, n23_adj_131, n110482, n14_adj_132, n4, n110475, 
            n110721, bcd_code_31__N_1384, n110701, \lux_data[11] , n107662, 
            n14_adj_133, n7_adj_134, n110523, n14_adj_135, n110535, 
            n14_adj_136, n14_adj_137, n110524, bcd_code_31__N_1769, 
            bcd_code_31__N_1773, n110965, n5621, n110536, n110507, 
            n110508, n14_adj_138, bcd_code_31__N_1845, bcd_code_31__N_1849, 
            n110952, n5502, \lux_data[31] , bcd_code_31__N_1973, bcd_code_31__N_1914, 
            bcd_code_31__N_1918, n110936, n5022, n14_adj_139, bcd_code_31__N_1974, 
            bcd_code_31__N_1978, n110921, n5660, n110269, n14_adj_140, 
            \bcd_code_31__N_1380[2] , bcd_code_31__N_2025, bcd_code_31__N_2029, 
            n110902, n5260, n7_adj_141, bcd_code_31__N_2067, bcd_code_31__N_2071, 
            n110884, n5292, n16584, n83307, n14_adj_142, bcd_code_31__N_2100, 
            bcd_code_31__N_2104, n110868, n5181, n14_adj_143, n14_adj_144, 
            n14_adj_145, n16558, n107664, n7_adj_146, n7_adj_147, 
            bcd_code_31__N_795, n14_adj_148, bcd_code_31__N_1257, n7_adj_149, 
            n14_adj_150, n14_adj_151, n110557, n110556, n110558, bcd_code_31__N_1913, 
            n110495, n110494, n7_adj_152, n16471, n16601, n110592, 
            n83295, n14_adj_153, n16738, n110591, bcd_code_31__N_2138, 
            n16428, n83319, \lux_data[7] , n110493, n922, n110578, 
            n110496, n110581, n110817, n14_adj_154, n110580, n14_adj_155, 
            n107668, bcd_code_31__N_2124, bcd_code_31__N_2128, n110850, 
            n5141, n14_adj_156, n14_adj_157, n14_adj_158, n14_adj_159, 
            n7_adj_160, bcd_code_31__N_1030, bcd_code_31__N_1034, n111081, 
            n5916, n107675, n14_adj_161, n7_adj_162, n14_adj_163, 
            n16300, n110504, n110503, \lux_data[3] , n110505, n110566, 
            bcd_code_31__N_988, bcd_code_31__N_992, n111089, n6021, 
            \lux_data[23] , n110489, bcd_code_31__N_1844, \lux_data[27] , 
            n83415, bcd_code_31__N_952, bcd_code_31__N_956, n111098, 
            n6059, bcd_code_31__N_1768, n6291, n110272, bcd_code_31__N_914, 
            bcd_code_31__N_918, n111102, n5329, n14_adj_164, n107610, 
            n7_adj_165, n14_adj_166, n14_adj_167, n7_adj_168, n14_adj_169, 
            n16550, n14_adj_170, bcd_code_31__N_1140, bcd_code_31__N_1690, 
            bcd_code_31__N_887, bcd_code_31__N_891, n111108, n5433, 
            n16351, bcd_code_31__N_798, bcd_code_31__N_860, bcd_code_31__N_864, 
            n111110, n5548, bcd_code_31__N_2099, bcd_code_31__N_1588, 
            bcd_code_31__N_1394, bcd_code_31__N_1450, \lux_data[19] , 
            bcd_code_31__N_1246, n110276, bcd_code_31__N_1047, bcd_code_31__N_1366, 
            bcd_code_31__N_1043, bcd_code_31__N_1392, n83303, bcd_code_31__N_1691, 
            bcd_code_31__N_1695, n110987, n5701, n110944, bcd_code_31__N_842, 
            bcd_code_31__N_846, n111115, n5804, bcd_code_31__N_1306, 
            n83327, bcd_code_31__N_1589, bcd_code_31__N_1593, n110994, 
            n5956, bcd_code_31__N_1520, bcd_code_31__N_1524, n111006, 
            n5470, bcd_code_31__N_1451, bcd_code_31__N_1455, n111016, 
            n5988, bcd_code_31__N_2066, bcd_code_31__N_1367, bcd_code_31__N_1371, 
            n111026, n5369, n16541, bcd_code_31__N_1307, bcd_code_31__N_1311, 
            n111037, n5883, n110979, n110275, bcd_code_31__N_1247, 
            bcd_code_31__N_1251, n111050, n5225, bcd_code_31__N_1181, 
            bcd_code_31__N_1185, n111059, n5401) /* synthesis syn_module_defined=1 */ ;
    input dat_valid;
    input [15:0]prox_dat;
    input \ch0_dat[13] ;
    input \ch0_dat[12] ;
    input GND_net;
    input \ch0_dat[14] ;
    input \ch0_dat[11] ;
    input \ch0_dat[10] ;
    input \ch0_dat[3] ;
    input \lux_31__N_754[0] ;
    input \ch0_dat[4] ;
    input \lux_31__N_625[2] ;
    input \ch0_dat[9] ;
    input \ch0_dat[8] ;
    output \lux_31__N_576[16] ;
    output \lux_31__N_576[17] ;
    output \lux_31__N_511[25] ;
    output \lux_31__N_543[25] ;
    input lux_31__N_575;
    output \lux[25] ;
    output \lux_31__N_511[17] ;
    output \lux_31__N_543[17] ;
    output \lux[17] ;
    input \ch0_dat[7] ;
    input \ch0_dat[6] ;
    input \ch0_dat[5] ;
    input \lux_31__N_625[3] ;
    input \lux_31__N_657[0] ;
    input \lux_31__N_657[1] ;
    input \ch1_dat[15] ;
    input \ch1_dat[14] ;
    input \ch1_dat[13] ;
    input \ch1_dat[12] ;
    input \ch1_dat[11] ;
    input \ch1_dat[10] ;
    input \ch1_dat[8] ;
    input \ch1_dat[9] ;
    input \ch1_dat[6] ;
    input \ch1_dat[7] ;
    input \ch1_dat[4] ;
    input \ch1_dat[5] ;
    input \ch1_dat[2] ;
    input \ch1_dat[3] ;
    input \ch0_dat[15] ;
    output \lux_31__N_576[14] ;
    output \lux_31__N_576[15] ;
    output \lux_31__N_576[12] ;
    output \lux_31__N_576[13] ;
    output \lux_31__N_576[10] ;
    output \lux_31__N_576[11] ;
    output \lux_31__N_576[8] ;
    output \lux_31__N_576[9] ;
    output \lux_31__N_576[7] ;
    output \lux_31__N_754[24] ;
    output \lux_31__N_754[25] ;
    output \lux_31__N_754[22] ;
    output \lux_31__N_754[23] ;
    output \lux_31__N_754[20] ;
    output \lux_31__N_754[21] ;
    output \lux_31__N_754[18] ;
    output \lux_31__N_754[19] ;
    output \lux_31__N_754[16] ;
    output \lux_31__N_754[17] ;
    output \lux_31__N_754[14] ;
    output \lux_31__N_754[15] ;
    output \lux_31__N_754[12] ;
    output \lux_31__N_754[13] ;
    output \lux_31__N_754[10] ;
    output \lux_31__N_754[11] ;
    output \lux_31__N_754[9] ;
    input lux_31__N_753;
    output \lux_31__N_754[6] ;
    output \lux_31__N_754[7] ;
    output \lux_31__N_754[5] ;
    output n15077;
    output n15075;
    output n15076;
    output n15073;
    output n15074;
    output \lux_31__N_543[27] ;
    output \lux_31__N_543[26] ;
    output n15072;
    output \lux_31__N_543[23] ;
    output \lux_31__N_543[24] ;
    output \lux_31__N_543[21] ;
    output \lux_31__N_543[22] ;
    output \lux_31__N_543[19] ;
    output \lux_31__N_543[20] ;
    output \lux_31__N_543[18] ;
    output \lux_31__N_543[15] ;
    output \lux_31__N_543[16] ;
    output \lux_31__N_543[13] ;
    output \lux_31__N_543[14] ;
    output \lux_31__N_543[11] ;
    output \lux_31__N_543[12] ;
    output \lux_31__N_543[9] ;
    output \lux_31__N_543[10] ;
    output \lux_31__N_543[7] ;
    output \lux_31__N_543[8] ;
    output n15066;
    output n15065;
    output \lux_31__N_543[5] ;
    output \lux_31__N_543[6] ;
    output \lux_31__N_543[3] ;
    output \lux_31__N_543[4] ;
    output \lux_31__N_543[2] ;
    output n15069;
    output n15070;
    output n15068;
    output \lux_31__N_511[18] ;
    output led_c_4;
    output led_c_3;
    output led_c_2;
    output \lux_31__N_511[27] ;
    input n486;
    input n2359;
    output \lux_31__N_576[5] ;
    output \lux_31__N_576[3] ;
    output \lux_31__N_576[4] ;
    output \lux_31__N_576[2] ;
    output \lux_31__N_511[10] ;
    input n2356;
    input n21676;
    output \lux_31__N_511[19] ;
    output \lux[19] ;
    output \lux_31__N_511[26] ;
    output \lux[26] ;
    output n15187;
    output n15185;
    output n15186;
    output \lux[18] ;
    output n15183;
    output n15184;
    output n15181;
    output n15182;
    output n111166;
    input n8;
    output n16;
    output n111170;
    input n12;
    output n14;
    output n15179;
    output n15180;
    output n15177;
    output n15178;
    output n15175;
    output n15176;
    output n15173;
    output n15174;
    output n13;
    output n12_adj_111;
    output n111197;
    output n10;
    output n111190;
    output n111191;
    output n15171;
    output n15172;
    output n15169;
    output n15170;
    output \lux_31__N_754[3] ;
    output n8_adj_112;
    output n15168;
    output n111222;
    output led_c_7;
    output n6;
    output n5;
    output n111219;
    output n12_adj_113;
    output \lux_31__N_754[2] ;
    output \lux_31__N_511[9] ;
    output \lux[9] ;
    output led_c_1;
    output led_c_5;
    output \lux_31__N_511[8] ;
    output \lux[8] ;
    output \lux_31__N_511[7] ;
    output \lux[7] ;
    output \lux_31__N_511[6] ;
    output \lux[6] ;
    output \lux_31__N_511[5] ;
    output \lux[5] ;
    output \lux_31__N_511[4] ;
    output \lux[4] ;
    output \lux_31__N_511[3] ;
    output \lux[3] ;
    output \lux_31__N_576[24] ;
    output \lux_31__N_576[25] ;
    output \lux_31__N_576[22] ;
    output \lux_31__N_576[23] ;
    output \lux_31__N_576[20] ;
    output \lux_31__N_576[21] ;
    output \lux_31__N_511[2] ;
    output \lux[2] ;
    output \lux_31__N_511[20] ;
    output \lux[20] ;
    output \lux_31__N_511[21] ;
    output \lux[21] ;
    output \lux_31__N_511[22] ;
    output \lux[22] ;
    output \lux_31__N_511[23] ;
    output \lux[23] ;
    output \lux_31__N_511[24] ;
    output \lux[24] ;
    output \lux_31__N_576[18] ;
    output \lux_31__N_576[19] ;
    output \lux[10] ;
    output \lux_31__N_511[11] ;
    output \lux[11] ;
    output \lux_31__N_511[12] ;
    output \lux[12] ;
    output \lux_31__N_511[13] ;
    output \lux[13] ;
    output \lux_31__N_511[14] ;
    output \lux[14] ;
    output \lux_31__N_511[15] ;
    output \lux[15] ;
    output \lux_31__N_511[16] ;
    output \lux[16] ;
    input bcd_code_31__N_965;
    input n110806;
    output n5695;
    output n110905;
    output n6295;
    output bcd_code_31__N_960;
    output n111044;
    output n110966;
    output n110278;
    input bcd_code_31__N_1130;
    input bcd_code_31__N_1134;
    input n111067;
    output n5740;
    output n6358;
    output n6354;
    input rst_n_c;
    output n110534;
    input bcd_code_31__N_841;
    input bcd_code_31__N_855;
    input bcd_code_31__N_851;
    input bcd_code_31__N_859;
    output n6264;
    output n5653;
    output bcd_code_31__N_797;
    output n110788;
    output n6268;
    output n110521;
    output n110506;
    output n110515;
    output n110514;
    output n110491;
    output n110497;
    output n110490;
    output n16726;
    input bcd_code_31__N_2024;
    output n110559;
    output n110530;
    output n110533;
    output n110545;
    output n110547;
    output n14_adj_114;
    output n14_adj_115;
    output bcd_code_31__N_1042;
    input n110980;
    output n110885;
    output n14_adj_116;
    output n83313;
    output n110532;
    output n7;
    output n110481;
    output n14_adj_117;
    input bcd_code_31__N_1180;
    output n14_adj_118;
    input bcd_code_31__N_1129;
    output n107666;
    input bcd_code_31__N_961;
    output n14_adj_119;
    output n111031;
    output n23;
    output n16565;
    output n7_adj_120;
    output n5948;
    input bcd_code_31__N_1078;
    output n110476;
    output n110546;
    output n14_adj_121;
    input bcd_code_31__N_1079;
    input bcd_code_31__N_1083;
    input n111075;
    output n5845;
    output n5465;
    input bcd_code_31__N_1029;
    output n111092;
    output \lux_data[15] ;
    output n110513;
    output bcd_code_31__N_895;
    output n110282;
    output n14_adj_122;
    output n110480;
    output n110487;
    output n16456;
    input bcd_code_31__N_900;
    output n14_adj_123;
    output n14_adj_124;
    output n7_adj_125;
    input bcd_code_31__N_987;
    output n14_adj_126;
    input bcd_code_31__N_896;
    output n107670;
    output n16625;
    output n111113;
    output n14_adj_127;
    input bcd_code_31__N_951;
    output n14_adj_128;
    output n23_adj_129;
    output n7_adj_130;
    output bcd_code_31__N_850;
    output n111082;
    output n110522;
    output n110485;
    output n110520;
    input bcd_code_31__N_913;
    output n110484;
    output n110281;
    input bcd_code_31__N_886;
    output n110285;
    output n110284;
    output n110289;
    input n110720;
    output n110568;
    output n110582;
    output n110567;
    output n16700;
    input bcd_code_31__N_1519;
    input \lux[27] ;
    output n83413;
    output n110486;
    output n110478;
    input n110930;
    output n23_adj_131;
    output n110482;
    output n14_adj_132;
    output n4;
    output n110475;
    input n110721;
    output bcd_code_31__N_1384;
    output n110701;
    output \lux_data[11] ;
    output n107662;
    output n14_adj_133;
    output n7_adj_134;
    output n110523;
    output n14_adj_135;
    output n110535;
    output n14_adj_136;
    output n14_adj_137;
    output n110524;
    input bcd_code_31__N_1769;
    input bcd_code_31__N_1773;
    input n110965;
    output n5621;
    output n110536;
    output n110507;
    output n110508;
    output n14_adj_138;
    input bcd_code_31__N_1845;
    input bcd_code_31__N_1849;
    input n110952;
    output n5502;
    output \lux_data[31] ;
    input bcd_code_31__N_1973;
    input bcd_code_31__N_1914;
    input bcd_code_31__N_1918;
    input n110936;
    output n5022;
    output n14_adj_139;
    input bcd_code_31__N_1974;
    input bcd_code_31__N_1978;
    input n110921;
    output n5660;
    output n110269;
    output n14_adj_140;
    input \bcd_code_31__N_1380[2] ;
    input bcd_code_31__N_2025;
    input bcd_code_31__N_2029;
    input n110902;
    output n5260;
    output n7_adj_141;
    input bcd_code_31__N_2067;
    input bcd_code_31__N_2071;
    input n110884;
    output n5292;
    output n16584;
    output n83307;
    output n14_adj_142;
    input bcd_code_31__N_2100;
    input bcd_code_31__N_2104;
    input n110868;
    output n5181;
    output n14_adj_143;
    output n14_adj_144;
    output n14_adj_145;
    output n16558;
    output n107664;
    output n7_adj_146;
    output n7_adj_147;
    input bcd_code_31__N_795;
    output n14_adj_148;
    input bcd_code_31__N_1257;
    output n7_adj_149;
    output n14_adj_150;
    output n14_adj_151;
    output n110557;
    output n110556;
    output n110558;
    input bcd_code_31__N_1913;
    output n110495;
    output n110494;
    output n7_adj_152;
    output n16471;
    output n16601;
    output n110592;
    output n83295;
    output n14_adj_153;
    output n16738;
    output n110591;
    output bcd_code_31__N_2138;
    output n16428;
    output n83319;
    output \lux_data[7] ;
    output n110493;
    input [3:0]n922;
    output n110578;
    output n110496;
    output n110581;
    output n110817;
    output n14_adj_154;
    output n110580;
    output n14_adj_155;
    output n107668;
    input bcd_code_31__N_2124;
    input bcd_code_31__N_2128;
    input n110850;
    output n5141;
    output n14_adj_156;
    output n14_adj_157;
    output n14_adj_158;
    output n14_adj_159;
    output n7_adj_160;
    input bcd_code_31__N_1030;
    input bcd_code_31__N_1034;
    input n111081;
    output n5916;
    output n107675;
    output n14_adj_161;
    output n7_adj_162;
    output n14_adj_163;
    output n16300;
    output n110504;
    output n110503;
    output \lux_data[3] ;
    output n110505;
    output n110566;
    input bcd_code_31__N_988;
    input bcd_code_31__N_992;
    input n111089;
    output n6021;
    output \lux_data[23] ;
    output n110489;
    input bcd_code_31__N_1844;
    output \lux_data[27] ;
    output n83415;
    input bcd_code_31__N_952;
    input bcd_code_31__N_956;
    input n111098;
    output n6059;
    input bcd_code_31__N_1768;
    input n6291;
    output n110272;
    input bcd_code_31__N_914;
    input bcd_code_31__N_918;
    input n111102;
    output n5329;
    output n14_adj_164;
    output n107610;
    output n7_adj_165;
    output n14_adj_166;
    output n14_adj_167;
    output n7_adj_168;
    output n14_adj_169;
    output n16550;
    output n14_adj_170;
    input bcd_code_31__N_1140;
    input bcd_code_31__N_1690;
    input bcd_code_31__N_887;
    input bcd_code_31__N_891;
    input n111108;
    output n5433;
    output n16351;
    input bcd_code_31__N_798;
    input bcd_code_31__N_860;
    input bcd_code_31__N_864;
    input n111110;
    output n5548;
    input bcd_code_31__N_2099;
    input bcd_code_31__N_1588;
    input bcd_code_31__N_1394;
    input bcd_code_31__N_1450;
    output \lux_data[19] ;
    input bcd_code_31__N_1246;
    output n110276;
    input bcd_code_31__N_1047;
    input bcd_code_31__N_1366;
    input bcd_code_31__N_1043;
    input bcd_code_31__N_1392;
    output n83303;
    input bcd_code_31__N_1691;
    input bcd_code_31__N_1695;
    input n110987;
    output n5701;
    output n110944;
    output bcd_code_31__N_842;
    output bcd_code_31__N_846;
    input n111115;
    output n5804;
    input bcd_code_31__N_1306;
    output n83327;
    input bcd_code_31__N_1589;
    input bcd_code_31__N_1593;
    input n110994;
    output n5956;
    input bcd_code_31__N_1520;
    input bcd_code_31__N_1524;
    input n111006;
    output n5470;
    input bcd_code_31__N_1451;
    input bcd_code_31__N_1455;
    input n111016;
    output n5988;
    input bcd_code_31__N_2066;
    input bcd_code_31__N_1367;
    input bcd_code_31__N_1371;
    input n111026;
    output n5369;
    output n16541;
    input bcd_code_31__N_1307;
    input bcd_code_31__N_1311;
    input n111037;
    output n5883;
    input n110979;
    output n110275;
    input bcd_code_31__N_1247;
    input bcd_code_31__N_1251;
    input n111050;
    output n5225;
    input bcd_code_31__N_1181;
    input bcd_code_31__N_1185;
    input n111059;
    output n5401;
    
    wire dat_valid /* synthesis is_clock=1, SET_AS_NETWORK=dat_valid */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(31[6:15])
    wire [15:0]prox_dat2;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(28[32:41])
    
    wire prox_dat2_15__N_608;
    wire [15:0]prox_dat0;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(28[12:21])
    wire [15:0]prox_dat1;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(28[22:31])
    
    wire n107253;
    wire [17:0]n15766;
    
    wire n107254, n107252;
    wire [42:0]lux_31__N_625;
    
    wire n107066, n107251, n106940;
    wire [25:0]n56;
    
    wire n106941, n107250, n107249, n107248, n107246;
    wire [23:0]n77;
    wire [23:0]n15739;
    
    wire n107245;
    wire [21:0]n15715;
    
    wire n15738, n107244, n107243, n107242, n107241, n107240, n107239, 
        n107238, n107236, n107235, n107234, n107233, n106836, n16089, 
        n106835;
    wire [23:0]n15325;
    
    wire n15350;
    wire [15:0]n16072;
    
    wire n106834, n106833, n106832, n106831, n106830, n106829, n106818, 
        n1, n106817;
    wire [24:0]n2;
    
    wire n106816, n106815, n106814, n106813, n106812, n106811, n107232, 
        n107231, n107063;
    wire [25:0]n56_adj_2711;
    
    wire n107062, n107230, n107229, n107061, n106939, n107060, n106938, 
        n107227, n1_adj_2388, n107226;
    wire [22:0]n2_adj_2712;
    
    wire n107225, n107224, n107223, n107222, n107221, n107220, n107218, 
        n15714, n107217;
    wire [19:0]n15693;
    
    wire n107059, n106937, n107058, n106936, n107216, n107215, n107214, 
        n107057, n107213, n107056, n106934, n1_adj_2412, n107212, 
        n106933;
    wire [25:0]n2_adj_2713;
    
    wire n106932, n107211, n107054, n1_adj_2419, n106931, n106930, 
        n107053;
    wire [24:0]n2_adj_2714;
    
    wire n106929, n106928, n107052, n106927, n107051, n107050, n107049, 
        n106924;
    wire [25:0]n15402;
    
    wire n107209, n107208, n107048, n106923, n107047, n106922, n107207, 
        n107206, n106921, n106920, n106919, n106918, n107205, n107204, 
        n107203, n107045, n15507, n107202, n107044;
    wire [21:0]n15484;
    
    wire n106917, n107043, n106914;
    wire [25:0]n19;
    
    wire n16049;
    wire [31:0]n764;
    wire [31:0]lux_31__N_721;
    
    wire n82919, n107201, n107042, n106913;
    wire [23:0]n16024;
    
    wire n107041, n106912, n107200, n107199, n107040, n106911, n106910, 
        n107039, n106909, n106908, n107038, n106907, n106906, n107197;
    wire [27:0]n16107;
    wire [27:0]n15662;
    
    wire n107196, n107036;
    wire [15:0]prox_dat2_15__N_609;
    
    wire n107195, n107035, n107034, n106905, n111240, n107033, n106903, 
        n15372, n107194, n107193, n107032, n106902;
    wire [19:0]n15351;
    
    wire n107031, n106901, n107192, n107030, n107029, n107191, n106900, 
        n106899, n107190, n107189, n107027;
    wire [31:0]lux_31__N_543;
    
    wire n106898, n106897, n107026;
    wire [42:0]lux_31__N_657;
    
    wire n106896, n107025, n107024, n106894, n107186;
    wire [26:0]n2_adj_2715;
    
    wire n1_adj_2447;
    wire [27:0]n20;
    
    wire n107185, n107184, n107183, n107182;
    wire [18:0]n15564;
    
    wire n15584, n107023, n107022, n107181, n107021, n107020, n107180, 
        n107019, n106893, n107179, n106892, n107178, n107018, n107177, 
        n107017, n106891, n106890, n107176, n107175, n107016, n107015, 
        n111239, n107173, n15661, n107014, n107172;
    wire [23:0]n15609;
    
    wire n15634;
    wire [24:0]n15635;
    
    wire n106889, n106888, n107171;
    wire [21:0]n15585;
    
    wire n15608, n107010, n106887, n107170, n107009, n107008, n106885;
    wire [26:0]n24;
    
    wire n107169, n107007, n107006, n106884, n106883, n107168, n107005, 
        n106882, n106881, n107167, n107004, n106880, n106879, n107166, 
        n107003, n107002, n106878, n106877, n107165, n107001, n107000, 
        n106876, n106875, n106874, n106998, n15482, n106872, n1_adj_2490, 
        n106997;
    wire [19:0]n15461;
    
    wire n106871;
    wire [22:0]n2_adj_2716;
    
    wire n106870, n106996, n106869, n106868, n107163, n106995, n106867, 
        n107162, n107161, n107160, n107159, n107158, n107157, n107156, 
        n106994, n106866, n106993, n107154, n106992, n106991, n106865, 
        n107153, n106863;
    wire [23:0]n27;
    
    wire n107152, n107151, n107150, n107149, n107148, n107147, n106989, 
        n15268, n106862, n106861, n106988;
    wire [20:0]n15246;
    
    wire n107453, n107145, n106987, n107452, n107144, n107451, n107450, 
        n107449, n106986, n106860, n107448, n107447, n107446, n107445;
    wire [31:0]lux;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(53[12:15])
    
    wire n107444, n107143, n107142, n107141, n106985, n107442, n107441, 
        n107440, n107439, n23_c, n21, n22, n107438, n14_adj_2514, 
        n107437, n107436, n106984, n107435, n107140, n107139, n107434, 
        n107433, n107432, n107431, n107138;
    wire [19:0]n2_adj_2717;
    
    wire n107429;
    wire [24:0]n2_adj_2718;
    wire [19:0]n15786;
    wire [22:0]n15832;
    wire [23:0]n77_adj_2719;
    wire [23:0]n15929;
    
    wire n107428;
    wire [22:0]n15999;
    
    wire n16023, n107427;
    wire [20:0]n15976;
    
    wire n15998, n107426, n107425, n107424, n107135, n1_adj_2520;
    wire [20:0]n24_adj_2720;
    
    wire n107423, n107422, n107421;
    wire [23:0]n2_adj_2721;
    
    wire n107134, n107133, n107132, n107419, n107418, n107131, n107417, 
        n107416, n107415, n107130, n106983, n107129, n106982, n107414, 
        n107128, n106859, n106858, n106980, n107127, n106979, n106857, 
        n106856, n106978, n107413, n107412, n107410, n107409, n107408, 
        n107407, n107406, n107405, n107404, n107403, n107123, n107401, 
        n1_adj_2536, n107122, n107400, n107399, n107121, n107398, 
        n107120, n107397, n107396, n107395, n107394, n107119, n107118, 
        n107117, n107392, n15975, n107391;
    wire [17:0]n15956;
    
    wire n107390, n107389, n107388, n107116, n107387, n107386, n107114, 
        n107385, n107113, n107112, n107382;
    wire [22:0]n2_adj_2722;
    
    wire n1_adj_2553, n107111, n107381, n107380;
    wire [18:0]n15885;
    
    wire n15905, n107110, n107109, n107379, n107108, n107107, n109755, 
        n107378, n107377, n107376, n107375, n107374, n107373, n107370, 
        n107369;
    wire [20:0]n15906;
    
    wire n15928, n107368, n107367, n107366, n107365, n107364, n107363, 
        n107362, n107360, n107359, n107358, n107357, n107356, n106977, 
        n106855, n107355, n106976, n107354, n107353, n107105, n1_adj_2588, 
        n107351, n107104;
    wire [22:0]n2_adj_2723;
    
    wire n15559, n106975, n107103;
    wire [20:0]n15537;
    
    wire n106974, n107102, n106973, n106972, n107350, n107349, n107348, 
        n107347, n106971, n106970, n106969, n106968, n107346, n107101, 
        n107345, n107100, n107344, n107342, n106962, n107341, n107099, 
        n107340, n107098, n107097, n107339, n107096, n106961;
    wire [24:0]n15857;
    
    wire n107338, n106960, n107337, n106959, n106958, n107336, n107335, 
        n107094, n107333, n107093, n107332, n107092, n107331, n107091, 
        n107330, n107090, n107329, n107089, n107328, n107327, n107088, 
        n107326, n107325, n107087, n111232, n107324, n106957, n107323, 
        n107322, n107319, n15856;
    wire [24:0]n25;
    
    wire n107318, n107317, n107316, n107315, n107314, n107313, n107085, 
        n106956, n107084, n106955, n106954, n107083, n106953, n106952, 
        n107082, n106951, n107312, n107311, n107310, n107309, n107305, 
        n107304;
    wire [21:0]n15808;
    
    wire n15831, n107303, n15807, n107081, n106950, n106949, n16171, 
        n16181, n107080, n107302, n107079, n106944, n107078, n106943, 
        n107301, n106942, n107300, n107076, n107299, n107075, n107298, 
        n107297, n107074, n107295, n107294, n107293, n107292, n107291, 
        n107290, n109173, n107289, n107073, n107288, n107072, n107286, 
        n107285, n107284, n107283, n107282, n107281, n107280, n107279, 
        n107277, n1_adj_2635, n107276, n107275, n107274, n107273, 
        n107272, n107271, n107071, n107270, n107070, n107267, n107069, 
        n107266, n107265, n107264, n15785, n107263, n107262, n107068, 
        n107261, n107260, n107259, n107258, n107067, n107257, n107255;
    
    FD1P3AX prox_dat2__i1 (.D(prox_dat0[9]), .SP(prox_dat2_15__N_608), .CK(dat_valid), 
            .Q(prox_dat2[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat2__i1.GSR = "DISABLED";
    FD1S3AX prox_dat1_i0 (.D(prox_dat0[0]), .CK(dat_valid), .Q(prox_dat1[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i0.GSR = "DISABLED";
    FD1S3AX prox_dat0_i0 (.D(prox_dat[0]), .CK(dat_valid), .Q(prox_dat0[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i0.GSR = "DISABLED";
    CCU2D add_9237_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107253), .COUT(n107254), .S0(n15766[14]), 
          .S1(n15766[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_14.INIT0 = 16'h5666;
    defparam add_9237_14.INIT1 = 16'h5666;
    defparam add_9237_14.INJECT1_0 = "NO";
    defparam add_9237_14.INJECT1_1 = "NO";
    CCU2D add_9237_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107252), .COUT(n107253), .S0(n15766[12]), 
          .S1(n15766[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_12.INIT0 = 16'h5666;
    defparam add_9237_12.INIT1 = 16'h5666;
    defparam add_9237_12.INJECT1_0 = "NO";
    defparam add_9237_12.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_2 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107066), .S1(lux_31__N_625[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_2.INIT0 = 16'h7000;
    defparam add_9143_add_3_2.INIT1 = 16'h5666;
    defparam add_9143_add_3_2.INJECT1_0 = "NO";
    defparam add_9143_add_3_2.INJECT1_1 = "NO";
    CCU2D add_9237_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107251), .COUT(n107252), .S0(n15766[10]), 
          .S1(n15766[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_10.INIT0 = 16'h5666;
    defparam add_9237_10.INIT1 = 16'h5666;
    defparam add_9237_10.INJECT1_0 = "NO";
    defparam add_9237_10.INJECT1_1 = "NO";
    CCU2D add_9208_12 (.A0(n56[16]), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[17]), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106940), .COUT(n106941), .S0(\lux_31__N_576[16] ), 
          .S1(\lux_31__N_576[17] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_12.INIT0 = 16'h5666;
    defparam add_9208_12.INIT1 = 16'h5666;
    defparam add_9208_12.INJECT1_0 = "NO";
    defparam add_9208_12.INJECT1_1 = "NO";
    LUT4 mux_19_i25_3_lut (.A(\lux_31__N_511[25] ), .B(\lux_31__N_543[25] ), 
         .C(lux_31__N_575), .Z(\lux[25] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i25_3_lut.init = 16'hcaca;
    LUT4 mux_19_i17_3_lut (.A(\lux_31__N_511[17] ), .B(\lux_31__N_543[17] ), 
         .C(lux_31__N_575), .Z(\lux[17] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i17_3_lut.init = 16'hcaca;
    CCU2D add_9237_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107250), .COUT(n107251), .S0(n15766[8]), 
          .S1(n15766[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_8.INIT0 = 16'h5666;
    defparam add_9237_8.INIT1 = 16'h5666;
    defparam add_9237_8.INJECT1_0 = "NO";
    defparam add_9237_8.INJECT1_1 = "NO";
    CCU2D add_9237_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107249), .COUT(n107250), .S0(n15766[6]), 
          .S1(n15766[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_6.INIT0 = 16'h5666;
    defparam add_9237_6.INIT1 = 16'h5666;
    defparam add_9237_6.INJECT1_0 = "NO";
    defparam add_9237_6.INJECT1_1 = "NO";
    CCU2D add_9237_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107248), .COUT(n107249), .S0(n15766[4]), 
          .S1(n15766[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_4.INIT0 = 16'h5666;
    defparam add_9237_4.INIT1 = 16'h5666;
    defparam add_9237_4.INJECT1_0 = "NO";
    defparam add_9237_4.INJECT1_1 = "NO";
    CCU2D add_9237_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107248), .S1(n15766[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_2.INIT0 = 16'h7000;
    defparam add_9237_2.INIT1 = 16'h5666;
    defparam add_9237_2.INJECT1_0 = "NO";
    defparam add_9237_2.INJECT1_1 = "NO";
    CCU2D add_9234_20 (.A0(n77[23]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107246), 
          .S0(n15739[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_20.INIT0 = 16'h5aaa;
    defparam add_9234_20.INIT1 = 16'h0000;
    defparam add_9234_20.INJECT1_0 = "NO";
    defparam add_9234_20.INJECT1_1 = "NO";
    CCU2D add_9234_18 (.A0(n77[21]), .B0(n15715[21]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[22]), .B1(n15738), .C1(GND_net), .D1(GND_net), .CIN(n107245), 
          .COUT(n107246), .S0(n15739[21]), .S1(n15739[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_18.INIT0 = 16'h5666;
    defparam add_9234_18.INIT1 = 16'h5666;
    defparam add_9234_18.INJECT1_0 = "NO";
    defparam add_9234_18.INJECT1_1 = "NO";
    CCU2D add_9234_16 (.A0(n77[19]), .B0(n15715[19]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[20]), .B1(n15715[20]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107244), .COUT(n107245), .S0(n15739[19]), .S1(n15739[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_16.INIT0 = 16'h5666;
    defparam add_9234_16.INIT1 = 16'h5666;
    defparam add_9234_16.INJECT1_0 = "NO";
    defparam add_9234_16.INJECT1_1 = "NO";
    CCU2D add_9234_14 (.A0(n77[17]), .B0(n15715[17]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[18]), .B1(n15715[18]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107243), .COUT(n107244), .S0(n15739[17]), .S1(n15739[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_14.INIT0 = 16'h5666;
    defparam add_9234_14.INIT1 = 16'h5666;
    defparam add_9234_14.INJECT1_0 = "NO";
    defparam add_9234_14.INJECT1_1 = "NO";
    CCU2D add_9234_12 (.A0(n77[15]), .B0(n15715[15]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[16]), .B1(n15715[16]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107242), .COUT(n107243), .S0(n15739[15]), .S1(n15739[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_12.INIT0 = 16'h5666;
    defparam add_9234_12.INIT1 = 16'h5666;
    defparam add_9234_12.INJECT1_0 = "NO";
    defparam add_9234_12.INJECT1_1 = "NO";
    CCU2D add_9234_10 (.A0(n77[13]), .B0(n15715[13]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[14]), .B1(n15715[14]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107241), .COUT(n107242), .S0(n15739[13]), .S1(n15739[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_10.INIT0 = 16'h5666;
    defparam add_9234_10.INIT1 = 16'h5666;
    defparam add_9234_10.INJECT1_0 = "NO";
    defparam add_9234_10.INJECT1_1 = "NO";
    CCU2D add_9234_8 (.A0(n77[11]), .B0(n15715[11]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[12]), .B1(n15715[12]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107240), .COUT(n107241), .S0(n15739[11]), .S1(n15739[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_8.INIT0 = 16'h5666;
    defparam add_9234_8.INIT1 = 16'h5666;
    defparam add_9234_8.INJECT1_0 = "NO";
    defparam add_9234_8.INJECT1_1 = "NO";
    CCU2D add_9234_6 (.A0(n77[9]), .B0(n15715[9]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[10]), .B1(n15715[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107239), .COUT(n107240), .S0(n15739[9]), .S1(n15739[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_6.INIT0 = 16'h5666;
    defparam add_9234_6.INIT1 = 16'h5666;
    defparam add_9234_6.INJECT1_0 = "NO";
    defparam add_9234_6.INJECT1_1 = "NO";
    CCU2D add_9234_4 (.A0(n77[7]), .B0(n15715[7]), .C0(GND_net), .D0(GND_net), 
          .A1(n77[8]), .B1(n15715[8]), .C1(GND_net), .D1(GND_net), .CIN(n107238), 
          .COUT(n107239), .S0(n15739[7]), .S1(n15739[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_4.INIT0 = 16'h5666;
    defparam add_9234_4.INIT1 = 16'h5666;
    defparam add_9234_4.INJECT1_0 = "NO";
    defparam add_9234_4.INJECT1_1 = "NO";
    CCU2D add_9234_2 (.A0(n77[5]), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_657[1] ), .B1(\lux_31__N_657[0] ), 
          .C1(n77[6]), .D1(GND_net), .COUT(n107238), .S1(n15739[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9234_2.INIT0 = 16'h7000;
    defparam add_9234_2.INIT1 = 16'h9696;
    defparam add_9234_2.INJECT1_0 = "NO";
    defparam add_9234_2.INJECT1_1 = "NO";
    FD1P3AX prox_dat2__i2 (.D(prox_dat0[10]), .SP(prox_dat2_15__N_608), 
            .CK(dat_valid), .Q(prox_dat2[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat2__i2.GSR = "DISABLED";
    FD1P3AX prox_dat2__i3 (.D(prox_dat0[11]), .SP(prox_dat2_15__N_608), 
            .CK(dat_valid), .Q(prox_dat2[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat2__i3.GSR = "DISABLED";
    FD1S3AX prox_dat1_i1 (.D(prox_dat0[1]), .CK(dat_valid), .Q(prox_dat1[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i1.GSR = "DISABLED";
    CCU2D add_9233_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107236), 
          .S0(n15738));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_cout.INIT0 = 16'h0000;
    defparam add_9233_cout.INIT1 = 16'h0000;
    defparam add_9233_cout.INJECT1_0 = "NO";
    defparam add_9233_cout.INJECT1_1 = "NO";
    FD1S3AX prox_dat1_i2 (.D(prox_dat0[2]), .CK(dat_valid), .Q(prox_dat1[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i2.GSR = "DISABLED";
    FD1S3AX prox_dat1_i3 (.D(prox_dat0[3]), .CK(dat_valid), .Q(prox_dat1[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i3.GSR = "DISABLED";
    FD1S3AX prox_dat1_i4 (.D(prox_dat0[4]), .CK(dat_valid), .Q(prox_dat1[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i4.GSR = "DISABLED";
    FD1S3AX prox_dat1_i5 (.D(prox_dat0[5]), .CK(dat_valid), .Q(prox_dat1[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i5.GSR = "DISABLED";
    FD1S3AX prox_dat1_i6 (.D(prox_dat0[6]), .CK(dat_valid), .Q(prox_dat1[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i6.GSR = "DISABLED";
    FD1S3AX prox_dat1_i7 (.D(prox_dat0[7]), .CK(dat_valid), .Q(prox_dat1[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i7.GSR = "DISABLED";
    FD1S3AX prox_dat1_i8 (.D(prox_dat0[8]), .CK(dat_valid), .Q(prox_dat1[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i8.GSR = "DISABLED";
    FD1S3AX prox_dat1_i9 (.D(prox_dat0[9]), .CK(dat_valid), .Q(prox_dat1[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i9.GSR = "DISABLED";
    FD1S3AX prox_dat1_i10 (.D(prox_dat0[10]), .CK(dat_valid), .Q(prox_dat1[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i10.GSR = "DISABLED";
    FD1S3AX prox_dat1_i11 (.D(prox_dat0[11]), .CK(dat_valid), .Q(prox_dat1[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i11.GSR = "DISABLED";
    FD1S3AX prox_dat1_i12 (.D(prox_dat0[12]), .CK(dat_valid), .Q(prox_dat1[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i12.GSR = "DISABLED";
    FD1S3AX prox_dat1_i13 (.D(prox_dat0[13]), .CK(dat_valid), .Q(prox_dat1[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i13.GSR = "DISABLED";
    FD1S3AX prox_dat1_i14 (.D(prox_dat0[14]), .CK(dat_valid), .Q(prox_dat1[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i14.GSR = "DISABLED";
    FD1S3AX prox_dat1_i15 (.D(prox_dat0[15]), .CK(dat_valid), .Q(prox_dat1[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat1_i15.GSR = "DISABLED";
    FD1S3AX prox_dat0_i1 (.D(prox_dat[1]), .CK(dat_valid), .Q(prox_dat0[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i1.GSR = "DISABLED";
    FD1S3AX prox_dat0_i2 (.D(prox_dat[2]), .CK(dat_valid), .Q(prox_dat0[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i2.GSR = "DISABLED";
    FD1S3AX prox_dat0_i3 (.D(prox_dat[3]), .CK(dat_valid), .Q(prox_dat0[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i3.GSR = "DISABLED";
    FD1S3AX prox_dat0_i4 (.D(prox_dat[4]), .CK(dat_valid), .Q(prox_dat0[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i4.GSR = "DISABLED";
    FD1S3AX prox_dat0_i5 (.D(prox_dat[5]), .CK(dat_valid), .Q(prox_dat0[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i5.GSR = "DISABLED";
    FD1S3AX prox_dat0_i6 (.D(prox_dat[6]), .CK(dat_valid), .Q(prox_dat0[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i6.GSR = "DISABLED";
    FD1S3AX prox_dat0_i7 (.D(prox_dat[7]), .CK(dat_valid), .Q(prox_dat0[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i7.GSR = "DISABLED";
    FD1S3AX prox_dat0_i8 (.D(prox_dat[8]), .CK(dat_valid), .Q(prox_dat0[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i8.GSR = "DISABLED";
    FD1S3AX prox_dat0_i9 (.D(prox_dat[9]), .CK(dat_valid), .Q(prox_dat0[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i9.GSR = "DISABLED";
    FD1S3AX prox_dat0_i10 (.D(prox_dat[10]), .CK(dat_valid), .Q(prox_dat0[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i10.GSR = "DISABLED";
    FD1S3AX prox_dat0_i11 (.D(prox_dat[11]), .CK(dat_valid), .Q(prox_dat0[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i11.GSR = "DISABLED";
    FD1S3AX prox_dat0_i12 (.D(prox_dat[12]), .CK(dat_valid), .Q(prox_dat0[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i12.GSR = "DISABLED";
    FD1S3AX prox_dat0_i13 (.D(prox_dat[13]), .CK(dat_valid), .Q(prox_dat0[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i13.GSR = "DISABLED";
    FD1S3AX prox_dat0_i14 (.D(prox_dat[14]), .CK(dat_valid), .Q(prox_dat0[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i14.GSR = "DISABLED";
    FD1S3AX prox_dat0_i15 (.D(prox_dat[15]), .CK(dat_valid), .Q(prox_dat0[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=3, LSE_LLINE=46, LSE_RLINE=54 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(29[8] 36[4])
    defparam prox_dat0_i15.GSR = "DISABLED";
    CCU2D add_9233_16 (.A0(\ch1_dat[15] ), .B0(\ch1_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107235), .COUT(n107236), .S0(n15715[20]), 
          .S1(n15715[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_16.INIT0 = 16'h5666;
    defparam add_9233_16.INIT1 = 16'hfaaa;
    defparam add_9233_16.INJECT1_0 = "NO";
    defparam add_9233_16.INJECT1_1 = "NO";
    CCU2D add_9233_14 (.A0(\ch1_dat[13] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[14] ), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107234), .COUT(n107235), .S0(n15715[18]), 
          .S1(n15715[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_14.INIT0 = 16'h5666;
    defparam add_9233_14.INIT1 = 16'h5666;
    defparam add_9233_14.INJECT1_0 = "NO";
    defparam add_9233_14.INJECT1_1 = "NO";
    CCU2D add_9233_12 (.A0(\ch1_dat[11] ), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[12] ), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107233), .COUT(n107234), .S0(n15715[16]), 
          .S1(n15715[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_12.INIT0 = 16'h5666;
    defparam add_9233_12.INIT1 = 16'h5666;
    defparam add_9233_12.INJECT1_0 = "NO";
    defparam add_9233_12.INJECT1_1 = "NO";
    CCU2D add_9273_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106836), 
          .S0(n16089));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_cout.INIT0 = 16'h0000;
    defparam add_9273_cout.INIT1 = 16'h0000;
    defparam add_9273_cout.INJECT1_0 = "NO";
    defparam add_9273_cout.INJECT1_1 = "NO";
    CCU2D add_9273_16 (.A0(n15325[23]), .B0(\ch1_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15350), .B1(\ch1_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106835), .COUT(n106836), .S0(n16072[14]), 
          .S1(n16072[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_16.INIT0 = 16'h5666;
    defparam add_9273_16.INIT1 = 16'h5666;
    defparam add_9273_16.INJECT1_0 = "NO";
    defparam add_9273_16.INJECT1_1 = "NO";
    CCU2D add_9273_14 (.A0(n15325[21]), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[22]), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106834), .COUT(n106835), .S0(n16072[12]), 
          .S1(n16072[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_14.INIT0 = 16'h5666;
    defparam add_9273_14.INIT1 = 16'h5666;
    defparam add_9273_14.INJECT1_0 = "NO";
    defparam add_9273_14.INJECT1_1 = "NO";
    CCU2D add_9273_12 (.A0(n15325[19]), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[20]), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106833), .COUT(n106834), .S0(n16072[10]), 
          .S1(n16072[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_12.INIT0 = 16'h5666;
    defparam add_9273_12.INIT1 = 16'h5666;
    defparam add_9273_12.INJECT1_0 = "NO";
    defparam add_9273_12.INJECT1_1 = "NO";
    CCU2D add_9273_10 (.A0(n15325[17]), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[18]), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106832), .COUT(n106833), .S0(n16072[8]), 
          .S1(n16072[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_10.INIT0 = 16'h5666;
    defparam add_9273_10.INIT1 = 16'h5666;
    defparam add_9273_10.INJECT1_0 = "NO";
    defparam add_9273_10.INJECT1_1 = "NO";
    CCU2D add_9273_8 (.A0(n15325[15]), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[16]), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106831), .COUT(n106832), .S0(n16072[6]), 
          .S1(n16072[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_8.INIT0 = 16'h5666;
    defparam add_9273_8.INIT1 = 16'h5666;
    defparam add_9273_8.INJECT1_0 = "NO";
    defparam add_9273_8.INJECT1_1 = "NO";
    CCU2D add_9273_6 (.A0(n15325[13]), .B0(\ch1_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[14]), .B1(\ch1_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106830), .COUT(n106831), .S0(n16072[4]), 
          .S1(n16072[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_6.INIT0 = 16'h5666;
    defparam add_9273_6.INIT1 = 16'h5666;
    defparam add_9273_6.INJECT1_0 = "NO";
    defparam add_9273_6.INJECT1_1 = "NO";
    CCU2D add_9273_4 (.A0(n15325[11]), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[12]), .B1(\ch1_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106829), .COUT(n106830), .S0(n16072[2]), 
          .S1(n16072[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_4.INIT0 = 16'h5666;
    defparam add_9273_4.INIT1 = 16'h5666;
    defparam add_9273_4.INJECT1_0 = "NO";
    defparam add_9273_4.INJECT1_1 = "NO";
    CCU2D add_9273_2 (.A0(n15325[9]), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15325[10]), .B1(\lux_31__N_657[1] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106829), .S1(n16072[1]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9273_2.INIT0 = 16'h7000;
    defparam add_9273_2.INIT1 = 16'h5666;
    defparam add_9273_2.INJECT1_0 = "NO";
    defparam add_9273_2.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106818), .S0(n1));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_cout.INIT0 = 16'h0000;
    defparam add_9092_add_1_cout.INIT1 = 16'h0000;
    defparam add_9092_add_1_cout.INJECT1_0 = "NO";
    defparam add_9092_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106817), .COUT(n106818), .S0(n2[23]), 
          .S1(n2[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9092_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9092_add_1_16.INJECT1_0 = "NO";
    defparam add_9092_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106816), .COUT(n106817), .S0(n2[21]), 
          .S1(n2[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9092_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9092_add_1_14.INJECT1_0 = "NO";
    defparam add_9092_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106815), .COUT(n106816), .S0(n2[19]), 
          .S1(n2[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9092_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9092_add_1_12.INJECT1_0 = "NO";
    defparam add_9092_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_10 (.A0(\ch0_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106814), .COUT(n106815), .S0(n2[17]), 
          .S1(n2[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9092_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9092_add_1_10.INJECT1_0 = "NO";
    defparam add_9092_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106813), .COUT(n106814), .S0(n2[15]), 
          .S1(n2[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_8.INIT0 = 16'h5666;
    defparam add_9092_add_1_8.INIT1 = 16'h5aaa;
    defparam add_9092_add_1_8.INJECT1_0 = "NO";
    defparam add_9092_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106812), .COUT(n106813), .S0(n2[13]), 
          .S1(n2[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_6.INIT0 = 16'h5666;
    defparam add_9092_add_1_6.INIT1 = 16'h5666;
    defparam add_9092_add_1_6.INJECT1_0 = "NO";
    defparam add_9092_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[11] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[12] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n106811), .COUT(n106812), 
          .S0(n2[11]), .S1(n2[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_4.INIT0 = 16'h5666;
    defparam add_9092_add_1_4.INIT1 = 16'h5666;
    defparam add_9092_add_1_4.INJECT1_0 = "NO";
    defparam add_9092_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9092_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n106811), .S1(n2[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9092_add_1_2.INIT0 = 16'h7000;
    defparam add_9092_add_1_2.INIT1 = 16'h5666;
    defparam add_9092_add_1_2.INJECT1_0 = "NO";
    defparam add_9092_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9233_10 (.A0(\ch1_dat[9] ), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[10] ), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107232), .COUT(n107233), .S0(n15715[14]), 
          .S1(n15715[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_10.INIT0 = 16'h5666;
    defparam add_9233_10.INIT1 = 16'h5666;
    defparam add_9233_10.INJECT1_0 = "NO";
    defparam add_9233_10.INJECT1_1 = "NO";
    CCU2D add_9233_8 (.A0(\ch1_dat[7] ), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[8] ), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107231), .COUT(n107232), .S0(n15715[12]), 
          .S1(n15715[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_8.INIT0 = 16'h5666;
    defparam add_9233_8.INIT1 = 16'h5666;
    defparam add_9233_8.INJECT1_0 = "NO";
    defparam add_9233_8.INJECT1_1 = "NO";
    CCU2D add_9215_18 (.A0(n56_adj_2711[24]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[25]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107063), .S0(lux_31__N_625[25]), .S1(lux_31__N_625[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_18.INIT0 = 16'h5aaa;
    defparam add_9215_18.INIT1 = 16'h5aaa;
    defparam add_9215_18.INJECT1_0 = "NO";
    defparam add_9215_18.INJECT1_1 = "NO";
    CCU2D add_9215_16 (.A0(n56_adj_2711[22]), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[23]), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107062), .COUT(n107063), .S0(lux_31__N_625[23]), 
          .S1(lux_31__N_625[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_16.INIT0 = 16'h5666;
    defparam add_9215_16.INIT1 = 16'h5666;
    defparam add_9215_16.INJECT1_0 = "NO";
    defparam add_9215_16.INJECT1_1 = "NO";
    CCU2D add_9233_6 (.A0(\ch1_dat[5] ), .B0(\ch1_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[6] ), .B1(\ch1_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107230), .COUT(n107231), .S0(n15715[10]), 
          .S1(n15715[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_6.INIT0 = 16'h5666;
    defparam add_9233_6.INIT1 = 16'h5666;
    defparam add_9233_6.INJECT1_0 = "NO";
    defparam add_9233_6.INJECT1_1 = "NO";
    CCU2D add_9233_4 (.A0(\ch1_dat[3] ), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[4] ), .B1(\ch1_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107229), .COUT(n107230), .S0(n15715[8]), 
          .S1(n15715[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_4.INIT0 = 16'h5666;
    defparam add_9233_4.INIT1 = 16'h5666;
    defparam add_9233_4.INJECT1_0 = "NO";
    defparam add_9233_4.INJECT1_1 = "NO";
    CCU2D add_9233_2 (.A0(\lux_31__N_657[1] ), .B0(\lux_31__N_657[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch1_dat[2] ), .B1(\lux_31__N_657[1] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107229), .S1(n15715[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9233_2.INIT0 = 16'h7000;
    defparam add_9233_2.INIT1 = 16'h5666;
    defparam add_9233_2.INJECT1_0 = "NO";
    defparam add_9233_2.INJECT1_1 = "NO";
    CCU2D add_9215_14 (.A0(n56_adj_2711[20]), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[21]), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107061), .COUT(n107062), .S0(lux_31__N_625[21]), 
          .S1(lux_31__N_625[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_14.INIT0 = 16'h5666;
    defparam add_9215_14.INIT1 = 16'h5666;
    defparam add_9215_14.INJECT1_0 = "NO";
    defparam add_9215_14.INJECT1_1 = "NO";
    CCU2D add_9208_10 (.A0(n56[14]), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[15]), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106939), .COUT(n106940), .S0(\lux_31__N_576[14] ), 
          .S1(\lux_31__N_576[15] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_10.INIT0 = 16'h5666;
    defparam add_9208_10.INIT1 = 16'h5666;
    defparam add_9208_10.INJECT1_0 = "NO";
    defparam add_9208_10.INJECT1_1 = "NO";
    CCU2D add_9215_12 (.A0(n56_adj_2711[18]), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[19]), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107060), .COUT(n107061), .S0(lux_31__N_625[19]), 
          .S1(lux_31__N_625[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_12.INIT0 = 16'h5666;
    defparam add_9215_12.INIT1 = 16'h5666;
    defparam add_9215_12.INJECT1_0 = "NO";
    defparam add_9215_12.INJECT1_1 = "NO";
    CCU2D add_9208_8 (.A0(n56[12]), .B0(\ch0_dat[6] ), .C0(GND_net), .D0(GND_net), 
          .A1(n56[13]), .B1(\ch0_dat[7] ), .C1(GND_net), .D1(GND_net), 
          .CIN(n106938), .COUT(n106939), .S0(\lux_31__N_576[12] ), .S1(\lux_31__N_576[13] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_8.INIT0 = 16'h5666;
    defparam add_9208_8.INIT1 = 16'h5666;
    defparam add_9208_8.INJECT1_0 = "NO";
    defparam add_9208_8.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107227), .S0(n1_adj_2388));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_cout.INIT0 = 16'h0000;
    defparam add_9125_add_1_cout.INIT1 = 16'h0000;
    defparam add_9125_add_1_cout.INJECT1_0 = "NO";
    defparam add_9125_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107226), .COUT(n107227), .S0(n2_adj_2712[21]), 
          .S1(n2_adj_2712[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9125_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9125_add_1_16.INJECT1_0 = "NO";
    defparam add_9125_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_14 (.A0(\ch1_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107225), .COUT(n107226), .S0(n2_adj_2712[19]), 
          .S1(n2_adj_2712[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9125_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9125_add_1_14.INJECT1_0 = "NO";
    defparam add_9125_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_12 (.A0(\ch1_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107224), .COUT(n107225), .S0(n2_adj_2712[17]), 
          .S1(n2_adj_2712[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9125_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9125_add_1_12.INJECT1_0 = "NO";
    defparam add_9125_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_10 (.A0(\ch1_dat[8] ), .B0(\ch1_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107223), .COUT(n107224), .S0(n2_adj_2712[15]), 
          .S1(n2_adj_2712[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_10.INIT0 = 16'h5666;
    defparam add_9125_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9125_add_1_10.INJECT1_0 = "NO";
    defparam add_9125_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_8 (.A0(\ch1_dat[6] ), .B0(\ch1_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(\ch1_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107222), .COUT(n107223), .S0(n2_adj_2712[13]), 
          .S1(n2_adj_2712[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_8.INIT0 = 16'h5666;
    defparam add_9125_add_1_8.INIT1 = 16'h5666;
    defparam add_9125_add_1_8.INJECT1_0 = "NO";
    defparam add_9125_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_6 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[11] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[12] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107221), .COUT(n107222), .S0(n2_adj_2712[11]), 
          .S1(n2_adj_2712[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_6.INIT0 = 16'h5666;
    defparam add_9125_add_1_6.INIT1 = 16'h5666;
    defparam add_9125_add_1_6.INJECT1_0 = "NO";
    defparam add_9125_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_4 (.A0(\ch1_dat[2] ), .B0(\ch1_dat[9] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\ch1_dat[10] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107220), .COUT(n107221), .S0(n2_adj_2712[9]), 
          .S1(n2_adj_2712[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_4.INIT0 = 16'h5666;
    defparam add_9125_add_1_4.INIT1 = 16'h5666;
    defparam add_9125_add_1_4.INJECT1_0 = "NO";
    defparam add_9125_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9125_add_1_2 (.A0(\lux_31__N_657[0] ), .B0(\ch1_dat[7] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_657[1] ), .B1(\ch1_dat[8] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107220), .S1(n2_adj_2712[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9125_add_1_2.INIT0 = 16'h7000;
    defparam add_9125_add_1_2.INIT1 = 16'h5666;
    defparam add_9125_add_1_2.INJECT1_0 = "NO";
    defparam add_9125_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9232_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107218), 
          .S0(n15714));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_cout.INIT0 = 16'h0000;
    defparam add_9232_cout.INIT1 = 16'h0000;
    defparam add_9232_cout.INJECT1_0 = "NO";
    defparam add_9232_cout.INJECT1_1 = "NO";
    CCU2D add_9232_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107217), .COUT(n107218), .S0(n15693[18]), 
          .S1(n15693[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_16.INIT0 = 16'hfaaa;
    defparam add_9232_16.INIT1 = 16'hfaaa;
    defparam add_9232_16.INJECT1_0 = "NO";
    defparam add_9232_16.INJECT1_1 = "NO";
    CCU2D add_9215_10 (.A0(n56_adj_2711[16]), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[17]), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107059), .COUT(n107060), .S0(lux_31__N_625[17]), 
          .S1(lux_31__N_625[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_10.INIT0 = 16'h5666;
    defparam add_9215_10.INIT1 = 16'h5666;
    defparam add_9215_10.INJECT1_0 = "NO";
    defparam add_9215_10.INJECT1_1 = "NO";
    CCU2D add_9208_6 (.A0(n56[10]), .B0(\ch0_dat[4] ), .C0(GND_net), .D0(GND_net), 
          .A1(n56[11]), .B1(\ch0_dat[5] ), .C1(GND_net), .D1(GND_net), 
          .CIN(n106937), .COUT(n106938), .S0(\lux_31__N_576[10] ), .S1(\lux_31__N_576[11] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_6.INIT0 = 16'h5666;
    defparam add_9208_6.INIT1 = 16'h5666;
    defparam add_9208_6.INJECT1_0 = "NO";
    defparam add_9208_6.INJECT1_1 = "NO";
    CCU2D add_9215_8 (.A0(n56_adj_2711[14]), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[15]), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107058), .COUT(n107059), .S0(lux_31__N_625[15]), 
          .S1(lux_31__N_625[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_8.INIT0 = 16'h5666;
    defparam add_9215_8.INIT1 = 16'h5666;
    defparam add_9215_8.INJECT1_0 = "NO";
    defparam add_9215_8.INJECT1_1 = "NO";
    CCU2D add_9208_4 (.A0(n56[8]), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[9]), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106936), .COUT(n106937), .S0(\lux_31__N_576[8] ), 
          .S1(\lux_31__N_576[9] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_4.INIT0 = 16'h5666;
    defparam add_9208_4.INIT1 = 16'h5666;
    defparam add_9208_4.INJECT1_0 = "NO";
    defparam add_9208_4.INJECT1_1 = "NO";
    CCU2D add_9232_14 (.A0(\ch1_dat[15] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107216), .COUT(n107217), .S0(n15693[16]), 
          .S1(n15693[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_14.INIT0 = 16'h5666;
    defparam add_9232_14.INIT1 = 16'hfaaa;
    defparam add_9232_14.INJECT1_0 = "NO";
    defparam add_9232_14.INJECT1_1 = "NO";
    CCU2D add_9232_12 (.A0(\ch1_dat[13] ), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[14] ), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107215), .COUT(n107216), .S0(n15693[14]), 
          .S1(n15693[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_12.INIT0 = 16'h5666;
    defparam add_9232_12.INIT1 = 16'h5666;
    defparam add_9232_12.INJECT1_0 = "NO";
    defparam add_9232_12.INJECT1_1 = "NO";
    CCU2D add_9232_10 (.A0(\ch1_dat[11] ), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[12] ), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107214), .COUT(n107215), .S0(n15693[12]), 
          .S1(n15693[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_10.INIT0 = 16'h5666;
    defparam add_9232_10.INIT1 = 16'h5666;
    defparam add_9232_10.INJECT1_0 = "NO";
    defparam add_9232_10.INJECT1_1 = "NO";
    CCU2D add_9215_6 (.A0(n56_adj_2711[12]), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[13]), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107057), .COUT(n107058), .S0(lux_31__N_625[13]), 
          .S1(lux_31__N_625[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_6.INIT0 = 16'h5666;
    defparam add_9215_6.INIT1 = 16'h5666;
    defparam add_9215_6.INJECT1_0 = "NO";
    defparam add_9215_6.INJECT1_1 = "NO";
    CCU2D add_9208_2 (.A0(n56[6]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[7]), .B1(\lux_31__N_625[2] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106936), .S1(\lux_31__N_576[7] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_2.INIT0 = 16'h7000;
    defparam add_9208_2.INIT1 = 16'h5666;
    defparam add_9208_2.INJECT1_0 = "NO";
    defparam add_9208_2.INJECT1_1 = "NO";
    CCU2D add_9232_8 (.A0(\ch1_dat[9] ), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[10] ), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107213), .COUT(n107214), .S0(n15693[10]), 
          .S1(n15693[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_8.INIT0 = 16'h5666;
    defparam add_9232_8.INIT1 = 16'h5666;
    defparam add_9232_8.INJECT1_0 = "NO";
    defparam add_9232_8.INJECT1_1 = "NO";
    CCU2D add_9215_4 (.A0(n56_adj_2711[10]), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[11]), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107056), .COUT(n107057), .S0(lux_31__N_625[11]), 
          .S1(lux_31__N_625[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_4.INIT0 = 16'h5666;
    defparam add_9215_4.INIT1 = 16'h5666;
    defparam add_9215_4.INJECT1_0 = "NO";
    defparam add_9215_4.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106934), .S0(n1_adj_2412));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_cout.INIT0 = 16'h0000;
    defparam add_9098_add_1_cout.INIT1 = 16'h0000;
    defparam add_9098_add_1_cout.INJECT1_0 = "NO";
    defparam add_9098_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9232_6 (.A0(\ch1_dat[7] ), .B0(\ch1_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[8] ), .B1(\ch1_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107212), .COUT(n107213), .S0(n15693[8]), 
          .S1(n15693[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_6.INIT0 = 16'h5666;
    defparam add_9232_6.INIT1 = 16'h5666;
    defparam add_9232_6.INJECT1_0 = "NO";
    defparam add_9232_6.INJECT1_1 = "NO";
    CCU2D add_9215_2 (.A0(n56_adj_2711[8]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56_adj_2711[9]), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107056), .S1(lux_31__N_625[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9215_2.INIT0 = 16'h7000;
    defparam add_9215_2.INIT1 = 16'h5666;
    defparam add_9215_2.INJECT1_0 = "NO";
    defparam add_9215_2.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106933), .COUT(n106934), .S0(n2_adj_2713[24]), 
          .S1(n2_adj_2713[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9098_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9098_add_1_16.INJECT1_0 = "NO";
    defparam add_9098_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_14 (.A0(\ch1_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106932), .COUT(n106933), .S0(n2_adj_2713[22]), 
          .S1(n2_adj_2713[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9098_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9098_add_1_14.INJECT1_0 = "NO";
    defparam add_9098_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9232_4 (.A0(\ch1_dat[5] ), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[6] ), .B1(\ch1_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107211), .COUT(n107212), .S0(n15693[6]), 
          .S1(n15693[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_4.INIT0 = 16'h5666;
    defparam add_9232_4.INIT1 = 16'h5666;
    defparam add_9232_4.INJECT1_0 = "NO";
    defparam add_9232_4.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107054), .S0(n1_adj_2419));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_cout.INIT0 = 16'h0000;
    defparam add_9143_add_1_cout.INIT1 = 16'h0000;
    defparam add_9143_add_1_cout.INJECT1_0 = "NO";
    defparam add_9143_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_12 (.A0(\ch1_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106931), .COUT(n106932), .S0(n2_adj_2713[20]), 
          .S1(n2_adj_2713[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9098_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9098_add_1_12.INJECT1_0 = "NO";
    defparam add_9098_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_10 (.A0(\ch1_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106930), .COUT(n106931), .S0(n2_adj_2713[18]), 
          .S1(n2_adj_2713[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9098_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9098_add_1_10.INJECT1_0 = "NO";
    defparam add_9098_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107053), .COUT(n107054), .S0(n2_adj_2714[23]), 
          .S1(n2_adj_2714[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9143_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9143_add_1_16.INJECT1_0 = "NO";
    defparam add_9143_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_8 (.A0(\ch1_dat[6] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106929), .COUT(n106930), .S0(n2_adj_2713[16]), 
          .S1(n2_adj_2713[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_8.INIT0 = 16'h5aaa;
    defparam add_9098_add_1_8.INIT1 = 16'h5aaa;
    defparam add_9098_add_1_8.INJECT1_0 = "NO";
    defparam add_9098_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_6 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106928), .COUT(n106929), .S0(n2_adj_2713[14]), 
          .S1(n2_adj_2713[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_6.INIT0 = 16'h5666;
    defparam add_9098_add_1_6.INIT1 = 16'h5666;
    defparam add_9098_add_1_6.INJECT1_0 = "NO";
    defparam add_9098_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9232_2 (.A0(\ch1_dat[3] ), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[4] ), .B1(\lux_31__N_657[1] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n107211), .S1(n15693[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9232_2.INIT0 = 16'h7000;
    defparam add_9232_2.INIT1 = 16'h5666;
    defparam add_9232_2.INJECT1_0 = "NO";
    defparam add_9232_2.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107052), .COUT(n107053), .S0(n2_adj_2714[21]), 
          .S1(n2_adj_2714[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9143_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9143_add_1_14.INJECT1_0 = "NO";
    defparam add_9143_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_4 (.A0(\ch1_dat[2] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106927), .COUT(n106928), .S0(n2_adj_2713[12]), 
          .S1(n2_adj_2713[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_4.INIT0 = 16'h5666;
    defparam add_9098_add_1_4.INIT1 = 16'h5666;
    defparam add_9098_add_1_4.INJECT1_0 = "NO";
    defparam add_9098_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107051), .COUT(n107052), .S0(n2_adj_2714[19]), 
          .S1(n2_adj_2714[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9143_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9143_add_1_12.INJECT1_0 = "NO";
    defparam add_9143_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9098_add_1_2 (.A0(\lux_31__N_657[0] ), .B0(\ch1_dat[10] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_657[1] ), .B1(\ch1_dat[11] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n106927), .S1(n2_adj_2713[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_1_2.INIT0 = 16'h7000;
    defparam add_9098_add_1_2.INIT1 = 16'h5666;
    defparam add_9098_add_1_2.INJECT1_0 = "NO";
    defparam add_9098_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_10 (.A0(\ch0_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107050), .COUT(n107051), .S0(n2_adj_2714[17]), 
          .S1(n2_adj_2714[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9143_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9143_add_1_10.INJECT1_0 = "NO";
    defparam add_9143_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107049), .COUT(n107050), .S0(n2_adj_2714[15]), 
          .S1(n2_adj_2714[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_8.INIT0 = 16'h5666;
    defparam add_9143_add_1_8.INIT1 = 16'h5aaa;
    defparam add_9143_add_1_8.INJECT1_0 = "NO";
    defparam add_9143_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9204_18 (.A0(n15402[24]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n15402[25]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106924), .S0(\lux_31__N_754[24] ), .S1(\lux_31__N_754[25] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_18.INIT0 = 16'h5aaa;
    defparam add_9204_18.INIT1 = 16'h5aaa;
    defparam add_9204_18.INJECT1_0 = "NO";
    defparam add_9204_18.INJECT1_1 = "NO";
    CCU2D add_9348_24 (.A0(n1_adj_2388), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107209), 
          .S0(n77[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_24.INIT0 = 16'h5aaa;
    defparam add_9348_24.INIT1 = 16'h0000;
    defparam add_9348_24.INJECT1_0 = "NO";
    defparam add_9348_24.INJECT1_1 = "NO";
    CCU2D add_9348_22 (.A0(n2_adj_2712[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107208), .COUT(n107209), .S0(n77[21]), 
          .S1(n77[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_22.INIT0 = 16'h5aaa;
    defparam add_9348_22.INIT1 = 16'h5aaa;
    defparam add_9348_22.INJECT1_0 = "NO";
    defparam add_9348_22.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107048), .COUT(n107049), .S0(n2_adj_2714[13]), 
          .S1(n2_adj_2714[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_6.INIT0 = 16'h5666;
    defparam add_9143_add_1_6.INIT1 = 16'h5666;
    defparam add_9143_add_1_6.INJECT1_0 = "NO";
    defparam add_9143_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9204_16 (.A0(n15402[22]), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[23]), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106923), .COUT(n106924), .S0(\lux_31__N_754[22] ), 
          .S1(\lux_31__N_754[23] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_16.INIT0 = 16'h5666;
    defparam add_9204_16.INIT1 = 16'h5666;
    defparam add_9204_16.INJECT1_0 = "NO";
    defparam add_9204_16.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[11] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[12] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107047), .COUT(n107048), 
          .S0(n2_adj_2714[11]), .S1(n2_adj_2714[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_4.INIT0 = 16'h5666;
    defparam add_9143_add_1_4.INIT1 = 16'h5666;
    defparam add_9143_add_1_4.INJECT1_0 = "NO";
    defparam add_9143_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9204_14 (.A0(n15402[20]), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[21]), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106922), .COUT(n106923), .S0(\lux_31__N_754[20] ), 
          .S1(\lux_31__N_754[21] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_14.INIT0 = 16'h5666;
    defparam add_9204_14.INIT1 = 16'h5666;
    defparam add_9204_14.INJECT1_0 = "NO";
    defparam add_9204_14.INJECT1_1 = "NO";
    CCU2D add_9348_20 (.A0(n2_adj_2712[19]), .B0(n15693[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[20]), .B1(n15714), .C1(GND_net), 
          .D1(GND_net), .CIN(n107207), .COUT(n107208), .S0(n77[19]), 
          .S1(n77[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_20.INIT0 = 16'h5666;
    defparam add_9348_20.INIT1 = 16'h5666;
    defparam add_9348_20.INJECT1_0 = "NO";
    defparam add_9348_20.INJECT1_1 = "NO";
    CCU2D add_9348_18 (.A0(n2_adj_2712[17]), .B0(n15693[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[18]), .B1(n15693[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107206), .COUT(n107207), .S0(n77[17]), 
          .S1(n77[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_18.INIT0 = 16'h5666;
    defparam add_9348_18.INIT1 = 16'h5666;
    defparam add_9348_18.INJECT1_0 = "NO";
    defparam add_9348_18.INJECT1_1 = "NO";
    CCU2D add_9143_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107047), .S1(n2_adj_2714[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_1_2.INIT0 = 16'h7000;
    defparam add_9143_add_1_2.INIT1 = 16'h5666;
    defparam add_9143_add_1_2.INJECT1_0 = "NO";
    defparam add_9143_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9204_12 (.A0(n15402[18]), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[19]), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106921), .COUT(n106922), .S0(\lux_31__N_754[18] ), 
          .S1(\lux_31__N_754[19] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_12.INIT0 = 16'h5666;
    defparam add_9204_12.INIT1 = 16'h5666;
    defparam add_9204_12.INJECT1_0 = "NO";
    defparam add_9204_12.INJECT1_1 = "NO";
    CCU2D add_9204_10 (.A0(n15402[16]), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[17]), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106920), .COUT(n106921), .S0(\lux_31__N_754[16] ), 
          .S1(\lux_31__N_754[17] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_10.INIT0 = 16'h5666;
    defparam add_9204_10.INIT1 = 16'h5666;
    defparam add_9204_10.INJECT1_0 = "NO";
    defparam add_9204_10.INJECT1_1 = "NO";
    CCU2D add_9204_8 (.A0(n15402[14]), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[15]), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106919), .COUT(n106920), .S0(\lux_31__N_754[14] ), 
          .S1(\lux_31__N_754[15] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_8.INIT0 = 16'h5666;
    defparam add_9204_8.INIT1 = 16'h5666;
    defparam add_9204_8.INJECT1_0 = "NO";
    defparam add_9204_8.INJECT1_1 = "NO";
    CCU2D add_9204_6 (.A0(n15402[12]), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[13]), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106918), .COUT(n106919), .S0(\lux_31__N_754[12] ), 
          .S1(\lux_31__N_754[13] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_6.INIT0 = 16'h5666;
    defparam add_9204_6.INIT1 = 16'h5666;
    defparam add_9204_6.INJECT1_0 = "NO";
    defparam add_9204_6.INJECT1_1 = "NO";
    CCU2D add_9348_16 (.A0(n2_adj_2712[15]), .B0(n15693[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[16]), .B1(n15693[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107205), .COUT(n107206), .S0(n77[15]), 
          .S1(n77[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_16.INIT0 = 16'h5666;
    defparam add_9348_16.INIT1 = 16'h5666;
    defparam add_9348_16.INJECT1_0 = "NO";
    defparam add_9348_16.INJECT1_1 = "NO";
    CCU2D add_9348_14 (.A0(n2_adj_2712[13]), .B0(n15693[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[14]), .B1(n15693[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107204), .COUT(n107205), .S0(n77[13]), 
          .S1(n77[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_14.INIT0 = 16'h5666;
    defparam add_9348_14.INIT1 = 16'h5666;
    defparam add_9348_14.INJECT1_0 = "NO";
    defparam add_9348_14.INJECT1_1 = "NO";
    CCU2D add_9348_12 (.A0(n2_adj_2712[11]), .B0(n15693[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[12]), .B1(n15693[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107203), .COUT(n107204), .S0(n77[11]), 
          .S1(n77[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_12.INIT0 = 16'h5666;
    defparam add_9348_12.INIT1 = 16'h5666;
    defparam add_9348_12.INJECT1_0 = "NO";
    defparam add_9348_12.INJECT1_1 = "NO";
    CCU2D add_9214_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107045), 
          .S0(n15507));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_cout.INIT0 = 16'h0000;
    defparam add_9214_cout.INIT1 = 16'h0000;
    defparam add_9214_cout.INJECT1_0 = "NO";
    defparam add_9214_cout.INJECT1_1 = "NO";
    CCU2D add_9348_10 (.A0(n2_adj_2712[9]), .B0(n15693[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[10]), .B1(n15693[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107202), .COUT(n107203), .S0(n77[9]), 
          .S1(n77[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_10.INIT0 = 16'h5666;
    defparam add_9348_10.INIT1 = 16'h5666;
    defparam add_9348_10.INJECT1_0 = "NO";
    defparam add_9348_10.INJECT1_1 = "NO";
    CCU2D add_9214_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107044), .COUT(n107045), .S0(n15484[20]), 
          .S1(n15484[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_16.INIT0 = 16'hfaaa;
    defparam add_9214_16.INIT1 = 16'hfaaa;
    defparam add_9214_16.INJECT1_0 = "NO";
    defparam add_9214_16.INJECT1_1 = "NO";
    CCU2D add_9204_4 (.A0(n15402[10]), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[11]), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106917), .COUT(n106918), .S0(\lux_31__N_754[10] ), 
          .S1(\lux_31__N_754[11] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_4.INIT0 = 16'h5666;
    defparam add_9204_4.INIT1 = 16'h5666;
    defparam add_9204_4.INJECT1_0 = "NO";
    defparam add_9204_4.INJECT1_1 = "NO";
    CCU2D add_9204_2 (.A0(n15402[8]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n15402[9]), .B1(\lux_31__N_625[2] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106917), .S1(\lux_31__N_754[9] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9204_2.INIT0 = 16'h7000;
    defparam add_9204_2.INIT1 = 16'h5666;
    defparam add_9204_2.INJECT1_0 = "NO";
    defparam add_9204_2.INJECT1_1 = "NO";
    CCU2D add_9214_14 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107043), .COUT(n107044), .S0(n15484[18]), 
          .S1(n15484[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_14.INIT0 = 16'h5666;
    defparam add_9214_14.INIT1 = 16'hfaaa;
    defparam add_9214_14.INJECT1_0 = "NO";
    defparam add_9214_14.INJECT1_1 = "NO";
    CCU2D add_9205_22 (.A0(n19[24]), .B0(n16049), .C0(GND_net), .D0(GND_net), 
          .A1(n19[25]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106914), 
          .S0(n15402[24]), .S1(n15402[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_22.INIT0 = 16'h5666;
    defparam add_9205_22.INIT1 = 16'h5aaa;
    defparam add_9205_22.INJECT1_0 = "NO";
    defparam add_9205_22.INJECT1_1 = "NO";
    LUT4 mux_27_i17_4_lut (.A(n764[17]), .B(lux_31__N_721[17]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[17] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i17_4_lut.init = 16'hcac0;
    CCU2D add_9348_8 (.A0(n2_adj_2712[7]), .B0(n15693[7]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2712[8]), .B1(n15693[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107201), .COUT(n107202), .S0(n77[7]), 
          .S1(n77[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_8.INIT0 = 16'h5666;
    defparam add_9348_8.INIT1 = 16'h5666;
    defparam add_9348_8.INJECT1_0 = "NO";
    defparam add_9348_8.INJECT1_1 = "NO";
    CCU2D add_9214_12 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107042), .COUT(n107043), .S0(n15484[16]), 
          .S1(n15484[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_12.INIT0 = 16'h5666;
    defparam add_9214_12.INIT1 = 16'h5666;
    defparam add_9214_12.INJECT1_0 = "NO";
    defparam add_9214_12.INJECT1_1 = "NO";
    CCU2D add_9205_20 (.A0(n19[22]), .B0(n16024[22]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[23]), .B1(n16024[23]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106913), .COUT(n106914), .S0(n15402[22]), .S1(n15402[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_20.INIT0 = 16'h5666;
    defparam add_9205_20.INIT1 = 16'h5666;
    defparam add_9205_20.INJECT1_0 = "NO";
    defparam add_9205_20.INJECT1_1 = "NO";
    CCU2D add_9214_10 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107041), .COUT(n107042), .S0(n15484[14]), 
          .S1(n15484[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_10.INIT0 = 16'h5666;
    defparam add_9214_10.INIT1 = 16'h5666;
    defparam add_9214_10.INJECT1_0 = "NO";
    defparam add_9214_10.INJECT1_1 = "NO";
    CCU2D add_9205_18 (.A0(n19[20]), .B0(n16024[20]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[21]), .B1(n16024[21]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106912), .COUT(n106913), .S0(n15402[20]), .S1(n15402[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_18.INIT0 = 16'h5666;
    defparam add_9205_18.INIT1 = 16'h5666;
    defparam add_9205_18.INJECT1_0 = "NO";
    defparam add_9205_18.INJECT1_1 = "NO";
    CCU2D add_9348_6 (.A0(\ch1_dat[5] ), .B0(n15693[5]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[6] ), .B1(n15693[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107200), .COUT(n107201), .S0(n77[5]), 
          .S1(n77[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_6.INIT0 = 16'h5666;
    defparam add_9348_6.INIT1 = 16'h5666;
    defparam add_9348_6.INJECT1_0 = "NO";
    defparam add_9348_6.INJECT1_1 = "NO";
    CCU2D add_9348_4 (.A0(\ch1_dat[3] ), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[4] ), .B1(n15693[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107199), .COUT(n107200), .S0(n77[3]), 
          .S1(n77[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_4.INIT0 = 16'h5666;
    defparam add_9348_4.INIT1 = 16'h5666;
    defparam add_9348_4.INJECT1_0 = "NO";
    defparam add_9348_4.INJECT1_1 = "NO";
    CCU2D add_9214_8 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107040), .COUT(n107041), .S0(n15484[12]), 
          .S1(n15484[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_8.INIT0 = 16'h5666;
    defparam add_9214_8.INIT1 = 16'h5666;
    defparam add_9214_8.INJECT1_0 = "NO";
    defparam add_9214_8.INJECT1_1 = "NO";
    CCU2D add_9205_16 (.A0(n19[18]), .B0(n16024[18]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[19]), .B1(n16024[19]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106911), .COUT(n106912), .S0(n15402[18]), .S1(n15402[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_16.INIT0 = 16'h5666;
    defparam add_9205_16.INIT1 = 16'h5666;
    defparam add_9205_16.INJECT1_0 = "NO";
    defparam add_9205_16.INJECT1_1 = "NO";
    CCU2D add_9205_14 (.A0(n19[16]), .B0(n16024[16]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[17]), .B1(n16024[17]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106910), .COUT(n106911), .S0(n15402[16]), .S1(n15402[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_14.INIT0 = 16'h5666;
    defparam add_9205_14.INIT1 = 16'h5666;
    defparam add_9205_14.INJECT1_0 = "NO";
    defparam add_9205_14.INJECT1_1 = "NO";
    CCU2D add_9214_6 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107039), .COUT(n107040), .S0(n15484[10]), 
          .S1(n15484[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_6.INIT0 = 16'h5666;
    defparam add_9214_6.INIT1 = 16'h5666;
    defparam add_9214_6.INJECT1_0 = "NO";
    defparam add_9214_6.INJECT1_1 = "NO";
    CCU2D add_9205_12 (.A0(n19[14]), .B0(n16024[14]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[15]), .B1(n16024[15]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106909), .COUT(n106910), .S0(n15402[14]), .S1(n15402[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_12.INIT0 = 16'h5666;
    defparam add_9205_12.INIT1 = 16'h5666;
    defparam add_9205_12.INJECT1_0 = "NO";
    defparam add_9205_12.INJECT1_1 = "NO";
    CCU2D add_9205_10 (.A0(n19[12]), .B0(n16024[12]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[13]), .B1(n16024[13]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106908), .COUT(n106909), .S0(n15402[12]), .S1(n15402[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_10.INIT0 = 16'h5666;
    defparam add_9205_10.INIT1 = 16'h5666;
    defparam add_9205_10.INJECT1_0 = "NO";
    defparam add_9205_10.INJECT1_1 = "NO";
    CCU2D add_9348_2 (.A0(\lux_31__N_657[1] ), .B0(\lux_31__N_657[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch1_dat[2] ), .B1(\lux_31__N_657[1] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107199), .S1(n77[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[21:30])
    defparam add_9348_2.INIT0 = 16'h7000;
    defparam add_9348_2.INIT1 = 16'h5666;
    defparam add_9348_2.INJECT1_0 = "NO";
    defparam add_9348_2.INJECT1_1 = "NO";
    CCU2D add_9214_4 (.A0(\ch0_dat[5] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107038), .COUT(n107039), .S0(n15484[8]), 
          .S1(n15484[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_4.INIT0 = 16'h5666;
    defparam add_9214_4.INIT1 = 16'h5666;
    defparam add_9214_4.INJECT1_0 = "NO";
    defparam add_9214_4.INJECT1_1 = "NO";
    CCU2D add_9205_8 (.A0(n19[10]), .B0(n16024[10]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[11]), .B1(n16024[11]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106907), .COUT(n106908), .S0(n15402[10]), .S1(n15402[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_8.INIT0 = 16'h5666;
    defparam add_9205_8.INIT1 = 16'h5666;
    defparam add_9205_8.INJECT1_0 = "NO";
    defparam add_9205_8.INJECT1_1 = "NO";
    CCU2D add_9214_2 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\lux_31__N_625[2] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n107038), .S1(n15484[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9214_2.INIT0 = 16'h7000;
    defparam add_9214_2.INIT1 = 16'h5666;
    defparam add_9214_2.INJECT1_0 = "NO";
    defparam add_9214_2.INJECT1_1 = "NO";
    CCU2D add_9205_6 (.A0(n19[8]), .B0(n16024[8]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[9]), .B1(n16024[9]), .C1(GND_net), .D1(GND_net), .CIN(n106906), 
          .COUT(n106907), .S0(n15402[8]), .S1(n15402[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_6.INIT0 = 16'h5666;
    defparam add_9205_6.INIT1 = 16'h5666;
    defparam add_9205_6.INJECT1_0 = "NO";
    defparam add_9205_6.INJECT1_1 = "NO";
    CCU2D add_9229_20 (.A0(n16107[27]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107197), 
          .S0(n15662[27]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_20.INIT0 = 16'h5aaa;
    defparam add_9229_20.INIT1 = 16'h0000;
    defparam add_9229_20.INJECT1_0 = "NO";
    defparam add_9229_20.INJECT1_1 = "NO";
    CCU2D add_9229_18 (.A0(n16107[25]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n16107[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107196), .COUT(n107197), .S0(n15662[25]), .S1(n15662[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_18.INIT0 = 16'h5aaa;
    defparam add_9229_18.INIT1 = 16'h5aaa;
    defparam add_9229_18.INJECT1_0 = "NO";
    defparam add_9229_18.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_17 (.A0(prox_dat1[15]), .B0(prox_dat0[15]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107036), .S0(prox_dat2_15__N_609[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_17.INIT0 = 16'h5999;
    defparam sub_3_add_2_17.INIT1 = 16'h0000;
    defparam sub_3_add_2_17.INJECT1_0 = "NO";
    defparam sub_3_add_2_17.INJECT1_1 = "NO";
    CCU2D add_9229_16 (.A0(n16107[23]), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[24]), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107195), .COUT(n107196), .S0(n15662[23]), 
          .S1(n15662[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_16.INIT0 = 16'h5666;
    defparam add_9229_16.INIT1 = 16'h5666;
    defparam add_9229_16.INJECT1_0 = "NO";
    defparam add_9229_16.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_15 (.A0(prox_dat1[13]), .B0(prox_dat0[13]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[14]), .B1(prox_dat0[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107035), .COUT(n107036), .S0(prox_dat2_15__N_609[13]), 
          .S1(prox_dat2_15__N_609[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_15.INIT0 = 16'h5999;
    defparam sub_3_add_2_15.INIT1 = 16'h5999;
    defparam sub_3_add_2_15.INJECT1_0 = "NO";
    defparam sub_3_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_13 (.A0(prox_dat1[11]), .B0(prox_dat0[11]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[12]), .B1(prox_dat0[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107034), .COUT(n107035), .S0(prox_dat2_15__N_609[11]), 
          .S1(prox_dat2_15__N_609[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_13.INIT0 = 16'h5999;
    defparam sub_3_add_2_13.INIT1 = 16'h5999;
    defparam sub_3_add_2_13.INJECT1_0 = "NO";
    defparam sub_3_add_2_13.INJECT1_1 = "NO";
    CCU2D add_9205_4 (.A0(n19[6]), .B0(n16024[6]), .C0(GND_net), .D0(GND_net), 
          .A1(n19[7]), .B1(n16024[7]), .C1(GND_net), .D1(GND_net), .CIN(n106905), 
          .COUT(n106906), .S0(\lux_31__N_754[6] ), .S1(\lux_31__N_754[7] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_4.INIT0 = 16'h5666;
    defparam add_9205_4.INIT1 = 16'h5666;
    defparam add_9205_4.INJECT1_0 = "NO";
    defparam add_9205_4.INJECT1_1 = "NO";
    CCU2D add_9205_2 (.A0(n19[4]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n19[5]), .B1(n111240), .C1(GND_net), .D1(GND_net), 
          .COUT(n106905), .S1(\lux_31__N_754[5] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9205_2.INIT0 = 16'h7000;
    defparam add_9205_2.INIT1 = 16'h5666;
    defparam add_9205_2.INJECT1_0 = "NO";
    defparam add_9205_2.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_11 (.A0(prox_dat1[9]), .B0(prox_dat0[9]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[10]), .B1(prox_dat0[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107033), .COUT(n107034));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_11.INIT0 = 16'h5999;
    defparam sub_3_add_2_11.INIT1 = 16'h5999;
    defparam sub_3_add_2_11.INJECT1_0 = "NO";
    defparam sub_3_add_2_11.INJECT1_1 = "NO";
    CCU2D add_9201_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106903), 
          .S0(n15372));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_cout.INIT0 = 16'h0000;
    defparam add_9201_cout.INIT1 = 16'h0000;
    defparam add_9201_cout.INJECT1_0 = "NO";
    defparam add_9201_cout.INJECT1_1 = "NO";
    CCU2D add_9229_14 (.A0(n16107[21]), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[22]), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107194), .COUT(n107195), .S0(n15662[21]), 
          .S1(n15662[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_14.INIT0 = 16'h5666;
    defparam add_9229_14.INIT1 = 16'h5666;
    defparam add_9229_14.INJECT1_0 = "NO";
    defparam add_9229_14.INJECT1_1 = "NO";
    CCU2D add_9229_12 (.A0(n16107[19]), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[20]), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107193), .COUT(n107194), .S0(n15662[19]), 
          .S1(n15662[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_12.INIT0 = 16'h5666;
    defparam add_9229_12.INIT1 = 16'h5666;
    defparam add_9229_12.INJECT1_0 = "NO";
    defparam add_9229_12.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_9 (.A0(prox_dat1[7]), .B0(prox_dat0[7]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[8]), .B1(prox_dat0[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107032), .COUT(n107033));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_9.INIT0 = 16'h5999;
    defparam sub_3_add_2_9.INIT1 = 16'h5999;
    defparam sub_3_add_2_9.INJECT1_0 = "NO";
    defparam sub_3_add_2_9.INJECT1_1 = "NO";
    CCU2D add_9201_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106902), .COUT(n106903), .S0(n15351[18]), 
          .S1(n15351[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_16.INIT0 = 16'hfaaa;
    defparam add_9201_16.INIT1 = 16'hfaaa;
    defparam add_9201_16.INJECT1_0 = "NO";
    defparam add_9201_16.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_7 (.A0(prox_dat1[5]), .B0(prox_dat0[5]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[6]), .B1(prox_dat0[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107031), .COUT(n107032));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_7.INIT0 = 16'h5999;
    defparam sub_3_add_2_7.INIT1 = 16'h5999;
    defparam sub_3_add_2_7.INJECT1_0 = "NO";
    defparam sub_3_add_2_7.INJECT1_1 = "NO";
    CCU2D add_9201_14 (.A0(\ch1_dat[14] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106901), .COUT(n106902), .S0(n15351[16]), 
          .S1(n15351[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_14.INIT0 = 16'h5666;
    defparam add_9201_14.INIT1 = 16'h5666;
    defparam add_9201_14.INJECT1_0 = "NO";
    defparam add_9201_14.INJECT1_1 = "NO";
    CCU2D add_9229_10 (.A0(n16107[17]), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[18]), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107192), .COUT(n107193), .S0(n15662[17]), 
          .S1(n15662[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_10.INIT0 = 16'h5666;
    defparam add_9229_10.INIT1 = 16'h5666;
    defparam add_9229_10.INJECT1_0 = "NO";
    defparam add_9229_10.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_5 (.A0(prox_dat1[3]), .B0(prox_dat0[3]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[4]), .B1(prox_dat0[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107030), .COUT(n107031));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_5.INIT0 = 16'h5999;
    defparam sub_3_add_2_5.INIT1 = 16'h5999;
    defparam sub_3_add_2_5.INJECT1_0 = "NO";
    defparam sub_3_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_3 (.A0(prox_dat1[1]), .B0(prox_dat0[1]), .C0(GND_net), 
          .D0(GND_net), .A1(prox_dat1[2]), .B1(prox_dat0[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107029), .COUT(n107030));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_3.INIT0 = 16'h5999;
    defparam sub_3_add_2_3.INIT1 = 16'h5999;
    defparam sub_3_add_2_3.INJECT1_0 = "NO";
    defparam sub_3_add_2_3.INJECT1_1 = "NO";
    CCU2D add_9229_8 (.A0(n16107[15]), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[16]), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107191), .COUT(n107192), .S0(n15077), 
          .S1(n15662[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_8.INIT0 = 16'h5666;
    defparam add_9229_8.INIT1 = 16'h5666;
    defparam add_9229_8.INJECT1_0 = "NO";
    defparam add_9229_8.INJECT1_1 = "NO";
    CCU2D sub_3_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(prox_dat1[0]), .B1(prox_dat0[0]), .C1(GND_net), .D1(GND_net), 
          .COUT(n107029));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[6:27])
    defparam sub_3_add_2_1.INIT0 = 16'h0000;
    defparam sub_3_add_2_1.INIT1 = 16'h5999;
    defparam sub_3_add_2_1.INJECT1_0 = "NO";
    defparam sub_3_add_2_1.INJECT1_1 = "NO";
    CCU2D add_9201_12 (.A0(\ch1_dat[12] ), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106900), .COUT(n106901), .S0(n15351[14]), 
          .S1(n15351[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_12.INIT0 = 16'h5666;
    defparam add_9201_12.INIT1 = 16'h5666;
    defparam add_9201_12.INJECT1_0 = "NO";
    defparam add_9201_12.INJECT1_1 = "NO";
    CCU2D add_9201_10 (.A0(\ch1_dat[10] ), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106899), .COUT(n106900), .S0(n15351[12]), 
          .S1(n15351[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_10.INIT0 = 16'h5666;
    defparam add_9201_10.INIT1 = 16'h5666;
    defparam add_9201_10.INJECT1_0 = "NO";
    defparam add_9201_10.INJECT1_1 = "NO";
    CCU2D add_9229_6 (.A0(n16107[13]), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[14]), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107190), .COUT(n107191), .S0(n15075), 
          .S1(n15076));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_6.INIT0 = 16'h5666;
    defparam add_9229_6.INIT1 = 16'h5666;
    defparam add_9229_6.INJECT1_0 = "NO";
    defparam add_9229_6.INJECT1_1 = "NO";
    CCU2D add_9229_4 (.A0(n16107[11]), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[12]), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107189), .COUT(n107190), .S0(n15073), 
          .S1(n15074));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_4.INIT0 = 16'h5666;
    defparam add_9229_4.INIT1 = 16'h5666;
    defparam add_9229_4.INJECT1_0 = "NO";
    defparam add_9229_4.INJECT1_1 = "NO";
    CCU2D add_1507_29 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107027), 
          .S0(\lux_31__N_543[27] ), .S1(lux_31__N_543[28]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_29.INIT0 = 16'hffff;
    defparam add_1507_29.INIT1 = 16'hffff;
    defparam add_1507_29.INJECT1_0 = "NO";
    defparam add_1507_29.INJECT1_1 = "NO";
    CCU2D add_9201_8 (.A0(\ch1_dat[8] ), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106898), .COUT(n106899), .S0(n15351[10]), 
          .S1(n15351[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_8.INIT0 = 16'h5666;
    defparam add_9201_8.INIT1 = 16'h5666;
    defparam add_9201_8.INJECT1_0 = "NO";
    defparam add_9201_8.INJECT1_1 = "NO";
    CCU2D add_9201_6 (.A0(\ch1_dat[6] ), .B0(\ch1_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(\ch1_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106897), .COUT(n106898), .S0(n15351[8]), 
          .S1(n15351[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_6.INIT0 = 16'h5666;
    defparam add_9201_6.INIT1 = 16'h5666;
    defparam add_9201_6.INJECT1_0 = "NO";
    defparam add_9201_6.INJECT1_1 = "NO";
    CCU2D add_1507_27 (.A0(lux_31__N_625[25]), .B0(lux_31__N_657[25]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[26]), .B1(lux_31__N_657[26]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107026), .COUT(n107027), 
          .S0(\lux_31__N_543[25] ), .S1(\lux_31__N_543[26] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_27.INIT0 = 16'h5999;
    defparam add_1507_27.INIT1 = 16'h5999;
    defparam add_1507_27.INJECT1_0 = "NO";
    defparam add_1507_27.INJECT1_1 = "NO";
    CCU2D add_9201_4 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106896), .COUT(n106897), .S0(n15351[6]), 
          .S1(n15351[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_4.INIT0 = 16'h5666;
    defparam add_9201_4.INIT1 = 16'h5666;
    defparam add_9201_4.INJECT1_0 = "NO";
    defparam add_9201_4.INJECT1_1 = "NO";
    CCU2D add_9229_2 (.A0(n16107[9]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n16107[10]), .B1(\lux_31__N_625[2] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n107189), .S1(n15072));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9229_2.INIT0 = 16'h7000;
    defparam add_9229_2.INIT1 = 16'h5666;
    defparam add_9229_2.INJECT1_0 = "NO";
    defparam add_9229_2.INJECT1_1 = "NO";
    CCU2D add_1507_25 (.A0(lux_31__N_625[23]), .B0(lux_31__N_657[23]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[24]), .B1(lux_31__N_657[24]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107025), .COUT(n107026), 
          .S0(\lux_31__N_543[23] ), .S1(\lux_31__N_543[24] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_25.INIT0 = 16'h5999;
    defparam add_1507_25.INIT1 = 16'h5999;
    defparam add_1507_25.INJECT1_0 = "NO";
    defparam add_1507_25.INJECT1_1 = "NO";
    CCU2D add_9201_2 (.A0(\ch1_dat[2] ), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\lux_31__N_657[1] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106896), .S1(n15351[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9201_2.INIT0 = 16'h7000;
    defparam add_9201_2.INIT1 = 16'h5666;
    defparam add_9201_2.INJECT1_0 = "NO";
    defparam add_9201_2.INJECT1_1 = "NO";
    CCU2D add_1507_23 (.A0(lux_31__N_625[21]), .B0(lux_31__N_657[21]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[22]), .B1(lux_31__N_657[22]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107024), .COUT(n107025), 
          .S0(\lux_31__N_543[21] ), .S1(\lux_31__N_543[22] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_23.INIT0 = 16'h5999;
    defparam add_1507_23.INIT1 = 16'h5999;
    defparam add_1507_23.INJECT1_0 = "NO";
    defparam add_1507_23.INJECT1_1 = "NO";
    CCU2D add_9200_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106894), 
          .S0(n15350));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_cout.INIT0 = 16'h0000;
    defparam add_9200_cout.INIT1 = 16'h0000;
    defparam add_9200_cout.INJECT1_0 = "NO";
    defparam add_9200_cout.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_26 (.A0(n2_adj_2715[26]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n1_adj_2447), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107186), .S0(n20[26]), .S1(n20[27]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_26.INIT0 = 16'h5aaa;
    defparam add_9130_add_5_26.INIT1 = 16'h5aaa;
    defparam add_9130_add_5_26.INJECT1_0 = "NO";
    defparam add_9130_add_5_26.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_24 (.A0(n2_adj_2715[24]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[25]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107185), .COUT(n107186), .S0(n20[24]), 
          .S1(n20[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_24.INIT0 = 16'h5aaa;
    defparam add_9130_add_5_24.INIT1 = 16'h5aaa;
    defparam add_9130_add_5_24.INJECT1_0 = "NO";
    defparam add_9130_add_5_24.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_22 (.A0(n2_adj_2715[22]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[23]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107184), .COUT(n107185), .S0(n20[22]), 
          .S1(n20[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_22.INIT0 = 16'h5aaa;
    defparam add_9130_add_5_22.INIT1 = 16'h5aaa;
    defparam add_9130_add_5_22.INJECT1_0 = "NO";
    defparam add_9130_add_5_22.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_20 (.A0(n2_adj_2715[20]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[21]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107183), .COUT(n107184), .S0(n20[20]), 
          .S1(n20[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_20.INIT0 = 16'h5aaa;
    defparam add_9130_add_5_20.INIT1 = 16'h5aaa;
    defparam add_9130_add_5_20.INJECT1_0 = "NO";
    defparam add_9130_add_5_20.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_18 (.A0(n2_adj_2715[18]), .B0(n15564[18]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[19]), .B1(n15584), .C1(GND_net), 
          .D1(GND_net), .CIN(n107182), .COUT(n107183), .S0(n20[18]), 
          .S1(n20[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_18.INIT0 = 16'h5666;
    defparam add_9130_add_5_18.INIT1 = 16'h5666;
    defparam add_9130_add_5_18.INJECT1_0 = "NO";
    defparam add_9130_add_5_18.INJECT1_1 = "NO";
    CCU2D add_1507_21 (.A0(lux_31__N_625[19]), .B0(lux_31__N_657[19]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[20]), .B1(lux_31__N_657[20]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107023), .COUT(n107024), 
          .S0(\lux_31__N_543[19] ), .S1(\lux_31__N_543[20] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_21.INIT0 = 16'h5999;
    defparam add_1507_21.INIT1 = 16'h5999;
    defparam add_1507_21.INJECT1_0 = "NO";
    defparam add_1507_21.INJECT1_1 = "NO";
    CCU2D add_1507_19 (.A0(lux_31__N_625[17]), .B0(lux_31__N_657[17]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[18]), .B1(lux_31__N_657[18]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107022), .COUT(n107023), 
          .S0(\lux_31__N_543[17] ), .S1(\lux_31__N_543[18] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_19.INIT0 = 16'h5999;
    defparam add_1507_19.INIT1 = 16'h5999;
    defparam add_1507_19.INJECT1_0 = "NO";
    defparam add_1507_19.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_16 (.A0(n2_adj_2715[16]), .B0(n15564[16]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[17]), .B1(n15564[17]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107181), .COUT(n107182), .S0(n20[16]), 
          .S1(n20[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_16.INIT0 = 16'h5666;
    defparam add_9130_add_5_16.INIT1 = 16'h5666;
    defparam add_9130_add_5_16.INJECT1_0 = "NO";
    defparam add_9130_add_5_16.INJECT1_1 = "NO";
    CCU2D add_1507_17 (.A0(lux_31__N_625[15]), .B0(lux_31__N_657[15]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[16]), .B1(lux_31__N_657[16]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107021), .COUT(n107022), 
          .S0(\lux_31__N_543[15] ), .S1(\lux_31__N_543[16] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_17.INIT0 = 16'h5999;
    defparam add_1507_17.INIT1 = 16'h5999;
    defparam add_1507_17.INJECT1_0 = "NO";
    defparam add_1507_17.INJECT1_1 = "NO";
    CCU2D add_1507_15 (.A0(lux_31__N_625[13]), .B0(lux_31__N_657[13]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[14]), .B1(lux_31__N_657[14]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107020), .COUT(n107021), 
          .S0(\lux_31__N_543[13] ), .S1(\lux_31__N_543[14] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_15.INIT0 = 16'h5999;
    defparam add_1507_15.INIT1 = 16'h5999;
    defparam add_1507_15.INJECT1_0 = "NO";
    defparam add_1507_15.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_14 (.A0(n2_adj_2715[14]), .B0(n15564[14]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[15]), .B1(n15564[15]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107180), .COUT(n107181), .S0(n20[14]), 
          .S1(n20[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_14.INIT0 = 16'h5666;
    defparam add_9130_add_5_14.INIT1 = 16'h5666;
    defparam add_9130_add_5_14.INJECT1_0 = "NO";
    defparam add_9130_add_5_14.INJECT1_1 = "NO";
    CCU2D add_1507_13 (.A0(lux_31__N_625[11]), .B0(lux_31__N_657[11]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[12]), .B1(lux_31__N_657[12]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107019), .COUT(n107020), 
          .S0(\lux_31__N_543[11] ), .S1(\lux_31__N_543[12] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_13.INIT0 = 16'h5999;
    defparam add_1507_13.INIT1 = 16'h5999;
    defparam add_1507_13.INJECT1_0 = "NO";
    defparam add_1507_13.INJECT1_1 = "NO";
    CCU2D add_9200_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106893), .COUT(n106894), .S0(n15325[22]), 
          .S1(n15325[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_16.INIT0 = 16'hfaaa;
    defparam add_9200_16.INIT1 = 16'hfaaa;
    defparam add_9200_16.INJECT1_0 = "NO";
    defparam add_9200_16.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_12 (.A0(n2_adj_2715[12]), .B0(n15564[12]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2715[13]), .B1(n15564[13]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107179), .COUT(n107180), .S0(n20[12]), 
          .S1(n20[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_12.INIT0 = 16'h5666;
    defparam add_9130_add_5_12.INIT1 = 16'h5666;
    defparam add_9130_add_5_12.INJECT1_0 = "NO";
    defparam add_9130_add_5_12.INJECT1_1 = "NO";
    CCU2D add_9200_14 (.A0(\ch1_dat[14] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106892), .COUT(n106893), .S0(n15325[20]), 
          .S1(n15325[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_14.INIT0 = 16'h5666;
    defparam add_9200_14.INIT1 = 16'h5666;
    defparam add_9200_14.INJECT1_0 = "NO";
    defparam add_9200_14.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_10 (.A0(\ch0_dat[10] ), .B0(n15564[10]), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_754[0] ), .B1(\ch0_dat[11] ), .C1(n15564[11]), 
          .D1(GND_net), .CIN(n107178), .COUT(n107179), .S0(n20[10]), 
          .S1(n20[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_10.INIT0 = 16'h5666;
    defparam add_9130_add_5_10.INIT1 = 16'h9696;
    defparam add_9130_add_5_10.INJECT1_0 = "NO";
    defparam add_9130_add_5_10.INJECT1_1 = "NO";
    CCU2D add_1507_11 (.A0(lux_31__N_625[9]), .B0(lux_31__N_657[9]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[10]), .B1(lux_31__N_657[10]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107018), .COUT(n107019), 
          .S0(\lux_31__N_543[9] ), .S1(\lux_31__N_543[10] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_11.INIT0 = 16'h5999;
    defparam add_1507_11.INIT1 = 16'h5999;
    defparam add_1507_11.INJECT1_0 = "NO";
    defparam add_1507_11.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_8 (.A0(\ch0_dat[8] ), .B0(n15564[8]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(n15564[9]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107177), .COUT(n107178), .S0(n20[8]), 
          .S1(n20[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_8.INIT0 = 16'h5666;
    defparam add_9130_add_5_8.INIT1 = 16'h5666;
    defparam add_9130_add_5_8.INJECT1_0 = "NO";
    defparam add_9130_add_5_8.INJECT1_1 = "NO";
    CCU2D add_1507_9 (.A0(lux_31__N_625[7]), .B0(lux_31__N_657[7]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[8]), .B1(lux_31__N_657[8]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107017), .COUT(n107018), 
          .S0(\lux_31__N_543[7] ), .S1(\lux_31__N_543[8] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_9.INIT0 = 16'h5999;
    defparam add_1507_9.INIT1 = 16'h5999;
    defparam add_1507_9.INJECT1_0 = "NO";
    defparam add_1507_9.INJECT1_1 = "NO";
    CCU2D add_9200_12 (.A0(\ch1_dat[12] ), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106891), .COUT(n106892), .S0(n15325[18]), 
          .S1(n15325[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_12.INIT0 = 16'h5666;
    defparam add_9200_12.INIT1 = 16'h5666;
    defparam add_9200_12.INJECT1_0 = "NO";
    defparam add_9200_12.INJECT1_1 = "NO";
    CCU2D add_9200_10 (.A0(\ch1_dat[10] ), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106890), .COUT(n106891), .S0(n15325[16]), 
          .S1(n15325[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_10.INIT0 = 16'h5666;
    defparam add_9200_10.INIT1 = 16'h5666;
    defparam add_9200_10.INJECT1_0 = "NO";
    defparam add_9200_10.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_6 (.A0(\ch0_dat[6] ), .B0(n15564[6]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(n15564[7]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107176), .COUT(n107177), .S0(n20[6]), 
          .S1(n20[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_6.INIT0 = 16'h5666;
    defparam add_9130_add_5_6.INIT1 = 16'h5666;
    defparam add_9130_add_5_6.INJECT1_0 = "NO";
    defparam add_9130_add_5_6.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_4 (.A0(\ch0_dat[4] ), .B0(n15564[4]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(n15564[5]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107175), .COUT(n107176), .S0(n15066), 
          .S1(n20[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_4.INIT0 = 16'h5666;
    defparam add_9130_add_5_4.INIT1 = 16'h5666;
    defparam add_9130_add_5_4.INJECT1_0 = "NO";
    defparam add_9130_add_5_4.INJECT1_1 = "NO";
    CCU2D add_9130_add_5_2 (.A0(\lux_31__N_625[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(\ch0_dat[3] ), .D1(GND_net), .COUT(n107175), .S1(n15065));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_5_2.INIT0 = 16'h7000;
    defparam add_9130_add_5_2.INIT1 = 16'h9696;
    defparam add_9130_add_5_2.INJECT1_0 = "NO";
    defparam add_9130_add_5_2.INJECT1_1 = "NO";
    CCU2D add_1507_7 (.A0(lux_31__N_625[5]), .B0(lux_31__N_657[5]), .C0(GND_net), 
          .D0(GND_net), .A1(lux_31__N_625[6]), .B1(lux_31__N_657[6]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107016), .COUT(n107017), 
          .S0(\lux_31__N_543[5] ), .S1(\lux_31__N_543[6] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_7.INIT0 = 16'h5999;
    defparam add_1507_7.INIT1 = 16'h5999;
    defparam add_1507_7.INJECT1_0 = "NO";
    defparam add_1507_7.INJECT1_1 = "NO";
    CCU2D add_1507_5 (.A0(\lux_31__N_625[3] ), .B0(lux_31__N_657[3]), .C0(GND_net), 
          .D0(GND_net), .A1(n111239), .B1(lux_31__N_657[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107015), .COUT(n107016), .S0(\lux_31__N_543[3] ), 
          .S1(\lux_31__N_543[4] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_5.INIT0 = 16'h5999;
    defparam add_1507_5.INIT1 = 16'h5999;
    defparam add_1507_5.INJECT1_0 = "NO";
    defparam add_1507_5.INJECT1_1 = "NO";
    CCU2D add_9228_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107173), 
          .S0(n15661));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_cout.INIT0 = 16'h0000;
    defparam add_9228_cout.INIT1 = 16'h0000;
    defparam add_9228_cout.INJECT1_0 = "NO";
    defparam add_9228_cout.INJECT1_1 = "NO";
    CCU2D add_1507_3 (.A0(\lux_31__N_754[0] ), .B0(\lux_31__N_657[1] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch1_dat[2] ), .B1(\lux_31__N_657[0] ), 
          .C1(\lux_31__N_625[2] ), .D1(GND_net), .CIN(n107014), .COUT(n107015), 
          .S0(lux_31__N_543[1]), .S1(\lux_31__N_543[2] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_3.INIT0 = 16'h5999;
    defparam add_1507_3.INIT1 = 16'h6969;
    defparam add_1507_3.INJECT1_0 = "NO";
    defparam add_1507_3.INJECT1_1 = "NO";
    CCU2D add_1507_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(\lux_31__N_657[0] ), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n107014));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:32])
    defparam add_1507_1.INIT0 = 16'hF000;
    defparam add_1507_1.INIT1 = 16'h0aaa;
    defparam add_1507_1.INJECT1_0 = "NO";
    defparam add_1507_1.INJECT1_1 = "NO";
    CCU2D add_9228_18 (.A0(n15609[23]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n15634), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107172), 
          .COUT(n107173), .S0(n15635[23]), .S1(n15635[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_18.INIT0 = 16'hfaaa;
    defparam add_9228_18.INIT1 = 16'hfaaa;
    defparam add_9228_18.INJECT1_0 = "NO";
    defparam add_9228_18.INJECT1_1 = "NO";
    CCU2D add_9200_8 (.A0(\ch1_dat[8] ), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106889), .COUT(n106890), .S0(n15325[14]), 
          .S1(n15325[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_8.INIT0 = 16'h5666;
    defparam add_9200_8.INIT1 = 16'h5666;
    defparam add_9200_8.INJECT1_0 = "NO";
    defparam add_9200_8.INJECT1_1 = "NO";
    CCU2D add_9200_6 (.A0(\ch1_dat[6] ), .B0(\ch1_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(\ch1_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106888), .COUT(n106889), .S0(n15325[12]), 
          .S1(n15325[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_6.INIT0 = 16'h5666;
    defparam add_9200_6.INIT1 = 16'h5666;
    defparam add_9200_6.INJECT1_0 = "NO";
    defparam add_9200_6.INJECT1_1 = "NO";
    CCU2D add_9228_16 (.A0(n15585[21]), .B0(n15609[21]), .C0(GND_net), 
          .D0(GND_net), .A1(n15608), .B1(n15609[22]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107171), .COUT(n107172), .S0(n15635[21]), 
          .S1(n15635[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_16.INIT0 = 16'h5666;
    defparam add_9228_16.INIT1 = 16'h5666;
    defparam add_9228_16.INJECT1_0 = "NO";
    defparam add_9228_16.INJECT1_1 = "NO";
    CCU2D add_9306_24 (.A0(n20[27]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107010), 
          .S0(n16107[27]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_24.INIT0 = 16'h5aaa;
    defparam add_9306_24.INIT1 = 16'h0000;
    defparam add_9306_24.INJECT1_0 = "NO";
    defparam add_9306_24.INJECT1_1 = "NO";
    CCU2D add_9200_4 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[2] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106887), .COUT(n106888), .S0(n15325[10]), 
          .S1(n15325[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_4.INIT0 = 16'h5666;
    defparam add_9200_4.INIT1 = 16'h5666;
    defparam add_9200_4.INJECT1_0 = "NO";
    defparam add_9200_4.INJECT1_1 = "NO";
    CCU2D add_9200_2 (.A0(\ch1_dat[2] ), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\lux_31__N_657[1] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106887), .S1(n15325[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9200_2.INIT0 = 16'h7000;
    defparam add_9200_2.INIT1 = 16'h5666;
    defparam add_9200_2.INJECT1_0 = "NO";
    defparam add_9200_2.INJECT1_1 = "NO";
    CCU2D add_9228_14 (.A0(n15585[19]), .B0(n15609[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n15585[20]), .B1(n15609[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107170), .COUT(n107171), .S0(n15635[19]), 
          .S1(n15635[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_14.INIT0 = 16'h5666;
    defparam add_9228_14.INIT1 = 16'h5666;
    defparam add_9228_14.INJECT1_0 = "NO";
    defparam add_9228_14.INJECT1_1 = "NO";
    CCU2D add_9306_22 (.A0(n20[25]), .B0(n15661), .C0(GND_net), .D0(GND_net), 
          .A1(n20[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107009), 
          .COUT(n107010), .S0(n16107[25]), .S1(n16107[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_22.INIT0 = 16'h5666;
    defparam add_9306_22.INIT1 = 16'h5aaa;
    defparam add_9306_22.INJECT1_0 = "NO";
    defparam add_9306_22.INJECT1_1 = "NO";
    CCU2D add_9306_20 (.A0(n20[23]), .B0(n15635[23]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[24]), .B1(n15635[24]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107008), .COUT(n107009), .S0(n16107[23]), .S1(n16107[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_20.INIT0 = 16'h5666;
    defparam add_9306_20.INIT1 = 16'h5666;
    defparam add_9306_20.INJECT1_0 = "NO";
    defparam add_9306_20.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_26 (.A0(n1_adj_2412), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106885), .S0(n24[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_26.INIT0 = 16'h5aaa;
    defparam add_9098_add_4_26.INIT1 = 16'h0000;
    defparam add_9098_add_4_26.INJECT1_0 = "NO";
    defparam add_9098_add_4_26.INJECT1_1 = "NO";
    CCU2D add_9228_12 (.A0(n15585[17]), .B0(n15609[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n15585[18]), .B1(n15609[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107169), .COUT(n107170), .S0(n15635[17]), 
          .S1(n15635[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_12.INIT0 = 16'h5666;
    defparam add_9228_12.INIT1 = 16'h5666;
    defparam add_9228_12.INJECT1_0 = "NO";
    defparam add_9228_12.INJECT1_1 = "NO";
    CCU2D add_9306_18 (.A0(n20[21]), .B0(n15635[21]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[22]), .B1(n15635[22]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107007), .COUT(n107008), .S0(n16107[21]), .S1(n16107[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_18.INIT0 = 16'h5666;
    defparam add_9306_18.INIT1 = 16'h5666;
    defparam add_9306_18.INJECT1_0 = "NO";
    defparam add_9306_18.INJECT1_1 = "NO";
    CCU2D add_9306_16 (.A0(n20[19]), .B0(n15635[19]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[20]), .B1(n15635[20]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107006), .COUT(n107007), .S0(n16107[19]), .S1(n16107[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_16.INIT0 = 16'h5666;
    defparam add_9306_16.INIT1 = 16'h5666;
    defparam add_9306_16.INJECT1_0 = "NO";
    defparam add_9306_16.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_24 (.A0(n2_adj_2713[24]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[25]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106884), .COUT(n106885), .S0(n24[24]), 
          .S1(n24[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_24.INIT0 = 16'h5aaa;
    defparam add_9098_add_4_24.INIT1 = 16'h5aaa;
    defparam add_9098_add_4_24.INJECT1_0 = "NO";
    defparam add_9098_add_4_24.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_22 (.A0(n2_adj_2713[22]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[23]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106883), .COUT(n106884), .S0(n24[22]), 
          .S1(n24[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_22.INIT0 = 16'h5aaa;
    defparam add_9098_add_4_22.INIT1 = 16'h5aaa;
    defparam add_9098_add_4_22.INJECT1_0 = "NO";
    defparam add_9098_add_4_22.INJECT1_1 = "NO";
    CCU2D add_9228_10 (.A0(n15585[15]), .B0(n15609[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n15585[16]), .B1(n15609[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107168), .COUT(n107169), .S0(n15635[15]), 
          .S1(n15635[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_10.INIT0 = 16'h5666;
    defparam add_9228_10.INIT1 = 16'h5666;
    defparam add_9228_10.INJECT1_0 = "NO";
    defparam add_9228_10.INJECT1_1 = "NO";
    CCU2D add_9306_14 (.A0(n20[17]), .B0(n15635[17]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[18]), .B1(n15635[18]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107005), .COUT(n107006), .S0(n16107[17]), .S1(n16107[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_14.INIT0 = 16'h5666;
    defparam add_9306_14.INIT1 = 16'h5666;
    defparam add_9306_14.INJECT1_0 = "NO";
    defparam add_9306_14.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_20 (.A0(n2_adj_2713[20]), .B0(n15372), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[21]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106882), .COUT(n106883), .S0(n24[20]), 
          .S1(n24[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_20.INIT0 = 16'h5666;
    defparam add_9098_add_4_20.INIT1 = 16'h5aaa;
    defparam add_9098_add_4_20.INJECT1_0 = "NO";
    defparam add_9098_add_4_20.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_18 (.A0(n2_adj_2713[18]), .B0(n15351[18]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[19]), .B1(n15351[19]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106881), .COUT(n106882), .S0(n24[18]), 
          .S1(n24[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_18.INIT0 = 16'h5666;
    defparam add_9098_add_4_18.INIT1 = 16'h5666;
    defparam add_9098_add_4_18.INJECT1_0 = "NO";
    defparam add_9098_add_4_18.INJECT1_1 = "NO";
    CCU2D add_9228_8 (.A0(n15585[13]), .B0(n15609[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n15585[14]), .B1(n15609[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107167), .COUT(n107168), .S0(n15635[13]), 
          .S1(n15635[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_8.INIT0 = 16'h5666;
    defparam add_9228_8.INIT1 = 16'h5666;
    defparam add_9228_8.INJECT1_0 = "NO";
    defparam add_9228_8.INJECT1_1 = "NO";
    CCU2D add_9306_12 (.A0(n20[15]), .B0(n15635[15]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[16]), .B1(n15635[16]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107004), .COUT(n107005), .S0(n16107[15]), .S1(n16107[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_12.INIT0 = 16'h5666;
    defparam add_9306_12.INIT1 = 16'h5666;
    defparam add_9306_12.INJECT1_0 = "NO";
    defparam add_9306_12.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_16 (.A0(n2_adj_2713[16]), .B0(n15351[16]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[17]), .B1(n15351[17]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106880), .COUT(n106881), .S0(n24[16]), 
          .S1(n24[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_16.INIT0 = 16'h5666;
    defparam add_9098_add_4_16.INIT1 = 16'h5666;
    defparam add_9098_add_4_16.INJECT1_0 = "NO";
    defparam add_9098_add_4_16.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_14 (.A0(n2_adj_2713[14]), .B0(n15351[14]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[15]), .B1(n15351[15]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106879), .COUT(n106880), .S0(n24[14]), 
          .S1(n24[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_14.INIT0 = 16'h5666;
    defparam add_9098_add_4_14.INIT1 = 16'h5666;
    defparam add_9098_add_4_14.INJECT1_0 = "NO";
    defparam add_9098_add_4_14.INJECT1_1 = "NO";
    CCU2D add_9228_6 (.A0(n15585[11]), .B0(n15609[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n15585[12]), .B1(n15609[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107166), .COUT(n107167), .S0(n15635[11]), 
          .S1(n15635[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_6.INIT0 = 16'h5666;
    defparam add_9228_6.INIT1 = 16'h5666;
    defparam add_9228_6.INJECT1_0 = "NO";
    defparam add_9228_6.INJECT1_1 = "NO";
    CCU2D add_9306_10 (.A0(n20[13]), .B0(n15635[13]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[14]), .B1(n15635[14]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107003), .COUT(n107004), .S0(n16107[13]), .S1(n16107[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_10.INIT0 = 16'h5666;
    defparam add_9306_10.INIT1 = 16'h5666;
    defparam add_9306_10.INJECT1_0 = "NO";
    defparam add_9306_10.INJECT1_1 = "NO";
    CCU2D add_9306_8 (.A0(n20[11]), .B0(n15635[11]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[12]), .B1(n15635[12]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107002), .COUT(n107003), .S0(n16107[11]), .S1(n16107[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_8.INIT0 = 16'h5666;
    defparam add_9306_8.INIT1 = 16'h5666;
    defparam add_9306_8.INJECT1_0 = "NO";
    defparam add_9306_8.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_12 (.A0(n2_adj_2713[12]), .B0(n15351[12]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[13]), .B1(n15351[13]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106878), .COUT(n106879), .S0(n24[12]), 
          .S1(n24[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_12.INIT0 = 16'h5666;
    defparam add_9098_add_4_12.INIT1 = 16'h5666;
    defparam add_9098_add_4_12.INJECT1_0 = "NO";
    defparam add_9098_add_4_12.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_10 (.A0(n2_adj_2713[10]), .B0(n15351[10]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2713[11]), .B1(n15351[11]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106877), .COUT(n106878), .S0(n24[10]), 
          .S1(n24[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_10.INIT0 = 16'h5666;
    defparam add_9098_add_4_10.INIT1 = 16'h5666;
    defparam add_9098_add_4_10.INJECT1_0 = "NO";
    defparam add_9098_add_4_10.INJECT1_1 = "NO";
    CCU2D add_9228_4 (.A0(n15585[9]), .B0(n15609[9]), .C0(GND_net), .D0(GND_net), 
          .A1(n15585[10]), .B1(n15609[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107165), .COUT(n107166), .S0(n15635[9]), .S1(n15635[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_4.INIT0 = 16'h5666;
    defparam add_9228_4.INIT1 = 16'h5666;
    defparam add_9228_4.INJECT1_0 = "NO";
    defparam add_9228_4.INJECT1_1 = "NO";
    CCU2D add_9306_6 (.A0(n20[9]), .B0(n15635[9]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[10]), .B1(n15635[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107001), .COUT(n107002), .S0(n16107[9]), .S1(n16107[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_6.INIT0 = 16'h5666;
    defparam add_9306_6.INIT1 = 16'h5666;
    defparam add_9306_6.INJECT1_0 = "NO";
    defparam add_9306_6.INJECT1_1 = "NO";
    CCU2D add_9306_4 (.A0(n20[7]), .B0(n15635[7]), .C0(GND_net), .D0(GND_net), 
          .A1(n20[8]), .B1(n15635[8]), .C1(GND_net), .D1(GND_net), .CIN(n107000), 
          .COUT(n107001), .S0(n15069), .S1(n15070));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_4.INIT0 = 16'h5666;
    defparam add_9306_4.INIT1 = 16'h5666;
    defparam add_9306_4.INJECT1_0 = "NO";
    defparam add_9306_4.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_8 (.A0(\ch1_dat[8] ), .B0(n15351[8]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(n15351[9]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106876), .COUT(n106877), .S0(n24[8]), 
          .S1(n24[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_8.INIT0 = 16'h5666;
    defparam add_9098_add_4_8.INIT1 = 16'h5666;
    defparam add_9098_add_4_8.INJECT1_0 = "NO";
    defparam add_9098_add_4_8.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_6 (.A0(\ch1_dat[6] ), .B0(n15351[6]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(n15351[7]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106875), .COUT(n106876), .S0(n24[6]), 
          .S1(n24[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_6.INIT0 = 16'h5666;
    defparam add_9098_add_4_6.INIT1 = 16'h5666;
    defparam add_9098_add_4_6.INJECT1_0 = "NO";
    defparam add_9098_add_4_6.INJECT1_1 = "NO";
    CCU2D add_9228_2 (.A0(n15585[7]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(n15585[8]), .D1(GND_net), .COUT(n107165), .S1(n15635[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9228_2.INIT0 = 16'h7000;
    defparam add_9228_2.INIT1 = 16'h9696;
    defparam add_9228_2.INJECT1_0 = "NO";
    defparam add_9228_2.INJECT1_1 = "NO";
    CCU2D add_9306_2 (.A0(n20[5]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n20[6]), .B1(n111240), .C1(GND_net), .D1(GND_net), 
          .COUT(n107000), .S1(n15068));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9306_2.INIT0 = 16'h7000;
    defparam add_9306_2.INIT1 = 16'h5666;
    defparam add_9306_2.INJECT1_0 = "NO";
    defparam add_9306_2.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_4 (.A0(\ch1_dat[4] ), .B0(n15351[4]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(n15351[5]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106874), .COUT(n106875), .S0(lux_31__N_657[4]), 
          .S1(lux_31__N_657[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_4.INIT0 = 16'h5666;
    defparam add_9098_add_4_4.INIT1 = 16'h5666;
    defparam add_9098_add_4_4.INJECT1_0 = "NO";
    defparam add_9098_add_4_4.INJECT1_1 = "NO";
    CCU2D add_9098_add_4_2 (.A0(\ch1_dat[2] ), .B0(\lux_31__N_657[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\lux_31__N_657[1] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n106874), .S1(lux_31__N_657[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9098_add_4_2.INIT0 = 16'h7000;
    defparam add_9098_add_4_2.INIT1 = 16'h5666;
    defparam add_9098_add_4_2.INJECT1_0 = "NO";
    defparam add_9098_add_4_2.INJECT1_1 = "NO";
    CCU2D add_9211_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106998), 
          .S0(n15482));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_cout.INIT0 = 16'h0000;
    defparam add_9211_cout.INIT1 = 16'h0000;
    defparam add_9211_cout.INJECT1_0 = "NO";
    defparam add_9211_cout.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106872), .S0(n1_adj_2490));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_cout.INIT0 = 16'h0000;
    defparam add_9096_add_1_cout.INIT1 = 16'h0000;
    defparam add_9096_add_1_cout.INJECT1_0 = "NO";
    defparam add_9096_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9211_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106997), .COUT(n106998), .S0(n15461[18]), 
          .S1(n15461[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_16.INIT0 = 16'hfaaa;
    defparam add_9211_16.INIT1 = 16'hfaaa;
    defparam add_9211_16.INJECT1_0 = "NO";
    defparam add_9211_16.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106871), .COUT(n106872), .S0(n2_adj_2716[21]), 
          .S1(n2_adj_2716[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9096_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9096_add_1_16.INJECT1_0 = "NO";
    defparam add_9096_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106870), .COUT(n106871), .S0(n2_adj_2716[19]), 
          .S1(n2_adj_2716[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9096_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9096_add_1_14.INJECT1_0 = "NO";
    defparam add_9096_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9211_14 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106996), .COUT(n106997), .S0(n15461[16]), 
          .S1(n15461[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_14.INIT0 = 16'h5666;
    defparam add_9211_14.INIT1 = 16'hfaaa;
    defparam add_9211_14.INJECT1_0 = "NO";
    defparam add_9211_14.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106869), .COUT(n106870), .S0(n2_adj_2716[17]), 
          .S1(n2_adj_2716[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9096_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9096_add_1_12.INJECT1_0 = "NO";
    defparam add_9096_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_10 (.A0(\ch0_dat[8] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106868), .COUT(n106869), .S0(n2_adj_2716[15]), 
          .S1(n2_adj_2716[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_10.INIT0 = 16'h5666;
    defparam add_9096_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9096_add_1_10.INJECT1_0 = "NO";
    defparam add_9096_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9227_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107163), 
          .S0(n15634));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_cout.INIT0 = 16'h0000;
    defparam add_9227_cout.INIT1 = 16'h0000;
    defparam add_9227_cout.INJECT1_0 = "NO";
    defparam add_9227_cout.INJECT1_1 = "NO";
    CCU2D add_9211_12 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106995), .COUT(n106996), .S0(n15461[14]), 
          .S1(n15461[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_12.INIT0 = 16'h5666;
    defparam add_9211_12.INIT1 = 16'h5666;
    defparam add_9211_12.INJECT1_0 = "NO";
    defparam add_9211_12.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106867), .COUT(n106868), .S0(n2_adj_2716[13]), 
          .S1(n2_adj_2716[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_8.INIT0 = 16'h5666;
    defparam add_9096_add_1_8.INIT1 = 16'h5666;
    defparam add_9096_add_1_8.INJECT1_0 = "NO";
    defparam add_9096_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9227_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107162), .COUT(n107163), .S0(n15609[22]), 
          .S1(n15609[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_16.INIT0 = 16'h5666;
    defparam add_9227_16.INIT1 = 16'hfaaa;
    defparam add_9227_16.INJECT1_0 = "NO";
    defparam add_9227_16.INJECT1_1 = "NO";
    CCU2D add_9227_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107161), .COUT(n107162), .S0(n15609[20]), 
          .S1(n15609[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_14.INIT0 = 16'h5666;
    defparam add_9227_14.INIT1 = 16'h5666;
    defparam add_9227_14.INJECT1_0 = "NO";
    defparam add_9227_14.INJECT1_1 = "NO";
    CCU2D add_9227_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107160), .COUT(n107161), .S0(n15609[18]), 
          .S1(n15609[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_12.INIT0 = 16'h5666;
    defparam add_9227_12.INIT1 = 16'h5666;
    defparam add_9227_12.INJECT1_0 = "NO";
    defparam add_9227_12.INJECT1_1 = "NO";
    CCU2D add_9227_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107159), .COUT(n107160), .S0(n15609[16]), 
          .S1(n15609[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_10.INIT0 = 16'h5666;
    defparam add_9227_10.INIT1 = 16'h5666;
    defparam add_9227_10.INJECT1_0 = "NO";
    defparam add_9227_10.INJECT1_1 = "NO";
    CCU2D add_9227_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107158), .COUT(n107159), .S0(n15609[14]), 
          .S1(n15609[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_8.INIT0 = 16'h5666;
    defparam add_9227_8.INIT1 = 16'h5666;
    defparam add_9227_8.INJECT1_0 = "NO";
    defparam add_9227_8.INJECT1_1 = "NO";
    CCU2D add_9227_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107157), .COUT(n107158), .S0(n15609[12]), 
          .S1(n15609[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_6.INIT0 = 16'h5666;
    defparam add_9227_6.INIT1 = 16'h5666;
    defparam add_9227_6.INJECT1_0 = "NO";
    defparam add_9227_6.INJECT1_1 = "NO";
    CCU2D add_9227_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107156), .COUT(n107157), .S0(n15609[10]), 
          .S1(n15609[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_4.INIT0 = 16'h5666;
    defparam add_9227_4.INIT1 = 16'h5666;
    defparam add_9227_4.INJECT1_0 = "NO";
    defparam add_9227_4.INJECT1_1 = "NO";
    CCU2D add_9211_10 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106994), .COUT(n106995), .S0(n15461[12]), 
          .S1(n15461[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_10.INIT0 = 16'h5666;
    defparam add_9211_10.INIT1 = 16'h5666;
    defparam add_9211_10.INJECT1_0 = "NO";
    defparam add_9211_10.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[11] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[12] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106866), .COUT(n106867), .S0(n2_adj_2716[11]), 
          .S1(n2_adj_2716[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_6.INIT0 = 16'h5666;
    defparam add_9096_add_1_6.INIT1 = 16'h5666;
    defparam add_9096_add_1_6.INJECT1_0 = "NO";
    defparam add_9096_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9211_8 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106993), .COUT(n106994), .S0(n15461[10]), 
          .S1(n15461[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_8.INIT0 = 16'h5666;
    defparam add_9211_8.INIT1 = 16'h5666;
    defparam add_9211_8.INJECT1_0 = "NO";
    defparam add_9211_8.INJECT1_1 = "NO";
    CCU2D add_9227_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107156), .S1(n15609[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9227_2.INIT0 = 16'h7000;
    defparam add_9227_2.INIT1 = 16'h5666;
    defparam add_9227_2.INJECT1_0 = "NO";
    defparam add_9227_2.INJECT1_1 = "NO";
    CCU2D add_9226_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107154), 
          .S0(n15608));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_cout.INIT0 = 16'h0000;
    defparam add_9226_cout.INIT1 = 16'h0000;
    defparam add_9226_cout.INJECT1_0 = "NO";
    defparam add_9226_cout.INJECT1_1 = "NO";
    CCU2D add_9211_6 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106992), .COUT(n106993), .S0(n15461[8]), 
          .S1(n15461[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_6.INIT0 = 16'h5666;
    defparam add_9211_6.INIT1 = 16'h5666;
    defparam add_9211_6.INJECT1_0 = "NO";
    defparam add_9211_6.INJECT1_1 = "NO";
    CCU2D add_9211_4 (.A0(\ch0_dat[5] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106991), .COUT(n106992), .S0(n15461[6]), 
          .S1(n15461[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_4.INIT0 = 16'h5666;
    defparam add_9211_4.INIT1 = 16'h5666;
    defparam add_9211_4.INJECT1_0 = "NO";
    defparam add_9211_4.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n106865), .COUT(n106866), 
          .S0(n2_adj_2716[9]), .S1(n2_adj_2716[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_4.INIT0 = 16'h5666;
    defparam add_9096_add_1_4.INIT1 = 16'h5666;
    defparam add_9096_add_1_4.INJECT1_0 = "NO";
    defparam add_9096_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9096_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[7] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[8] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n106865), .S1(n2_adj_2716[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_1_2.INIT0 = 16'h7000;
    defparam add_9096_add_1_2.INIT1 = 16'h5666;
    defparam add_9096_add_1_2.INJECT1_0 = "NO";
    defparam add_9096_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9226_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107153), .COUT(n107154), .S0(n15585[20]), 
          .S1(n15585[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_16.INIT0 = 16'h5666;
    defparam add_9226_16.INIT1 = 16'hfaaa;
    defparam add_9226_16.INJECT1_0 = "NO";
    defparam add_9226_16.INJECT1_1 = "NO";
    CCU2D add_9211_2 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\lux_31__N_625[2] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106991), .S1(n15461[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9211_2.INIT0 = 16'h7000;
    defparam add_9211_2.INIT1 = 16'h5666;
    defparam add_9211_2.INJECT1_0 = "NO";
    defparam add_9211_2.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_20 (.A0(n1_adj_2490), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106863), .S0(n27[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_20.INIT0 = 16'h5aaa;
    defparam add_9096_add_2_20.INIT1 = 16'h0000;
    defparam add_9096_add_2_20.INJECT1_0 = "NO";
    defparam add_9096_add_2_20.INJECT1_1 = "NO";
    CCU2D add_9226_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107152), .COUT(n107153), .S0(n15585[18]), 
          .S1(n15585[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_14.INIT0 = 16'h5666;
    defparam add_9226_14.INIT1 = 16'h5666;
    defparam add_9226_14.INJECT1_0 = "NO";
    defparam add_9226_14.INJECT1_1 = "NO";
    LUT4 mux_27_i18_4_lut (.A(n764[18]), .B(lux_31__N_721[18]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[18] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i18_4_lut.init = 16'hcac0;
    CCU2D add_9226_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107151), .COUT(n107152), .S0(n15585[16]), 
          .S1(n15585[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_12.INIT0 = 16'h5666;
    defparam add_9226_12.INIT1 = 16'h5666;
    defparam add_9226_12.INJECT1_0 = "NO";
    defparam add_9226_12.INJECT1_1 = "NO";
    CCU2D add_9226_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107150), .COUT(n107151), .S0(n15585[14]), 
          .S1(n15585[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_10.INIT0 = 16'h5666;
    defparam add_9226_10.INIT1 = 16'h5666;
    defparam add_9226_10.INJECT1_0 = "NO";
    defparam add_9226_10.INJECT1_1 = "NO";
    CCU2D add_9226_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107149), .COUT(n107150), .S0(n15585[12]), 
          .S1(n15585[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_8.INIT0 = 16'h5666;
    defparam add_9226_8.INIT1 = 16'h5666;
    defparam add_9226_8.INJECT1_0 = "NO";
    defparam add_9226_8.INJECT1_1 = "NO";
    CCU2D add_9226_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107148), .COUT(n107149), .S0(n15585[10]), 
          .S1(n15585[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_6.INIT0 = 16'h5666;
    defparam add_9226_6.INIT1 = 16'h5666;
    defparam add_9226_6.INJECT1_0 = "NO";
    defparam add_9226_6.INJECT1_1 = "NO";
    LUT4 i4_1_lut (.A(prox_dat2[11]), .Z(led_c_4)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(39[2] 49[9])
    defparam i4_1_lut.init = 16'h5555;
    LUT4 i101787_3_lut (.A(prox_dat2[11]), .B(prox_dat2[9]), .C(prox_dat2[10]), 
         .Z(led_c_3)) /* synthesis lut_function=(!(A+(B (C)))) */ ;
    defparam i101787_3_lut.init = 16'h1515;
    LUT4 i101840_2_lut (.A(prox_dat2[10]), .B(prox_dat2[11]), .Z(led_c_2)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i101840_2_lut.init = 16'h1111;
    CCU2D add_9226_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107147), .COUT(n107148), .S0(n15585[8]), 
          .S1(n15585[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_4.INIT0 = 16'h5666;
    defparam add_9226_4.INIT1 = 16'h5666;
    defparam add_9226_4.INJECT1_0 = "NO";
    defparam add_9226_4.INJECT1_1 = "NO";
    CCU2D add_9226_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107147), .S1(n15585[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9226_2.INIT0 = 16'h7000;
    defparam add_9226_2.INIT1 = 16'h5666;
    defparam add_9226_2.INJECT1_0 = "NO";
    defparam add_9226_2.INJECT1_1 = "NO";
    CCU2D add_9169_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106989), 
          .S0(n15268));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_cout.INIT0 = 16'h0000;
    defparam add_9169_cout.INIT1 = 16'h0000;
    defparam add_9169_cout.INJECT1_0 = "NO";
    defparam add_9169_cout.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_18 (.A0(n2_adj_2716[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106862), .COUT(n106863), .S0(n27[21]), 
          .S1(n27[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_18.INIT0 = 16'h5aaa;
    defparam add_9096_add_2_18.INIT1 = 16'h5aaa;
    defparam add_9096_add_2_18.INJECT1_0 = "NO";
    defparam add_9096_add_2_18.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_16 (.A0(n2_adj_2716[19]), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[20]), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106861), .COUT(n106862), .S0(n27[19]), 
          .S1(n27[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_16.INIT0 = 16'h5666;
    defparam add_9096_add_2_16.INIT1 = 16'h5666;
    defparam add_9096_add_2_16.INJECT1_0 = "NO";
    defparam add_9096_add_2_16.INJECT1_1 = "NO";
    CCU2D add_9169_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106988), .COUT(n106989), .S0(n15246[19]), 
          .S1(n15246[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_16.INIT0 = 16'h5aaa;
    defparam add_9169_16.INIT1 = 16'h5aaa;
    defparam add_9169_16.INJECT1_0 = "NO";
    defparam add_9169_16.INJECT1_1 = "NO";
    CCU2D add_9197_22 (.A0(n24[26]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107453), 
          .S0(lux_31__N_657[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_22.INIT0 = 16'h5aaa;
    defparam add_9197_22.INIT1 = 16'h0000;
    defparam add_9197_22.INJECT1_0 = "NO";
    defparam add_9197_22.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107145), .S0(n1_adj_2447));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_cout.INIT0 = 16'h0000;
    defparam add_9130_add_1_cout.INIT1 = 16'h0000;
    defparam add_9130_add_1_cout.INJECT1_0 = "NO";
    defparam add_9130_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9169_14 (.A0(\ch1_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106987), .COUT(n106988), .S0(n15246[17]), 
          .S1(n15246[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_14.INIT0 = 16'h5aaa;
    defparam add_9169_14.INIT1 = 16'h5aaa;
    defparam add_9169_14.INJECT1_0 = "NO";
    defparam add_9169_14.INJECT1_1 = "NO";
    CCU2D add_9197_20 (.A0(n24[24]), .B0(n16072[15]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[25]), .B1(n16089), .C1(GND_net), .D1(GND_net), .CIN(n107452), 
          .COUT(n107453), .S0(lux_31__N_657[24]), .S1(lux_31__N_657[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_20.INIT0 = 16'h5666;
    defparam add_9197_20.INIT1 = 16'h5666;
    defparam add_9197_20.INJECT1_0 = "NO";
    defparam add_9197_20.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107144), .COUT(n107145), .S0(n2_adj_2715[25]), 
          .S1(n2_adj_2715[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9130_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_16.INJECT1_0 = "NO";
    defparam add_9130_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9197_18 (.A0(n24[22]), .B0(n16072[13]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[23]), .B1(n16072[14]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107451), .COUT(n107452), .S0(lux_31__N_657[22]), .S1(lux_31__N_657[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_18.INIT0 = 16'h5666;
    defparam add_9197_18.INIT1 = 16'h5666;
    defparam add_9197_18.INJECT1_0 = "NO";
    defparam add_9197_18.INJECT1_1 = "NO";
    CCU2D add_9197_16 (.A0(n24[20]), .B0(n16072[11]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[21]), .B1(n16072[12]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107450), .COUT(n107451), .S0(lux_31__N_657[20]), .S1(lux_31__N_657[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_16.INIT0 = 16'h5666;
    defparam add_9197_16.INIT1 = 16'h5666;
    defparam add_9197_16.INJECT1_0 = "NO";
    defparam add_9197_16.INJECT1_1 = "NO";
    CCU2D add_9197_14 (.A0(n24[18]), .B0(n16072[9]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[19]), .B1(n16072[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107449), .COUT(n107450), .S0(lux_31__N_657[18]), .S1(lux_31__N_657[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_14.INIT0 = 16'h5666;
    defparam add_9197_14.INIT1 = 16'h5666;
    defparam add_9197_14.INJECT1_0 = "NO";
    defparam add_9197_14.INJECT1_1 = "NO";
    CCU2D add_9169_12 (.A0(\ch1_dat[10] ), .B0(\ch1_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n106986), .COUT(n106987), .S0(n15246[15]), 
          .S1(n15246[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_12.INIT0 = 16'h5666;
    defparam add_9169_12.INIT1 = 16'h5aaa;
    defparam add_9169_12.INJECT1_0 = "NO";
    defparam add_9169_12.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_14 (.A0(n2_adj_2716[17]), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[18]), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106860), .COUT(n106861), .S0(n27[17]), 
          .S1(n27[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_14.INIT0 = 16'h5666;
    defparam add_9096_add_2_14.INIT1 = 16'h5666;
    defparam add_9096_add_2_14.INJECT1_0 = "NO";
    defparam add_9096_add_2_14.INJECT1_1 = "NO";
    CCU2D add_9197_12 (.A0(n24[16]), .B0(n16072[7]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[17]), .B1(n16072[8]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107448), .COUT(n107449), .S0(lux_31__N_657[16]), .S1(lux_31__N_657[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_12.INIT0 = 16'h5666;
    defparam add_9197_12.INIT1 = 16'h5666;
    defparam add_9197_12.INJECT1_0 = "NO";
    defparam add_9197_12.INJECT1_1 = "NO";
    CCU2D add_9197_10 (.A0(n24[14]), .B0(n16072[5]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[15]), .B1(n16072[6]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107447), .COUT(n107448), .S0(lux_31__N_657[14]), .S1(lux_31__N_657[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_10.INIT0 = 16'h5666;
    defparam add_9197_10.INIT1 = 16'h5666;
    defparam add_9197_10.INJECT1_0 = "NO";
    defparam add_9197_10.INJECT1_1 = "NO";
    CCU2D add_9197_8 (.A0(n24[12]), .B0(n16072[3]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[13]), .B1(n16072[4]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107446), .COUT(n107447), .S0(lux_31__N_657[12]), .S1(lux_31__N_657[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_8.INIT0 = 16'h5666;
    defparam add_9197_8.INIT1 = 16'h5666;
    defparam add_9197_8.INJECT1_0 = "NO";
    defparam add_9197_8.INJECT1_1 = "NO";
    CCU2D add_9197_6 (.A0(n24[10]), .B0(n16072[1]), .C0(GND_net), .D0(GND_net), 
          .A1(n24[11]), .B1(n16072[2]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107445), .COUT(n107446), .S0(lux_31__N_657[10]), .S1(lux_31__N_657[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_6.INIT0 = 16'h5666;
    defparam add_9197_6.INIT1 = 16'h5666;
    defparam add_9197_6.INJECT1_0 = "NO";
    defparam add_9197_6.INJECT1_1 = "NO";
    LUT4 mux_19_i29_3_lut (.A(\lux_31__N_511[27] ), .B(lux_31__N_543[28]), 
         .C(lux_31__N_575), .Z(lux[29])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i29_3_lut.init = 16'hcaca;
    CCU2D add_9197_4 (.A0(\ch1_dat[2] ), .B0(\lux_31__N_657[0] ), .C0(n24[8]), 
          .D0(GND_net), .A1(n15325[9]), .B1(\lux_31__N_657[0] ), .C1(n24[9]), 
          .D1(GND_net), .CIN(n107444), .COUT(n107445), .S0(lux_31__N_657[8]), 
          .S1(lux_31__N_657[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_4.INIT0 = 16'h9696;
    defparam add_9197_4.INIT1 = 16'h9696;
    defparam add_9197_4.INJECT1_0 = "NO";
    defparam add_9197_4.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107143), .COUT(n107144), .S0(n2_adj_2715[23]), 
          .S1(n2_adj_2715[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9130_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_14.INJECT1_0 = "NO";
    defparam add_9130_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9197_2 (.A0(n24[6]), .B0(\lux_31__N_657[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(n24[7]), .B1(\lux_31__N_657[1] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n107444), .S1(lux_31__N_657[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[22:32])
    defparam add_9197_2.INIT0 = 16'h7000;
    defparam add_9197_2.INIT1 = 16'h5666;
    defparam add_9197_2.INJECT1_0 = "NO";
    defparam add_9197_2.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107142), .COUT(n107143), .S0(n2_adj_2715[21]), 
          .S1(n2_adj_2715[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9130_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_12.INJECT1_0 = "NO";
    defparam add_9130_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_10 (.A0(\ch0_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107141), .COUT(n107142), .S0(n2_adj_2715[19]), 
          .S1(n2_adj_2715[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9130_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_10.INJECT1_0 = "NO";
    defparam add_9130_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9169_10 (.A0(\ch1_dat[8] ), .B0(\ch1_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(\ch1_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106985), .COUT(n106986), .S0(n15246[13]), 
          .S1(n15246[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_10.INIT0 = 16'h5666;
    defparam add_9169_10.INIT1 = 16'h5666;
    defparam add_9169_10.INJECT1_0 = "NO";
    defparam add_9169_10.INJECT1_1 = "NO";
    CCU2D add_9351_26 (.A0(n1), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107442), 
          .S0(n56[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_26.INIT0 = 16'h5aaa;
    defparam add_9351_26.INIT1 = 16'h0000;
    defparam add_9351_26.INJECT1_0 = "NO";
    defparam add_9351_26.INJECT1_1 = "NO";
    CCU2D add_9351_24 (.A0(n2[23]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n2[24]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107441), 
          .COUT(n107442), .S0(n56[23]), .S1(n56[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_24.INIT0 = 16'h5aaa;
    defparam add_9351_24.INIT1 = 16'h5aaa;
    defparam add_9351_24.INJECT1_0 = "NO";
    defparam add_9351_24.INJECT1_1 = "NO";
    CCU2D add_9351_22 (.A0(n2[21]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n2[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107440), 
          .COUT(n107441), .S0(n56[21]), .S1(n56[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_22.INIT0 = 16'h5aaa;
    defparam add_9351_22.INIT1 = 16'h5aaa;
    defparam add_9351_22.INJECT1_0 = "NO";
    defparam add_9351_22.INJECT1_1 = "NO";
    CCU2D add_9351_20 (.A0(n2[19]), .B0(n15461[19]), .C0(GND_net), .D0(GND_net), 
          .A1(n2[20]), .B1(n15482), .C1(GND_net), .D1(GND_net), .CIN(n107439), 
          .COUT(n107440), .S0(n56[19]), .S1(n56[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_20.INIT0 = 16'h5666;
    defparam add_9351_20.INIT1 = 16'h5666;
    defparam add_9351_20.INJECT1_0 = "NO";
    defparam add_9351_20.INJECT1_1 = "NO";
    LUT4 i1_4_lut (.A(n486), .B(n23_c), .C(n21), .D(n22), .Z(n82919)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_4_lut.init = 16'hfffe;
    CCU2D add_9351_18 (.A0(n2[17]), .B0(n15461[17]), .C0(GND_net), .D0(GND_net), 
          .A1(n2[18]), .B1(n15461[18]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107438), .COUT(n107439), .S0(n56[17]), .S1(n56[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_18.INIT0 = 16'h5666;
    defparam add_9351_18.INIT1 = 16'h5666;
    defparam add_9351_18.INJECT1_0 = "NO";
    defparam add_9351_18.INJECT1_1 = "NO";
    LUT4 i10_4_lut (.A(n15662[24]), .B(n15662[27]), .C(n15662[17]), .D(n14_adj_2514), 
         .Z(n23_c)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i10_4_lut.init = 16'hfffe;
    CCU2D add_9351_16 (.A0(n2[15]), .B0(n15461[15]), .C0(GND_net), .D0(GND_net), 
          .A1(n2[16]), .B1(n15461[16]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107437), .COUT(n107438), .S0(n56[15]), .S1(n56[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_16.INIT0 = 16'h5666;
    defparam add_9351_16.INIT1 = 16'h5666;
    defparam add_9351_16.INJECT1_0 = "NO";
    defparam add_9351_16.INJECT1_1 = "NO";
    CCU2D add_9351_14 (.A0(n2[13]), .B0(n15461[13]), .C0(GND_net), .D0(GND_net), 
          .A1(n2[14]), .B1(n15461[14]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107436), .COUT(n107437), .S0(n56[13]), .S1(n56[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_14.INIT0 = 16'h5666;
    defparam add_9351_14.INIT1 = 16'h5666;
    defparam add_9351_14.INJECT1_0 = "NO";
    defparam add_9351_14.INJECT1_1 = "NO";
    CCU2D add_9169_8 (.A0(\ch1_dat[6] ), .B0(\ch1_dat[11] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(\ch1_dat[12] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106984), .COUT(n106985), .S0(n15246[11]), 
          .S1(n15246[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_8.INIT0 = 16'h5666;
    defparam add_9169_8.INIT1 = 16'h5666;
    defparam add_9169_8.INJECT1_0 = "NO";
    defparam add_9169_8.INJECT1_1 = "NO";
    CCU2D add_9351_12 (.A0(n2[11]), .B0(n15461[11]), .C0(GND_net), .D0(GND_net), 
          .A1(n2[12]), .B1(n15461[12]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107435), .COUT(n107436), .S0(n56[11]), .S1(n56[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_12.INIT0 = 16'h5666;
    defparam add_9351_12.INIT1 = 16'h5666;
    defparam add_9351_12.INJECT1_0 = "NO";
    defparam add_9351_12.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_8 (.A0(\ch0_dat[6] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107140), .COUT(n107141), .S0(n2_adj_2715[17]), 
          .S1(n2_adj_2715[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_8.INIT0 = 16'h5aaa;
    defparam add_9130_add_1_8.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_8.INJECT1_0 = "NO";
    defparam add_9130_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107139), .COUT(n107140), .S0(n2_adj_2715[15]), 
          .S1(n2_adj_2715[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_6.INIT0 = 16'h5666;
    defparam add_9130_add_1_6.INIT1 = 16'h5aaa;
    defparam add_9130_add_1_6.INJECT1_0 = "NO";
    defparam add_9130_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9351_10 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[9] ), .C0(n15461[9]), 
          .D0(GND_net), .A1(n2[10]), .B1(n15461[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107434), .COUT(n107435), .S0(n56[9]), 
          .S1(n56[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_10.INIT0 = 16'h9696;
    defparam add_9351_10.INIT1 = 16'h5666;
    defparam add_9351_10.INJECT1_0 = "NO";
    defparam add_9351_10.INJECT1_1 = "NO";
    LUT4 i8_4_lut (.A(n15662[18]), .B(n15662[21]), .C(n15662[23]), .D(n15662[22]), 
         .Z(n21)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i9_4_lut (.A(n15662[16]), .B(n15662[19]), .C(n15662[26]), .D(n15662[25]), 
         .Z(n22)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut (.A(n2359), .B(n15662[20]), .Z(n14_adj_2514)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut.init = 16'heeee;
    CCU2D add_9351_8 (.A0(\ch0_dat[7] ), .B0(n15461[7]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(n15461[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107433), .COUT(n107434), .S0(n56[7]), 
          .S1(n56[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_8.INIT0 = 16'h5666;
    defparam add_9351_8.INIT1 = 16'h5666;
    defparam add_9351_8.INJECT1_0 = "NO";
    defparam add_9351_8.INJECT1_1 = "NO";
    CCU2D add_9351_6 (.A0(\ch0_dat[5] ), .B0(n15461[5]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(n15461[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107432), .COUT(n107433), .S0(\lux_31__N_576[5] ), 
          .S1(n56[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_6.INIT0 = 16'h5666;
    defparam add_9351_6.INIT1 = 16'h5666;
    defparam add_9351_6.INJECT1_0 = "NO";
    defparam add_9351_6.INJECT1_1 = "NO";
    CCU2D add_9351_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\lux_31__N_754[0] ), .C1(\ch0_dat[4] ), 
          .D1(GND_net), .CIN(n107431), .COUT(n107432), .S0(\lux_31__N_576[3] ), 
          .S1(\lux_31__N_576[4] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_4.INIT0 = 16'h5666;
    defparam add_9351_4.INIT1 = 16'h9696;
    defparam add_9351_4.INJECT1_0 = "NO";
    defparam add_9351_4.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[13] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[14] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107138), .COUT(n107139), 
          .S0(n2_adj_2715[13]), .S1(n2_adj_2715[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_4.INIT0 = 16'h5666;
    defparam add_9130_add_1_4.INIT1 = 16'h5666;
    defparam add_9130_add_1_4.INJECT1_0 = "NO";
    defparam add_9130_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9351_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107431), .S1(\lux_31__N_576[2] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9351_2.INIT0 = 16'h7000;
    defparam add_9351_2.INIT1 = 16'h5666;
    defparam add_9351_2.INJECT1_0 = "NO";
    defparam add_9351_2.INJECT1_1 = "NO";
    LUT4 i99344_2_lut (.A(n77[5]), .B(\lux_31__N_657[0] ), .Z(n15739[5])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99344_2_lut.init = 16'h6666;
    LUT4 i99330_2_lut (.A(\lux_31__N_657[0] ), .B(\ch1_dat[4] ), .Z(n2_adj_2717[4])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99330_2_lut.init = 16'h6666;
    LUT4 i99308_2_lut (.A(\lux_31__N_754[0] ), .B(\ch0_dat[7] ), .Z(n2_adj_2716[7])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99308_2_lut.init = 16'h6666;
    CCU2D add_9252_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107429), 
          .S0(n16049));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_cout.INIT0 = 16'h0000;
    defparam add_9252_cout.INIT1 = 16'h0000;
    defparam add_9252_cout.INJECT1_0 = "NO";
    defparam add_9252_cout.INJECT1_1 = "NO";
    LUT4 i99318_2_lut (.A(\lux_31__N_657[0] ), .B(\ch1_dat[5] ), .Z(n15246[5])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99318_2_lut.init = 16'h6666;
    LUT4 i99360_2_lut (.A(\lux_31__N_754[0] ), .B(\ch0_dat[9] ), .Z(n2_adj_2718[9])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99360_2_lut.init = 16'h6666;
    LUT4 i99350_2_lut (.A(n15786[5]), .B(\lux_31__N_754[0] ), .Z(n15832[5])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99350_2_lut.init = 16'h6666;
    LUT4 i99357_2_lut (.A(n77_adj_2719[4]), .B(\lux_31__N_754[0] ), .Z(n15929[4])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99357_2_lut.init = 16'h6666;
    CCU2D add_9252_18 (.A0(n15999[22]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n16023), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107428), 
          .COUT(n107429), .S0(n16024[22]), .S1(n16024[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_18.INIT0 = 16'hfaaa;
    defparam add_9252_18.INIT1 = 16'hfaaa;
    defparam add_9252_18.INJECT1_0 = "NO";
    defparam add_9252_18.INJECT1_1 = "NO";
    CCU2D add_9130_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[11] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[12] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107138), .S1(n2_adj_2715[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9130_add_1_2.INIT0 = 16'h7000;
    defparam add_9130_add_1_2.INIT1 = 16'h5666;
    defparam add_9130_add_1_2.INJECT1_0 = "NO";
    defparam add_9130_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9252_16 (.A0(n15976[20]), .B0(n15999[20]), .C0(GND_net), 
          .D0(GND_net), .A1(n15998), .B1(n15999[21]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107427), .COUT(n107428), .S0(n16024[20]), 
          .S1(n16024[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_16.INIT0 = 16'h5666;
    defparam add_9252_16.INIT1 = 16'h5666;
    defparam add_9252_16.INJECT1_0 = "NO";
    defparam add_9252_16.INJECT1_1 = "NO";
    CCU2D add_9252_14 (.A0(n15976[18]), .B0(n15999[18]), .C0(GND_net), 
          .D0(GND_net), .A1(n15976[19]), .B1(n15999[19]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107426), .COUT(n107427), .S0(n16024[18]), 
          .S1(n16024[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_14.INIT0 = 16'h5666;
    defparam add_9252_14.INIT1 = 16'h5666;
    defparam add_9252_14.INJECT1_0 = "NO";
    defparam add_9252_14.INJECT1_1 = "NO";
    CCU2D add_9252_12 (.A0(n15976[16]), .B0(n15999[16]), .C0(GND_net), 
          .D0(GND_net), .A1(n15976[17]), .B1(n15999[17]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107425), .COUT(n107426), .S0(n16024[16]), 
          .S1(n16024[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_12.INIT0 = 16'h5666;
    defparam add_9252_12.INIT1 = 16'h5666;
    defparam add_9252_12.INJECT1_0 = "NO";
    defparam add_9252_12.INJECT1_1 = "NO";
    CCU2D add_9252_10 (.A0(n15976[14]), .B0(n15999[14]), .C0(GND_net), 
          .D0(GND_net), .A1(n15976[15]), .B1(n15999[15]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107424), .COUT(n107425), .S0(n16024[14]), 
          .S1(n16024[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_10.INIT0 = 16'h5666;
    defparam add_9252_10.INIT1 = 16'h5666;
    defparam add_9252_10.INJECT1_0 = "NO";
    defparam add_9252_10.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_19 (.A0(GND_net), .B0(n486), .C0(n15739[19]), 
          .D0(n2_adj_2717[19]), .A1(GND_net), .B1(n486), .C1(n15739[20]), 
          .D1(n1_adj_2520), .CIN(n107135), .S0(n24_adj_2720[19]), .S1(n24_adj_2720[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_19.INIT0 = 16'h596a;
    defparam add_9138_add_2_19.INIT1 = 16'h596a;
    defparam add_9138_add_2_19.INJECT1_0 = "NO";
    defparam add_9138_add_2_19.INJECT1_1 = "NO";
    CCU2D add_9252_8 (.A0(n15976[12]), .B0(n15999[12]), .C0(GND_net), 
          .D0(GND_net), .A1(n15976[13]), .B1(n15999[13]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107423), .COUT(n107424), .S0(n16024[12]), 
          .S1(n16024[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_8.INIT0 = 16'h5666;
    defparam add_9252_8.INIT1 = 16'h5666;
    defparam add_9252_8.INJECT1_0 = "NO";
    defparam add_9252_8.INJECT1_1 = "NO";
    CCU2D add_9252_6 (.A0(n15976[10]), .B0(n15999[10]), .C0(GND_net), 
          .D0(GND_net), .A1(n15976[11]), .B1(n15999[11]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107422), .COUT(n107423), .S0(n16024[10]), 
          .S1(n16024[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_6.INIT0 = 16'h5666;
    defparam add_9252_6.INIT1 = 16'h5666;
    defparam add_9252_6.INJECT1_0 = "NO";
    defparam add_9252_6.INJECT1_1 = "NO";
    CCU2D add_9252_4 (.A0(n15976[8]), .B0(n15999[8]), .C0(GND_net), .D0(GND_net), 
          .A1(n15976[9]), .B1(n15999[9]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107421), .COUT(n107422), .S0(n16024[8]), .S1(n16024[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_4.INIT0 = 16'h5666;
    defparam add_9252_4.INIT1 = 16'h5666;
    defparam add_9252_4.INJECT1_0 = "NO";
    defparam add_9252_4.INJECT1_1 = "NO";
    LUT4 mux_27_i10_4_lut (.A(n764[10]), .B(lux_31__N_721[10]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[10] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i10_4_lut.init = 16'hcac0;
    LUT4 i99347_2_lut (.A(\lux_31__N_754[0] ), .B(\ch0_dat[8] ), .Z(n2_adj_2721[8])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99347_2_lut.init = 16'h6666;
    CCU2D add_9252_2 (.A0(n15976[6]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(n15976[7]), .D1(GND_net), .COUT(n107421), .S1(n16024[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9252_2.INIT0 = 16'h7000;
    defparam add_9252_2.INIT1 = 16'h9696;
    defparam add_9252_2.INJECT1_0 = "NO";
    defparam add_9252_2.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_17 (.A0(\ch1_dat[14] ), .B0(n486), .C0(n15739[17]), 
          .D0(n2_adj_2717[17]), .A1(\ch1_dat[15] ), .B1(n486), .C1(n15739[18]), 
          .D1(n2_adj_2717[18]), .CIN(n107134), .COUT(n107135), .S0(n24_adj_2720[17]), 
          .S1(n24_adj_2720[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_17.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_17.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_17.INJECT1_0 = "NO";
    defparam add_9138_add_2_17.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_15 (.A0(\ch1_dat[12] ), .B0(n486), .C0(n15739[15]), 
          .D0(n2_adj_2717[15]), .A1(\ch1_dat[13] ), .B1(n486), .C1(n15739[16]), 
          .D1(n2_adj_2717[16]), .CIN(n107133), .COUT(n107134), .S0(n24_adj_2720[15]), 
          .S1(n24_adj_2720[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_15.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_15.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_15.INJECT1_0 = "NO";
    defparam add_9138_add_2_15.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_13 (.A0(\ch1_dat[10] ), .B0(n486), .C0(n15739[13]), 
          .D0(n2_adj_2717[13]), .A1(\ch1_dat[11] ), .B1(n486), .C1(n15739[14]), 
          .D1(n2_adj_2717[14]), .CIN(n107132), .COUT(n107133), .S0(n24_adj_2720[13]), 
          .S1(n24_adj_2720[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_13.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_13.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_13.INJECT1_0 = "NO";
    defparam add_9138_add_2_13.INJECT1_1 = "NO";
    CCU2D add_9251_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107419), 
          .S0(n16023));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_cout.INIT0 = 16'h0000;
    defparam add_9251_cout.INIT1 = 16'h0000;
    defparam add_9251_cout.INJECT1_0 = "NO";
    defparam add_9251_cout.INJECT1_1 = "NO";
    CCU2D add_9251_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107418), .COUT(n107419), .S0(n15999[21]), 
          .S1(n15999[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_16.INIT0 = 16'h5666;
    defparam add_9251_16.INIT1 = 16'hfaaa;
    defparam add_9251_16.INJECT1_0 = "NO";
    defparam add_9251_16.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_11 (.A0(\ch1_dat[8] ), .B0(n486), .C0(n15739[11]), 
          .D0(n2_adj_2717[11]), .A1(\ch1_dat[9] ), .B1(n486), .C1(n15739[12]), 
          .D1(n2_adj_2717[12]), .CIN(n107131), .COUT(n107132), .S0(n24_adj_2720[11]), 
          .S1(n24_adj_2720[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_11.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_11.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_11.INJECT1_0 = "NO";
    defparam add_9138_add_2_11.INJECT1_1 = "NO";
    CCU2D add_9251_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107417), .COUT(n107418), .S0(n15999[19]), 
          .S1(n15999[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_14.INIT0 = 16'h5666;
    defparam add_9251_14.INIT1 = 16'h5666;
    defparam add_9251_14.INJECT1_0 = "NO";
    defparam add_9251_14.INJECT1_1 = "NO";
    CCU2D add_9251_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107416), .COUT(n107417), .S0(n15999[17]), 
          .S1(n15999[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_12.INIT0 = 16'h5666;
    defparam add_9251_12.INIT1 = 16'h5666;
    defparam add_9251_12.INJECT1_0 = "NO";
    defparam add_9251_12.INJECT1_1 = "NO";
    CCU2D add_9251_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107415), .COUT(n107416), .S0(n15999[15]), 
          .S1(n15999[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_10.INIT0 = 16'h5666;
    defparam add_9251_10.INIT1 = 16'h5666;
    defparam add_9251_10.INJECT1_0 = "NO";
    defparam add_9251_10.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_9 (.A0(\ch1_dat[6] ), .B0(n486), .C0(n15739[9]), 
          .D0(n2_adj_2717[9]), .A1(\ch1_dat[7] ), .B1(n486), .C1(n15739[10]), 
          .D1(n2_adj_2717[10]), .CIN(n107130), .COUT(n107131), .S0(n24_adj_2720[9]), 
          .S1(n24_adj_2720[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_9.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_9.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_9.INJECT1_0 = "NO";
    defparam add_9138_add_2_9.INJECT1_1 = "NO";
    CCU2D add_9169_6 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[9] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[10] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106983), .COUT(n106984), .S0(n15246[9]), 
          .S1(n15246[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_6.INIT0 = 16'h5666;
    defparam add_9169_6.INIT1 = 16'h5666;
    defparam add_9169_6.INJECT1_0 = "NO";
    defparam add_9169_6.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_7 (.A0(\ch1_dat[4] ), .B0(n486), .C0(n15739[7]), 
          .D0(n2_adj_2717[7]), .A1(\ch1_dat[5] ), .B1(n486), .C1(n15739[8]), 
          .D1(n2_adj_2717[8]), .CIN(n107129), .COUT(n107130), .S0(n24_adj_2720[7]), 
          .S1(n24_adj_2720[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_7.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_7.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_7.INJECT1_0 = "NO";
    defparam add_9138_add_2_7.INJECT1_1 = "NO";
    CCU2D add_9169_4 (.A0(\ch1_dat[2] ), .B0(\ch1_dat[7] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\ch1_dat[8] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106982), .COUT(n106983), .S0(n15246[7]), 
          .S1(n15246[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_4.INIT0 = 16'h5666;
    defparam add_9169_4.INIT1 = 16'h5666;
    defparam add_9169_4.INJECT1_0 = "NO";
    defparam add_9169_4.INJECT1_1 = "NO";
    CCU2D add_9169_2 (.A0(\lux_31__N_657[0] ), .B0(\ch1_dat[5] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_657[1] ), .B1(\ch1_dat[6] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106982), .S1(n15246[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[21:31])
    defparam add_9169_2.INIT0 = 16'h7000;
    defparam add_9169_2.INIT1 = 16'h5666;
    defparam add_9169_2.INJECT1_0 = "NO";
    defparam add_9169_2.INJECT1_1 = "NO";
    CCU2D add_9251_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107414), .COUT(n107415), .S0(n15999[13]), 
          .S1(n15999[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_8.INIT0 = 16'h5666;
    defparam add_9251_8.INIT1 = 16'h5666;
    defparam add_9251_8.INJECT1_0 = "NO";
    defparam add_9251_8.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_5 (.A0(\ch1_dat[2] ), .B0(n486), .C0(n15739[5]), 
          .D0(n2_adj_2717[5]), .A1(\ch1_dat[3] ), .B1(n486), .C1(n15739[6]), 
          .D1(n2_adj_2717[6]), .CIN(n107128), .COUT(n107129), .S0(n24_adj_2720[5]), 
          .S1(n24_adj_2720[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_5.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_5.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_5.INJECT1_0 = "NO";
    defparam add_9138_add_2_5.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_12 (.A0(n2_adj_2716[15]), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[16]), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106859), .COUT(n106860), .S0(n27[15]), 
          .S1(n27[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_12.INIT0 = 16'h5666;
    defparam add_9096_add_2_12.INIT1 = 16'h5666;
    defparam add_9096_add_2_12.INJECT1_0 = "NO";
    defparam add_9096_add_2_12.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_10 (.A0(n2_adj_2716[13]), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[14]), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106858), .COUT(n106859), .S0(n27[13]), 
          .S1(n27[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_10.INIT0 = 16'h5666;
    defparam add_9096_add_2_10.INIT1 = 16'h5666;
    defparam add_9096_add_2_10.INJECT1_0 = "NO";
    defparam add_9096_add_2_10.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_27 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106980), 
          .S0(lux_31__N_721[27]));
    defparam sub_31_add_2_27.INIT0 = 16'hffff;
    defparam sub_31_add_2_27.INIT1 = 16'h0000;
    defparam sub_31_add_2_27.INJECT1_0 = "NO";
    defparam sub_31_add_2_27.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_3 (.A0(\lux_31__N_657[0] ), .B0(n486), .C0(n77[3]), 
          .D0(\ch1_dat[3] ), .A1(\lux_31__N_657[1] ), .B1(n486), .C1(n77[4]), 
          .D1(n2_adj_2717[4]), .CIN(n107127), .COUT(n107128), .S0(n24_adj_2720[3]), 
          .S1(n24_adj_2720[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_3.INIT0 = 16'hd1e2;
    defparam add_9138_add_2_3.INIT1 = 16'hd1e2;
    defparam add_9138_add_2_3.INJECT1_0 = "NO";
    defparam add_9138_add_2_3.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_25 (.A0(n27[23]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106979), 
          .COUT(n106980), .S0(lux_31__N_721[25]), .S1(lux_31__N_721[26]));
    defparam sub_31_add_2_25.INIT0 = 16'h5555;
    defparam sub_31_add_2_25.INIT1 = 16'hffff;
    defparam sub_31_add_2_25.INJECT1_0 = "NO";
    defparam sub_31_add_2_25.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_8 (.A0(n2_adj_2716[11]), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[12]), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106857), .COUT(n106858), .S0(n27[11]), 
          .S1(n27[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_8.INIT0 = 16'h5666;
    defparam add_9096_add_2_8.INIT1 = 16'h5666;
    defparam add_9096_add_2_8.INJECT1_0 = "NO";
    defparam add_9096_add_2_8.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_6 (.A0(n2_adj_2716[9]), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2716[10]), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106856), .COUT(n106857), .S0(n27[9]), 
          .S1(n27[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_6.INIT0 = 16'h5666;
    defparam add_9096_add_2_6.INIT1 = 16'h5666;
    defparam add_9096_add_2_6.INJECT1_0 = "NO";
    defparam add_9096_add_2_6.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_23 (.A0(n27[21]), .B0(n15268), .C0(GND_net), .D0(GND_net), 
          .A1(n27[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106978), 
          .COUT(n106979), .S0(lux_31__N_721[23]), .S1(lux_31__N_721[24]));
    defparam sub_31_add_2_23.INIT0 = 16'h5999;
    defparam sub_31_add_2_23.INIT1 = 16'h5555;
    defparam sub_31_add_2_23.INJECT1_0 = "NO";
    defparam sub_31_add_2_23.INJECT1_1 = "NO";
    CCU2D add_9251_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107413), .COUT(n107414), .S0(n15999[11]), 
          .S1(n15999[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_6.INIT0 = 16'h5666;
    defparam add_9251_6.INIT1 = 16'h5666;
    defparam add_9251_6.INJECT1_0 = "NO";
    defparam add_9251_6.INJECT1_1 = "NO";
    CCU2D add_9251_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107412), .COUT(n107413), .S0(n15999[9]), 
          .S1(n15999[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_4.INIT0 = 16'h5666;
    defparam add_9251_4.INIT1 = 16'h5666;
    defparam add_9251_4.INJECT1_0 = "NO";
    defparam add_9251_4.INJECT1_1 = "NO";
    CCU2D add_9251_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107412), .S1(n15999[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9251_2.INIT0 = 16'h7000;
    defparam add_9251_2.INIT1 = 16'h5666;
    defparam add_9251_2.INJECT1_0 = "NO";
    defparam add_9251_2.INJECT1_1 = "NO";
    CCU2D add_9138_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2356), .B1(n21676), .C1(GND_net), .D1(GND_net), 
          .COUT(n107127));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_2_1.INIT0 = 16'hF000;
    defparam add_9138_add_2_1.INIT1 = 16'hffff;
    defparam add_9138_add_2_1.INJECT1_0 = "NO";
    defparam add_9138_add_2_1.INJECT1_1 = "NO";
    CCU2D add_9250_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107410), 
          .S0(n15998));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_cout.INIT0 = 16'h0000;
    defparam add_9250_cout.INIT1 = 16'h0000;
    defparam add_9250_cout.INJECT1_0 = "NO";
    defparam add_9250_cout.INJECT1_1 = "NO";
    CCU2D add_9250_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107409), .COUT(n107410), .S0(n15976[19]), 
          .S1(n15976[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_16.INIT0 = 16'h5666;
    defparam add_9250_16.INIT1 = 16'hfaaa;
    defparam add_9250_16.INJECT1_0 = "NO";
    defparam add_9250_16.INJECT1_1 = "NO";
    CCU2D add_9250_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107408), .COUT(n107409), .S0(n15976[17]), 
          .S1(n15976[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_14.INIT0 = 16'h5666;
    defparam add_9250_14.INIT1 = 16'h5666;
    defparam add_9250_14.INJECT1_0 = "NO";
    defparam add_9250_14.INJECT1_1 = "NO";
    CCU2D add_9250_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107407), .COUT(n107408), .S0(n15976[15]), 
          .S1(n15976[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_12.INIT0 = 16'h5666;
    defparam add_9250_12.INIT1 = 16'h5666;
    defparam add_9250_12.INJECT1_0 = "NO";
    defparam add_9250_12.INJECT1_1 = "NO";
    CCU2D add_9250_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107406), .COUT(n107407), .S0(n15976[13]), 
          .S1(n15976[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_10.INIT0 = 16'h5666;
    defparam add_9250_10.INIT1 = 16'h5666;
    defparam add_9250_10.INJECT1_0 = "NO";
    defparam add_9250_10.INJECT1_1 = "NO";
    CCU2D add_9250_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107405), .COUT(n107406), .S0(n15976[11]), 
          .S1(n15976[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_8.INIT0 = 16'h5666;
    defparam add_9250_8.INIT1 = 16'h5666;
    defparam add_9250_8.INJECT1_0 = "NO";
    defparam add_9250_8.INJECT1_1 = "NO";
    CCU2D add_9250_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107404), .COUT(n107405), .S0(n15976[9]), 
          .S1(n15976[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_6.INIT0 = 16'h5666;
    defparam add_9250_6.INIT1 = 16'h5666;
    defparam add_9250_6.INJECT1_0 = "NO";
    defparam add_9250_6.INJECT1_1 = "NO";
    CCU2D add_9250_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107403), .COUT(n107404), .S0(n15976[7]), 
          .S1(n15976[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_4.INIT0 = 16'h5666;
    defparam add_9250_4.INIT1 = 16'h5666;
    defparam add_9250_4.INJECT1_0 = "NO";
    defparam add_9250_4.INJECT1_1 = "NO";
    CCU2D add_9225_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107123), 
          .S0(n15584));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_cout.INIT0 = 16'h0000;
    defparam add_9225_cout.INIT1 = 16'h0000;
    defparam add_9225_cout.INJECT1_0 = "NO";
    defparam add_9225_cout.INJECT1_1 = "NO";
    CCU2D add_9250_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107403), .S1(n15976[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9250_2.INIT0 = 16'h7000;
    defparam add_9250_2.INIT1 = 16'h5666;
    defparam add_9250_2.INJECT1_0 = "NO";
    defparam add_9250_2.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107401), .S0(n1_adj_2536));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_cout.INIT0 = 16'h0000;
    defparam add_9104_add_1_cout.INIT1 = 16'h0000;
    defparam add_9104_add_1_cout.INJECT1_0 = "NO";
    defparam add_9104_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9225_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107122), .COUT(n107123), .S0(n15564[17]), 
          .S1(n15564[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_16.INIT0 = 16'h5666;
    defparam add_9225_16.INIT1 = 16'hfaaa;
    defparam add_9225_16.INJECT1_0 = "NO";
    defparam add_9225_16.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107400), .COUT(n107401), .S0(n2_adj_2718[23]), 
          .S1(n2_adj_2718[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9104_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9104_add_1_16.INJECT1_0 = "NO";
    defparam add_9104_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107399), .COUT(n107400), .S0(n2_adj_2718[21]), 
          .S1(n2_adj_2718[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9104_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9104_add_1_14.INJECT1_0 = "NO";
    defparam add_9104_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9225_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107121), .COUT(n107122), .S0(n15564[15]), 
          .S1(n15564[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_14.INIT0 = 16'h5666;
    defparam add_9225_14.INIT1 = 16'h5666;
    defparam add_9225_14.INJECT1_0 = "NO";
    defparam add_9225_14.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107398), .COUT(n107399), .S0(n2_adj_2718[19]), 
          .S1(n2_adj_2718[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9104_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9104_add_1_12.INJECT1_0 = "NO";
    defparam add_9104_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9225_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107120), .COUT(n107121), .S0(n15564[13]), 
          .S1(n15564[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_12.INIT0 = 16'h5666;
    defparam add_9225_12.INIT1 = 16'h5666;
    defparam add_9225_12.INJECT1_0 = "NO";
    defparam add_9225_12.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_10 (.A0(\ch0_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107397), .COUT(n107398), .S0(n2_adj_2718[17]), 
          .S1(n2_adj_2718[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9104_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9104_add_1_10.INJECT1_0 = "NO";
    defparam add_9104_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107396), .COUT(n107397), .S0(n2_adj_2718[15]), 
          .S1(n2_adj_2718[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_8.INIT0 = 16'h5666;
    defparam add_9104_add_1_8.INIT1 = 16'h5aaa;
    defparam add_9104_add_1_8.INJECT1_0 = "NO";
    defparam add_9104_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107395), .COUT(n107396), .S0(n2_adj_2718[13]), 
          .S1(n2_adj_2718[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_6.INIT0 = 16'h5666;
    defparam add_9104_add_1_6.INIT1 = 16'h5666;
    defparam add_9104_add_1_6.INJECT1_0 = "NO";
    defparam add_9104_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[11] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[12] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107394), .COUT(n107395), 
          .S0(n2_adj_2718[11]), .S1(n2_adj_2718[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_4.INIT0 = 16'h5666;
    defparam add_9104_add_1_4.INIT1 = 16'h5666;
    defparam add_9104_add_1_4.INJECT1_0 = "NO";
    defparam add_9104_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9225_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107119), .COUT(n107120), .S0(n15564[11]), 
          .S1(n15564[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_10.INIT0 = 16'h5666;
    defparam add_9225_10.INIT1 = 16'h5666;
    defparam add_9225_10.INJECT1_0 = "NO";
    defparam add_9225_10.INJECT1_1 = "NO";
    CCU2D add_9225_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107118), .COUT(n107119), .S0(n15564[9]), 
          .S1(n15564[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_8.INIT0 = 16'h5666;
    defparam add_9225_8.INIT1 = 16'h5666;
    defparam add_9225_8.INJECT1_0 = "NO";
    defparam add_9225_8.INJECT1_1 = "NO";
    CCU2D add_9104_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107394), .S1(n2_adj_2718[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9104_add_1_2.INIT0 = 16'h7000;
    defparam add_9104_add_1_2.INIT1 = 16'h5666;
    defparam add_9104_add_1_2.INJECT1_0 = "NO";
    defparam add_9104_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9225_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107117), .COUT(n107118), .S0(n15564[7]), 
          .S1(n15564[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_6.INIT0 = 16'h5666;
    defparam add_9225_6.INIT1 = 16'h5666;
    defparam add_9225_6.INJECT1_0 = "NO";
    defparam add_9225_6.INJECT1_1 = "NO";
    CCU2D add_9249_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107392), 
          .S0(n15975));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_cout.INIT0 = 16'h0000;
    defparam add_9249_cout.INIT1 = 16'h0000;
    defparam add_9249_cout.INJECT1_0 = "NO";
    defparam add_9249_cout.INJECT1_1 = "NO";
    CCU2D add_9249_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107391), .COUT(n107392), .S0(n15956[16]), 
          .S1(n15956[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_16.INIT0 = 16'h5666;
    defparam add_9249_16.INIT1 = 16'hfaaa;
    defparam add_9249_16.INJECT1_0 = "NO";
    defparam add_9249_16.INJECT1_1 = "NO";
    CCU2D add_9249_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107390), .COUT(n107391), .S0(n15956[14]), 
          .S1(n15956[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_14.INIT0 = 16'h5666;
    defparam add_9249_14.INIT1 = 16'h5666;
    defparam add_9249_14.INJECT1_0 = "NO";
    defparam add_9249_14.INJECT1_1 = "NO";
    CCU2D add_9249_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107389), .COUT(n107390), .S0(n15956[12]), 
          .S1(n15956[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_12.INIT0 = 16'h5666;
    defparam add_9249_12.INIT1 = 16'h5666;
    defparam add_9249_12.INJECT1_0 = "NO";
    defparam add_9249_12.INJECT1_1 = "NO";
    CCU2D add_9249_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107388), .COUT(n107389), .S0(n15956[10]), 
          .S1(n15956[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_10.INIT0 = 16'h5666;
    defparam add_9249_10.INIT1 = 16'h5666;
    defparam add_9249_10.INJECT1_0 = "NO";
    defparam add_9249_10.INJECT1_1 = "NO";
    CCU2D add_9225_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107116), .COUT(n107117), .S0(n15564[5]), 
          .S1(n15564[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_4.INIT0 = 16'h5666;
    defparam add_9225_4.INIT1 = 16'h5666;
    defparam add_9225_4.INJECT1_0 = "NO";
    defparam add_9225_4.INJECT1_1 = "NO";
    CCU2D add_9225_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107116), .S1(n15564[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[19:29])
    defparam add_9225_2.INIT0 = 16'h7000;
    defparam add_9225_2.INIT1 = 16'h5666;
    defparam add_9225_2.INJECT1_0 = "NO";
    defparam add_9225_2.INJECT1_1 = "NO";
    CCU2D add_9249_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107387), .COUT(n107388), .S0(n15956[8]), 
          .S1(n15956[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_8.INIT0 = 16'h5666;
    defparam add_9249_8.INIT1 = 16'h5666;
    defparam add_9249_8.INJECT1_0 = "NO";
    defparam add_9249_8.INJECT1_1 = "NO";
    CCU2D add_9249_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107386), .COUT(n107387), .S0(n15956[6]), 
          .S1(n15956[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_6.INIT0 = 16'h5666;
    defparam add_9249_6.INIT1 = 16'h5666;
    defparam add_9249_6.INJECT1_0 = "NO";
    defparam add_9249_6.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107114), .S0(n1_adj_2520));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_cout.INIT0 = 16'h0000;
    defparam add_9138_add_1_cout.INIT1 = 16'h0000;
    defparam add_9138_add_1_cout.INJECT1_0 = "NO";
    defparam add_9138_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9249_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107385), .COUT(n107386), .S0(n15956[4]), 
          .S1(n15956[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_4.INIT0 = 16'h5666;
    defparam add_9249_4.INIT1 = 16'h5666;
    defparam add_9249_4.INJECT1_0 = "NO";
    defparam add_9249_4.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_16 (.A0(\ch1_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107113), .COUT(n107114), .S0(n2_adj_2717[18]), 
          .S1(n2_adj_2717[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9138_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9138_add_1_16.INJECT1_0 = "NO";
    defparam add_9138_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9249_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107385), .S1(n15956[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9249_2.INIT0 = 16'h7000;
    defparam add_9249_2.INIT1 = 16'h5666;
    defparam add_9249_2.INJECT1_0 = "NO";
    defparam add_9249_2.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_14 (.A0(\ch1_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107112), .COUT(n107113), .S0(n2_adj_2717[16]), 
          .S1(n2_adj_2717[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9138_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9138_add_1_14.INJECT1_0 = "NO";
    defparam add_9138_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_22 (.A0(n2_adj_2722[22]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n1_adj_2553), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107382), .S0(n77_adj_2719[22]), .S1(n77_adj_2719[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_22.INIT0 = 16'h5aaa;
    defparam add_9113_add_4_22.INIT1 = 16'h5aaa;
    defparam add_9113_add_4_22.INJECT1_0 = "NO";
    defparam add_9113_add_4_22.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_12 (.A0(\ch1_dat[10] ), .B0(\ch1_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[11] ), .B1(\ch1_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107111), .COUT(n107112), .S0(n2_adj_2717[14]), 
          .S1(n2_adj_2717[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_12.INIT0 = 16'h5666;
    defparam add_9138_add_1_12.INIT1 = 16'h5666;
    defparam add_9138_add_1_12.INJECT1_0 = "NO";
    defparam add_9138_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_20 (.A0(n2_adj_2722[20]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[21]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107381), .COUT(n107382), .S0(n77_adj_2719[20]), 
          .S1(n77_adj_2719[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_20.INIT0 = 16'h5aaa;
    defparam add_9113_add_4_20.INIT1 = 16'h5aaa;
    defparam add_9113_add_4_20.INJECT1_0 = "NO";
    defparam add_9113_add_4_20.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_18 (.A0(n2_adj_2722[18]), .B0(n15885[18]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[19]), .B1(n15905), .C1(GND_net), 
          .D1(GND_net), .CIN(n107380), .COUT(n107381), .S0(n77_adj_2719[18]), 
          .S1(n77_adj_2719[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_18.INIT0 = 16'h5666;
    defparam add_9113_add_4_18.INIT1 = 16'h5666;
    defparam add_9113_add_4_18.INJECT1_0 = "NO";
    defparam add_9113_add_4_18.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_10 (.A0(\ch1_dat[8] ), .B0(\ch1_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[9] ), .B1(\ch1_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107110), .COUT(n107111), .S0(n2_adj_2717[12]), 
          .S1(n2_adj_2717[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_10.INIT0 = 16'h5666;
    defparam add_9138_add_1_10.INIT1 = 16'h5666;
    defparam add_9138_add_1_10.INJECT1_0 = "NO";
    defparam add_9138_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_8 (.A0(\ch1_dat[6] ), .B0(\ch1_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[7] ), .B1(\ch1_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107109), .COUT(n107110), .S0(n2_adj_2717[10]), 
          .S1(n2_adj_2717[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_8.INIT0 = 16'h5666;
    defparam add_9138_add_1_8.INIT1 = 16'h5666;
    defparam add_9138_add_1_8.INJECT1_0 = "NO";
    defparam add_9138_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_16 (.A0(n2_adj_2722[16]), .B0(n15885[16]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[17]), .B1(n15885[17]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107379), .COUT(n107380), .S0(n77_adj_2719[16]), 
          .S1(n77_adj_2719[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_16.INIT0 = 16'h5666;
    defparam add_9113_add_4_16.INIT1 = 16'h5666;
    defparam add_9113_add_4_16.INJECT1_0 = "NO";
    defparam add_9113_add_4_16.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_6 (.A0(\ch1_dat[4] ), .B0(\ch1_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[5] ), .B1(\ch1_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107108), .COUT(n107109), .S0(n2_adj_2717[8]), 
          .S1(n2_adj_2717[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_6.INIT0 = 16'h5666;
    defparam add_9138_add_1_6.INIT1 = 16'h5666;
    defparam add_9138_add_1_6.INJECT1_0 = "NO";
    defparam add_9138_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9138_add_1_4 (.A0(\ch1_dat[2] ), .B0(\ch1_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch1_dat[3] ), .B1(\ch1_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107107), .COUT(n107108), .S0(n2_adj_2717[6]), 
          .S1(n2_adj_2717[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_4.INIT0 = 16'h5666;
    defparam add_9138_add_1_4.INIT1 = 16'h5666;
    defparam add_9138_add_1_4.INJECT1_0 = "NO";
    defparam add_9138_add_1_4.INJECT1_1 = "NO";
    LUT4 i101830_4_lut (.A(n109755), .B(prox_dat2_15__N_609[12]), .C(prox_dat2_15__N_609[11]), 
         .D(prox_dat2_15__N_609[15]), .Z(prox_dat2_15__N_608)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[5:39])
    defparam i101830_4_lut.init = 16'h0002;
    CCU2D add_9113_add_4_14 (.A0(n2_adj_2722[14]), .B0(n15885[14]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[15]), .B1(n15885[15]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107378), .COUT(n107379), .S0(n77_adj_2719[14]), 
          .S1(n77_adj_2719[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_14.INIT0 = 16'h5666;
    defparam add_9113_add_4_14.INIT1 = 16'h5666;
    defparam add_9113_add_4_14.INJECT1_0 = "NO";
    defparam add_9113_add_4_14.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_12 (.A0(n2_adj_2722[12]), .B0(n15885[12]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[13]), .B1(n15885[13]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107377), .COUT(n107378), .S0(n77_adj_2719[12]), 
          .S1(n77_adj_2719[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_12.INIT0 = 16'h5666;
    defparam add_9113_add_4_12.INIT1 = 16'h5666;
    defparam add_9113_add_4_12.INJECT1_0 = "NO";
    defparam add_9113_add_4_12.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_10 (.A0(n2_adj_2722[10]), .B0(n15885[10]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[11]), .B1(n15885[11]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107376), .COUT(n107377), .S0(n77_adj_2719[10]), 
          .S1(n77_adj_2719[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_10.INIT0 = 16'h5666;
    defparam add_9113_add_4_10.INIT1 = 16'h5666;
    defparam add_9113_add_4_10.INJECT1_0 = "NO";
    defparam add_9113_add_4_10.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_8 (.A0(n2_adj_2722[8]), .B0(n15885[8]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2722[9]), .B1(n15885[9]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107375), .COUT(n107376), .S0(n77_adj_2719[8]), 
          .S1(n77_adj_2719[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_8.INIT0 = 16'h5666;
    defparam add_9113_add_4_8.INIT1 = 16'h5666;
    defparam add_9113_add_4_8.INJECT1_0 = "NO";
    defparam add_9113_add_4_8.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_6 (.A0(\ch0_dat[6] ), .B0(n15885[6]), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_754[0] ), .B1(\ch0_dat[7] ), .C1(n15885[7]), 
          .D1(GND_net), .CIN(n107374), .COUT(n107375), .S0(n77_adj_2719[6]), 
          .S1(n77_adj_2719[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_6.INIT0 = 16'h5666;
    defparam add_9113_add_4_6.INIT1 = 16'h9696;
    defparam add_9113_add_4_6.INJECT1_0 = "NO";
    defparam add_9113_add_4_6.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_4 (.A0(\ch0_dat[4] ), .B0(n15885[4]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(n15885[5]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107373), .COUT(n107374), .S0(n77_adj_2719[4]), 
          .S1(n77_adj_2719[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_4.INIT0 = 16'h5666;
    defparam add_9113_add_4_4.INIT1 = 16'h5666;
    defparam add_9113_add_4_4.INJECT1_0 = "NO";
    defparam add_9113_add_4_4.INJECT1_1 = "NO";
    CCU2D add_9113_add_4_2 (.A0(\lux_31__N_625[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(\ch0_dat[3] ), .D1(GND_net), .COUT(n107373), .S1(n77_adj_2719[3]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_4_2.INIT0 = 16'h7000;
    defparam add_9113_add_4_2.INIT1 = 16'h9696;
    defparam add_9113_add_4_2.INJECT1_0 = "NO";
    defparam add_9113_add_4_2.INJECT1_1 = "NO";
    CCU2D add_9246_20 (.A0(n77_adj_2719[22]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[23]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107370), .S0(n15929[22]), .S1(n15929[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_20.INIT0 = 16'h5aaa;
    defparam add_9246_20.INIT1 = 16'h5aaa;
    defparam add_9246_20.INJECT1_0 = "NO";
    defparam add_9246_20.INJECT1_1 = "NO";
    CCU2D add_9246_18 (.A0(n77_adj_2719[20]), .B0(n15906[20]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[21]), .B1(n15928), .C1(GND_net), 
          .D1(GND_net), .CIN(n107369), .COUT(n107370), .S0(n15929[20]), 
          .S1(n15929[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_18.INIT0 = 16'h5666;
    defparam add_9246_18.INIT1 = 16'h5666;
    defparam add_9246_18.INJECT1_0 = "NO";
    defparam add_9246_18.INJECT1_1 = "NO";
    LUT4 mux_19_i19_3_lut (.A(\lux_31__N_511[19] ), .B(\lux_31__N_543[19] ), 
         .C(lux_31__N_575), .Z(\lux[19] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i19_3_lut.init = 16'hcaca;
    LUT4 mux_19_i26_3_lut (.A(\lux_31__N_511[26] ), .B(\lux_31__N_543[26] ), 
         .C(lux_31__N_575), .Z(\lux[26] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i26_3_lut.init = 16'hcaca;
    CCU2D add_9246_16 (.A0(n77_adj_2719[18]), .B0(n15906[18]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[19]), .B1(n15906[19]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107368), .COUT(n107369), .S0(n15929[18]), 
          .S1(n15929[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_16.INIT0 = 16'h5666;
    defparam add_9246_16.INIT1 = 16'h5666;
    defparam add_9246_16.INJECT1_0 = "NO";
    defparam add_9246_16.INJECT1_1 = "NO";
    CCU2D add_9246_14 (.A0(n77_adj_2719[16]), .B0(n15906[16]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[17]), .B1(n15906[17]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107367), .COUT(n107368), .S0(n15929[16]), 
          .S1(n15929[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_14.INIT0 = 16'h5666;
    defparam add_9246_14.INIT1 = 16'h5666;
    defparam add_9246_14.INJECT1_0 = "NO";
    defparam add_9246_14.INJECT1_1 = "NO";
    CCU2D add_9246_12 (.A0(n77_adj_2719[14]), .B0(n15906[14]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[15]), .B1(n15906[15]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107366), .COUT(n107367), .S0(n15929[14]), 
          .S1(n15929[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_12.INIT0 = 16'h5666;
    defparam add_9246_12.INIT1 = 16'h5666;
    defparam add_9246_12.INJECT1_0 = "NO";
    defparam add_9246_12.INJECT1_1 = "NO";
    LUT4 i101828_2_lut (.A(prox_dat2_15__N_609[13]), .B(prox_dat2_15__N_609[14]), 
         .Z(n109755)) /* synthesis lut_function=(!(A+(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(32[5:39])
    defparam i101828_2_lut.init = 16'h1111;
    CCU2D add_9246_10 (.A0(n77_adj_2719[12]), .B0(n15906[12]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[13]), .B1(n15906[13]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107365), .COUT(n107366), .S0(n15929[12]), 
          .S1(n15929[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_10.INIT0 = 16'h5666;
    defparam add_9246_10.INIT1 = 16'h5666;
    defparam add_9246_10.INJECT1_0 = "NO";
    defparam add_9246_10.INJECT1_1 = "NO";
    CCU2D add_9246_8 (.A0(n77_adj_2719[10]), .B0(n15906[10]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[11]), .B1(n15906[11]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107364), .COUT(n107365), .S0(n15929[10]), 
          .S1(n15929[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_8.INIT0 = 16'h5666;
    defparam add_9246_8.INIT1 = 16'h5666;
    defparam add_9246_8.INJECT1_0 = "NO";
    defparam add_9246_8.INJECT1_1 = "NO";
    CCU2D add_9246_6 (.A0(n77_adj_2719[8]), .B0(n15906[8]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[9]), .B1(n15906[9]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107363), .COUT(n107364), .S0(n15929[8]), 
          .S1(n15929[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_6.INIT0 = 16'h5666;
    defparam add_9246_6.INIT1 = 16'h5666;
    defparam add_9246_6.INJECT1_0 = "NO";
    defparam add_9246_6.INJECT1_1 = "NO";
    CCU2D add_9246_4 (.A0(n77_adj_2719[6]), .B0(n15906[6]), .C0(GND_net), 
          .D0(GND_net), .A1(n77_adj_2719[7]), .B1(n15906[7]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107362), .COUT(n107363), .S0(n15929[6]), 
          .S1(n15929[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_4.INIT0 = 16'h5666;
    defparam add_9246_4.INIT1 = 16'h5666;
    defparam add_9246_4.INJECT1_0 = "NO";
    defparam add_9246_4.INJECT1_1 = "NO";
    CCU2D add_9246_2 (.A0(n77_adj_2719[4]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(n77_adj_2719[5]), .D1(GND_net), .COUT(n107362), .S1(n15929[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9246_2.INIT0 = 16'h7000;
    defparam add_9246_2.INIT1 = 16'h9696;
    defparam add_9246_2.INJECT1_0 = "NO";
    defparam add_9246_2.INJECT1_1 = "NO";
    LUT4 mux_27_i19_4_lut (.A(n764[19]), .B(lux_31__N_721[19]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[19] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i19_4_lut.init = 16'hcac0;
    CCU2D add_9138_add_1_2 (.A0(\lux_31__N_657[0] ), .B0(\ch1_dat[4] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_657[1] ), .B1(\ch1_dat[5] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107107), .S1(n2_adj_2717[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[21:29])
    defparam add_9138_add_1_2.INIT0 = 16'h7000;
    defparam add_9138_add_1_2.INIT1 = 16'h5666;
    defparam add_9138_add_1_2.INJECT1_0 = "NO";
    defparam add_9138_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9245_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107360), 
          .S0(n15928));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_cout.INIT0 = 16'h0000;
    defparam add_9245_cout.INIT1 = 16'h0000;
    defparam add_9245_cout.INJECT1_0 = "NO";
    defparam add_9245_cout.INJECT1_1 = "NO";
    CCU2D add_9245_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107359), .COUT(n107360), .S0(n15906[19]), 
          .S1(n15906[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_16.INIT0 = 16'h5666;
    defparam add_9245_16.INIT1 = 16'hfaaa;
    defparam add_9245_16.INJECT1_0 = "NO";
    defparam add_9245_16.INJECT1_1 = "NO";
    CCU2D add_9245_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107358), .COUT(n107359), .S0(n15906[17]), 
          .S1(n15906[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_14.INIT0 = 16'h5666;
    defparam add_9245_14.INIT1 = 16'h5666;
    defparam add_9245_14.INJECT1_0 = "NO";
    defparam add_9245_14.INJECT1_1 = "NO";
    CCU2D add_9245_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107357), .COUT(n107358), .S0(n15906[15]), 
          .S1(n15906[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_12.INIT0 = 16'h5666;
    defparam add_9245_12.INIT1 = 16'h5666;
    defparam add_9245_12.INJECT1_0 = "NO";
    defparam add_9245_12.INJECT1_1 = "NO";
    CCU2D add_9245_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107356), .COUT(n107357), .S0(n15906[13]), 
          .S1(n15906[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_10.INIT0 = 16'h5666;
    defparam add_9245_10.INIT1 = 16'h5666;
    defparam add_9245_10.INJECT1_0 = "NO";
    defparam add_9245_10.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_21 (.A0(n27[19]), .B0(n15246[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[20]), .B1(n15246[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106977), .COUT(n106978), .S0(lux_31__N_721[21]), 
          .S1(lux_31__N_721[22]));
    defparam sub_31_add_2_21.INIT0 = 16'h5999;
    defparam sub_31_add_2_21.INIT1 = 16'h5999;
    defparam sub_31_add_2_21.INJECT1_0 = "NO";
    defparam sub_31_add_2_21.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_4 (.A0(n2_adj_2716[7]), .B0(\lux_31__N_625[3] ), 
          .C0(GND_net), .D0(GND_net), .A1(n2_adj_2716[8]), .B1(\ch0_dat[3] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n106855), .COUT(n106856), 
          .S0(n27[7]), .S1(n27[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_4.INIT0 = 16'h5666;
    defparam add_9096_add_2_4.INIT1 = 16'h5666;
    defparam add_9096_add_2_4.INJECT1_0 = "NO";
    defparam add_9096_add_2_4.INJECT1_1 = "NO";
    CCU2D add_9096_add_2_2 (.A0(\ch0_dat[5] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n106855), .S1(n27[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(62[9:18])
    defparam add_9096_add_2_2.INIT0 = 16'h7000;
    defparam add_9096_add_2_2.INIT1 = 16'h5666;
    defparam add_9096_add_2_2.INJECT1_0 = "NO";
    defparam add_9096_add_2_2.INJECT1_1 = "NO";
    CCU2D add_9245_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107355), .COUT(n107356), .S0(n15906[11]), 
          .S1(n15906[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_8.INIT0 = 16'h5666;
    defparam add_9245_8.INIT1 = 16'h5666;
    defparam add_9245_8.INJECT1_0 = "NO";
    defparam add_9245_8.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_19 (.A0(n27[17]), .B0(n15246[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[18]), .B1(n15246[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106976), .COUT(n106977), .S0(lux_31__N_721[19]), 
          .S1(lux_31__N_721[20]));
    defparam sub_31_add_2_19.INIT0 = 16'h5999;
    defparam sub_31_add_2_19.INIT1 = 16'h5999;
    defparam sub_31_add_2_19.INJECT1_0 = "NO";
    defparam sub_31_add_2_19.INJECT1_1 = "NO";
    CCU2D add_9245_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107354), .COUT(n107355), .S0(n15906[9]), 
          .S1(n15906[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_6.INIT0 = 16'h5666;
    defparam add_9245_6.INIT1 = 16'h5666;
    defparam add_9245_6.INJECT1_0 = "NO";
    defparam add_9245_6.INJECT1_1 = "NO";
    CCU2D add_9245_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107353), .COUT(n107354), .S0(n15906[7]), 
          .S1(n15906[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_4.INIT0 = 16'h5666;
    defparam add_9245_4.INIT1 = 16'h5666;
    defparam add_9245_4.INJECT1_0 = "NO";
    defparam add_9245_4.INJECT1_1 = "NO";
    CCU2D add_9245_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107353), .S1(n15906[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9245_2.INIT0 = 16'h7000;
    defparam add_9245_2.INIT1 = 16'h5666;
    defparam add_9245_2.INJECT1_0 = "NO";
    defparam add_9245_2.INJECT1_1 = "NO";
    LUT4 i13164_3_lut_4_lut (.A(n764[27]), .B(n82919), .C(lux_31__N_753), 
         .D(lux_31__N_721[27]), .Z(\lux_31__N_511[27] )) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (C (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(65[7] 68[11])
    defparam i13164_3_lut_4_lut.init = 16'hf808;
    CCU2D add_9140_add_3_22 (.A0(n1_adj_2588), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107105), .S0(n15187));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_22.INIT0 = 16'h5aaa;
    defparam add_9140_add_3_22.INIT1 = 16'h0000;
    defparam add_9140_add_3_22.INJECT1_0 = "NO";
    defparam add_9140_add_3_22.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107351), .S0(n1_adj_2553));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_cout.INIT0 = 16'h0000;
    defparam add_9113_add_1_cout.INIT1 = 16'h0000;
    defparam add_9113_add_1_cout.INJECT1_0 = "NO";
    defparam add_9113_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_20 (.A0(n2_adj_2723[21]), .B0(n15559), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107104), .COUT(n107105), .S0(n15185), 
          .S1(n15186));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_20.INIT0 = 16'h5666;
    defparam add_9140_add_3_20.INIT1 = 16'h5aaa;
    defparam add_9140_add_3_20.INJECT1_0 = "NO";
    defparam add_9140_add_3_20.INJECT1_1 = "NO";
    LUT4 mux_19_i18_3_lut (.A(\lux_31__N_511[18] ), .B(\lux_31__N_543[18] ), 
         .C(lux_31__N_575), .Z(\lux[18] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i18_3_lut.init = 16'hcaca;
    CCU2D sub_31_add_2_17 (.A0(n27[15]), .B0(n15246[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[16]), .B1(n15246[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106975), .COUT(n106976), .S0(lux_31__N_721[17]), 
          .S1(lux_31__N_721[18]));
    defparam sub_31_add_2_17.INIT0 = 16'h5999;
    defparam sub_31_add_2_17.INIT1 = 16'h5999;
    defparam sub_31_add_2_17.INJECT1_0 = "NO";
    defparam sub_31_add_2_17.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_18 (.A0(n2_adj_2723[19]), .B0(n15537[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[20]), .B1(n15537[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107103), .COUT(n107104), .S0(n15183), 
          .S1(n15184));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_18.INIT0 = 16'h5666;
    defparam add_9140_add_3_18.INIT1 = 16'h5666;
    defparam add_9140_add_3_18.INJECT1_0 = "NO";
    defparam add_9140_add_3_18.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_15 (.A0(n27[13]), .B0(n15246[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[14]), .B1(n15246[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106974), .COUT(n106975), .S0(lux_31__N_721[15]), 
          .S1(lux_31__N_721[16]));
    defparam sub_31_add_2_15.INIT0 = 16'h5999;
    defparam sub_31_add_2_15.INIT1 = 16'h5999;
    defparam sub_31_add_2_15.INJECT1_0 = "NO";
    defparam sub_31_add_2_15.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_16 (.A0(n2_adj_2723[17]), .B0(n15537[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[18]), .B1(n15537[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107102), .COUT(n107103), .S0(n15181), 
          .S1(n15182));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_16.INIT0 = 16'h5666;
    defparam add_9140_add_3_16.INIT1 = 16'h5666;
    defparam add_9140_add_3_16.INJECT1_0 = "NO";
    defparam add_9140_add_3_16.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_13 (.A0(n27[11]), .B0(n15246[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[12]), .B1(n15246[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106973), .COUT(n106974), .S0(lux_31__N_721[13]), 
          .S1(lux_31__N_721[14]));
    defparam sub_31_add_2_13.INIT0 = 16'h5999;
    defparam sub_31_add_2_13.INIT1 = 16'h5999;
    defparam sub_31_add_2_13.INJECT1_0 = "NO";
    defparam sub_31_add_2_13.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_11 (.A0(n27[9]), .B0(n15246[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n27[10]), .B1(n15246[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106972), .COUT(n106973), .S0(lux_31__N_721[11]), 
          .S1(lux_31__N_721[12]));
    defparam sub_31_add_2_11.INIT0 = 16'h5999;
    defparam sub_31_add_2_11.INIT1 = 16'h5999;
    defparam sub_31_add_2_11.INJECT1_0 = "NO";
    defparam sub_31_add_2_11.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107350), .COUT(n107351), .S0(n2_adj_2722[21]), 
          .S1(n2_adj_2722[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9113_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9113_add_1_16.INJECT1_0 = "NO";
    defparam add_9113_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107349), .COUT(n107350), .S0(n2_adj_2722[19]), 
          .S1(n2_adj_2722[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9113_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9113_add_1_14.INJECT1_0 = "NO";
    defparam add_9113_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107348), .COUT(n107349), .S0(n2_adj_2722[17]), 
          .S1(n2_adj_2722[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9113_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9113_add_1_12.INJECT1_0 = "NO";
    defparam add_9113_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_10 (.A0(\ch0_dat[8] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107347), .COUT(n107348), .S0(n2_adj_2722[15]), 
          .S1(n2_adj_2722[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_10.INIT0 = 16'h5666;
    defparam add_9113_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9113_add_1_10.INJECT1_0 = "NO";
    defparam add_9113_add_1_10.INJECT1_1 = "NO";
    LUT4 LessThan_1522_i19_2_lut_rep_1108_3_lut (.A(n16107[9]), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[9] ), .Z(n111166)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1522_i19_2_lut_rep_1108_3_lut.init = 16'h9696;
    LUT4 LessThan_1522_i16_3_lut_3_lut_4_lut (.A(n16107[9]), .B(\lux_31__N_754[0] ), 
         .C(n8), .D(\ch1_dat[9] ), .Z(n16)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1522_i16_3_lut_3_lut_4_lut.init = 16'h60f6;
    LUT4 LessThan_1516_i17_2_lut_rep_1112_3_lut (.A(n15402[8]), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[8] ), .Z(n111170)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1516_i17_2_lut_rep_1112_3_lut.init = 16'h9696;
    LUT4 LessThan_1516_i14_3_lut_3_lut_4_lut (.A(n15402[8]), .B(\lux_31__N_754[0] ), 
         .C(n12), .D(\ch1_dat[8] ), .Z(n14)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1516_i14_3_lut_3_lut_4_lut.init = 16'h60f6;
    CCU2D sub_31_add_2_9 (.A0(n27[7]), .B0(n15246[7]), .C0(GND_net), .D0(GND_net), 
          .A1(n27[8]), .B1(n15246[8]), .C1(GND_net), .D1(GND_net), .CIN(n106971), 
          .COUT(n106972), .S0(lux_31__N_721[9]), .S1(lux_31__N_721[10]));
    defparam sub_31_add_2_9.INIT0 = 16'h5999;
    defparam sub_31_add_2_9.INIT1 = 16'h5999;
    defparam sub_31_add_2_9.INJECT1_0 = "NO";
    defparam sub_31_add_2_9.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_7 (.A0(\ch0_dat[5] ), .B0(\lux_31__N_754[0] ), .C0(n15246[5]), 
          .D0(GND_net), .A1(n27[6]), .B1(n15246[6]), .C1(GND_net), .D1(GND_net), 
          .CIN(n106970), .COUT(n106971), .S0(lux_31__N_721[7]), .S1(lux_31__N_721[8]));
    defparam sub_31_add_2_7.INIT0 = 16'h9969;
    defparam sub_31_add_2_7.INIT1 = 16'h5999;
    defparam sub_31_add_2_7.INJECT1_0 = "NO";
    defparam sub_31_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_5 (.A0(\ch0_dat[3] ), .B0(\ch1_dat[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch1_dat[4] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106969), .COUT(n106970), .S0(lux_31__N_721[5]), 
          .S1(lux_31__N_721[6]));
    defparam sub_31_add_2_5.INIT0 = 16'h5999;
    defparam sub_31_add_2_5.INIT1 = 16'h5999;
    defparam sub_31_add_2_5.INJECT1_0 = "NO";
    defparam sub_31_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_3 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_657[1] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\ch1_dat[2] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n106968), .COUT(n106969), 
          .S0(lux_31__N_721[3]), .S1(lux_31__N_721[4]));
    defparam sub_31_add_2_3.INIT0 = 16'h5999;
    defparam sub_31_add_2_3.INIT1 = 16'h5999;
    defparam sub_31_add_2_3.INJECT1_0 = "NO";
    defparam sub_31_add_2_3.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107346), .COUT(n107347), .S0(n2_adj_2722[13]), 
          .S1(n2_adj_2722[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_8.INIT0 = 16'h5666;
    defparam add_9113_add_1_8.INIT1 = 16'h5666;
    defparam add_9113_add_1_8.INJECT1_0 = "NO";
    defparam add_9113_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_14 (.A0(n2_adj_2723[15]), .B0(n15537[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[16]), .B1(n15537[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107101), .COUT(n107102), .S0(n15179), 
          .S1(n15180));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_14.INIT0 = 16'h5666;
    defparam add_9140_add_3_14.INIT1 = 16'h5666;
    defparam add_9140_add_3_14.INJECT1_0 = "NO";
    defparam add_9140_add_3_14.INJECT1_1 = "NO";
    CCU2D sub_31_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(\lux_31__N_754[0] ), .B1(\lux_31__N_657[0] ), .C1(GND_net), 
          .D1(GND_net), .COUT(n106968), .S1(lux_31__N_721[2]));
    defparam sub_31_add_2_1.INIT0 = 16'h0000;
    defparam sub_31_add_2_1.INIT1 = 16'h5999;
    defparam sub_31_add_2_1.INJECT1_0 = "NO";
    defparam sub_31_add_2_1.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[11] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[12] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107345), .COUT(n107346), .S0(n2_adj_2722[11]), 
          .S1(n2_adj_2722[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_6.INIT0 = 16'h5666;
    defparam add_9113_add_1_6.INIT1 = 16'h5666;
    defparam add_9113_add_1_6.INJECT1_0 = "NO";
    defparam add_9113_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_12 (.A0(n2_adj_2723[13]), .B0(n15537[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[14]), .B1(n15537[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107100), .COUT(n107101), .S0(n15177), 
          .S1(n15178));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_12.INIT0 = 16'h5666;
    defparam add_9140_add_3_12.INIT1 = 16'h5666;
    defparam add_9140_add_3_12.INJECT1_0 = "NO";
    defparam add_9140_add_3_12.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107344), .COUT(n107345), 
          .S0(n2_adj_2722[9]), .S1(n2_adj_2722[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_4.INIT0 = 16'h5666;
    defparam add_9113_add_1_4.INIT1 = 16'h5666;
    defparam add_9113_add_1_4.INJECT1_0 = "NO";
    defparam add_9113_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9113_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[7] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[8] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107344), .S1(n2_adj_2722[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9113_add_1_2.INIT0 = 16'h7000;
    defparam add_9113_add_1_2.INIT1 = 16'h5666;
    defparam add_9113_add_1_2.INJECT1_0 = "NO";
    defparam add_9113_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9244_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107342), 
          .S0(n15905));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_cout.INIT0 = 16'h0000;
    defparam add_9244_cout.INIT1 = 16'h0000;
    defparam add_9244_cout.INJECT1_0 = "NO";
    defparam add_9244_cout.INJECT1_1 = "NO";
    CCU2D add_1960_29 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106962), 
          .S0(n764[27]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_29.INIT0 = 16'hffff;
    defparam add_1960_29.INIT1 = 16'h0000;
    defparam add_1960_29.INJECT1_0 = "NO";
    defparam add_1960_29.INJECT1_1 = "NO";
    CCU2D add_9244_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107341), .COUT(n107342), .S0(n15885[17]), 
          .S1(n15885[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_16.INIT0 = 16'h5666;
    defparam add_9244_16.INIT1 = 16'hfaaa;
    defparam add_9244_16.INJECT1_0 = "NO";
    defparam add_9244_16.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_10 (.A0(n2_adj_2723[11]), .B0(n15537[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[12]), .B1(n15537[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107099), .COUT(n107100), .S0(n15175), 
          .S1(n15176));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_10.INIT0 = 16'h5666;
    defparam add_9140_add_3_10.INIT1 = 16'h5666;
    defparam add_9140_add_3_10.INJECT1_0 = "NO";
    defparam add_9140_add_3_10.INJECT1_1 = "NO";
    CCU2D add_9244_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107340), .COUT(n107341), .S0(n15885[15]), 
          .S1(n15885[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_14.INIT0 = 16'h5666;
    defparam add_9244_14.INIT1 = 16'h5666;
    defparam add_9244_14.INJECT1_0 = "NO";
    defparam add_9244_14.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_8 (.A0(n2_adj_2723[9]), .B0(n15537[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2723[10]), .B1(n15537[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107098), .COUT(n107099), .S0(n15173), 
          .S1(n15174));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_8.INIT0 = 16'h5666;
    defparam add_9140_add_3_8.INIT1 = 16'h5666;
    defparam add_9140_add_3_8.INJECT1_0 = "NO";
    defparam add_9140_add_3_8.INJECT1_1 = "NO";
    LUT4 LessThan_1513_i13_2_lut_3_lut (.A(n56[6]), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[6] ), .Z(n13)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1513_i13_2_lut_3_lut.init = 16'h9696;
    LUT4 LessThan_1513_i12_3_lut_3_lut_4_lut (.A(n56[6]), .B(\lux_31__N_754[0] ), 
         .C(\lux_31__N_576[7] ), .D(\ch1_dat[7] ), .Z(n12_adj_111)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1513_i12_3_lut_3_lut_4_lut.init = 16'h60f6;
    LUT4 i99320_2_lut_rep_1139 (.A(n20[5]), .B(\lux_31__N_754[0] ), .Z(n111197)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99320_2_lut_rep_1139.init = 16'h6666;
    LUT4 LessThan_1522_i10_3_lut_3_lut_4_lut (.A(n20[5]), .B(\lux_31__N_754[0] ), 
         .C(n15068), .D(\ch1_dat[6] ), .Z(n10)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1522_i10_3_lut_3_lut_4_lut.init = 16'h60f6;
    LUT4 LessThan_1522_i11_2_lut_rep_1132_3_lut (.A(n20[5]), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[5] ), .Z(n111190)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1522_i11_2_lut_rep_1132_3_lut.init = 16'h9696;
    LUT4 LessThan_1516_i9_2_lut_rep_1133_3_lut (.A(n19[4]), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[4] ), .Z(n111191)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1516_i9_2_lut_rep_1133_3_lut.init = 16'h9696;
    CCU2D add_9140_add_3_6 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[7] ), 
          .C0(n15537[7]), .D0(GND_net), .A1(n2_adj_2723[8]), .B1(n15537[8]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107097), .COUT(n107098), 
          .S0(n15171), .S1(n15172));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_6.INIT0 = 16'h9696;
    defparam add_9140_add_3_6.INIT1 = 16'h5666;
    defparam add_9140_add_3_6.INJECT1_0 = "NO";
    defparam add_9140_add_3_6.INJECT1_1 = "NO";
    CCU2D add_9244_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107339), .COUT(n107340), .S0(n15885[13]), 
          .S1(n15885[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_12.INIT0 = 16'h5666;
    defparam add_9244_12.INIT1 = 16'h5666;
    defparam add_9244_12.INJECT1_0 = "NO";
    defparam add_9244_12.INJECT1_1 = "NO";
    CCU2D add_9140_add_3_4 (.A0(\lux_31__N_625[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(\ch0_dat[5] ), .D0(GND_net), .A1(\ch0_dat[6] ), .B1(n15537[6]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107096), .COUT(n107097), 
          .S0(n15169), .S1(n15170));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_4.INIT0 = 16'h9696;
    defparam add_9140_add_3_4.INIT1 = 16'h5666;
    defparam add_9140_add_3_4.INJECT1_0 = "NO";
    defparam add_9140_add_3_4.INJECT1_1 = "NO";
    CCU2D add_1960_27 (.A0(n15857[24]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106961), 
          .COUT(n106962), .S0(n764[25]), .S1(n764[26]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_27.INIT0 = 16'h5555;
    defparam add_1960_27.INIT1 = 16'hffff;
    defparam add_1960_27.INJECT1_0 = "NO";
    defparam add_1960_27.INJECT1_1 = "NO";
    CCU2D add_9244_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107338), .COUT(n107339), .S0(n15885[11]), 
          .S1(n15885[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_10.INIT0 = 16'h5666;
    defparam add_9244_10.INIT1 = 16'h5666;
    defparam add_9244_10.INJECT1_0 = "NO";
    defparam add_9244_10.INJECT1_1 = "NO";
    LUT4 LessThan_1516_i8_3_lut_3_lut_4_lut (.A(n19[4]), .B(\lux_31__N_754[0] ), 
         .C(\lux_31__N_754[3] ), .D(\ch1_dat[4] ), .Z(n8_adj_112)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1516_i8_3_lut_3_lut_4_lut.init = 16'h60f6;
    CCU2D add_9140_add_3_2 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107096), .S1(n15168));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_3_2.INIT0 = 16'h7000;
    defparam add_9140_add_3_2.INIT1 = 16'h5666;
    defparam add_9140_add_3_2.INJECT1_0 = "NO";
    defparam add_9140_add_3_2.INJECT1_1 = "NO";
    CCU2D add_1960_25 (.A0(n15739[23]), .B0(n486), .C0(n15857[22]), .D0(GND_net), 
          .A1(n15857[23]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106960), .COUT(n106961), .S0(n764[23]), .S1(n764[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_25.INIT0 = 16'h8787;
    defparam add_1960_25.INIT1 = 16'h5555;
    defparam add_1960_25.INJECT1_0 = "NO";
    defparam add_1960_25.INJECT1_1 = "NO";
    CCU2D add_9244_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107337), .COUT(n107338), .S0(n15885[9]), 
          .S1(n15885[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_8.INIT0 = 16'h5666;
    defparam add_9244_8.INIT1 = 16'h5666;
    defparam add_9244_8.INJECT1_0 = "NO";
    defparam add_9244_8.INJECT1_1 = "NO";
    CCU2D add_1960_23 (.A0(n15739[21]), .B0(n486), .C0(n15857[20]), .D0(GND_net), 
          .A1(n15739[22]), .B1(n486), .C1(n15857[21]), .D1(GND_net), 
          .CIN(n106959), .COUT(n106960), .S0(n764[21]), .S1(n764[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_23.INIT0 = 16'h8787;
    defparam add_1960_23.INIT1 = 16'h8787;
    defparam add_1960_23.INJECT1_0 = "NO";
    defparam add_1960_23.INJECT1_1 = "NO";
    CCU2D add_1960_21 (.A0(n15857[18]), .B0(n24_adj_2720[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[19]), .B1(n24_adj_2720[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106958), .COUT(n106959), .S0(n764[19]), 
          .S1(n764[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_21.INIT0 = 16'h5999;
    defparam add_1960_21.INIT1 = 16'h5999;
    defparam add_1960_21.INJECT1_0 = "NO";
    defparam add_1960_21.INJECT1_1 = "NO";
    CCU2D add_9244_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107336), .COUT(n107337), .S0(n15885[7]), 
          .S1(n15885[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_6.INIT0 = 16'h5666;
    defparam add_9244_6.INIT1 = 16'h5666;
    defparam add_9244_6.INJECT1_0 = "NO";
    defparam add_9244_6.INJECT1_1 = "NO";
    CCU2D add_9244_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107335), .COUT(n107336), .S0(n15885[5]), 
          .S1(n15885[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_4.INIT0 = 16'h5666;
    defparam add_9244_4.INIT1 = 16'h5666;
    defparam add_9244_4.INJECT1_0 = "NO";
    defparam add_9244_4.INJECT1_1 = "NO";
    CCU2D add_9244_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107335), .S1(n15885[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(64[9:18])
    defparam add_9244_2.INIT0 = 16'h7000;
    defparam add_9244_2.INIT1 = 16'h5666;
    defparam add_9244_2.INJECT1_0 = "NO";
    defparam add_9244_2.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107094), .S0(n1_adj_2588));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_cout.INIT0 = 16'h0000;
    defparam add_9140_add_1_cout.INIT1 = 16'h0000;
    defparam add_9140_add_1_cout.INJECT1_0 = "NO";
    defparam add_9140_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9350_26 (.A0(n1_adj_2536), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107333), 
          .S0(n19[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_26.INIT0 = 16'h5aaa;
    defparam add_9350_26.INIT1 = 16'h0000;
    defparam add_9350_26.INJECT1_0 = "NO";
    defparam add_9350_26.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107093), .COUT(n107094), .S0(n2_adj_2723[21]), 
          .S1(n2_adj_2723[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9140_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9140_add_1_16.INJECT1_0 = "NO";
    defparam add_9140_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9350_24 (.A0(n2_adj_2718[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[24]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107332), .COUT(n107333), .S0(n19[23]), 
          .S1(n19[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_24.INIT0 = 16'h5aaa;
    defparam add_9350_24.INIT1 = 16'h5aaa;
    defparam add_9350_24.INJECT1_0 = "NO";
    defparam add_9350_24.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107092), .COUT(n107093), .S0(n2_adj_2723[19]), 
          .S1(n2_adj_2723[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9140_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9140_add_1_14.INJECT1_0 = "NO";
    defparam add_9140_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9350_22 (.A0(n2_adj_2718[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107331), .COUT(n107332), .S0(n19[21]), 
          .S1(n19[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_22.INIT0 = 16'h5aaa;
    defparam add_9350_22.INIT1 = 16'h5aaa;
    defparam add_9350_22.INJECT1_0 = "NO";
    defparam add_9350_22.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107091), .COUT(n107092), .S0(n2_adj_2723[17]), 
          .S1(n2_adj_2723[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9140_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9140_add_1_12.INJECT1_0 = "NO";
    defparam add_9140_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9350_20 (.A0(n2_adj_2718[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107330), .COUT(n107331), .S0(n19[19]), 
          .S1(n19[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_20.INIT0 = 16'h5aaa;
    defparam add_9350_20.INIT1 = 16'h5aaa;
    defparam add_9350_20.INJECT1_0 = "NO";
    defparam add_9350_20.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_10 (.A0(\ch0_dat[8] ), .B0(\ch0_dat[15] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107090), .COUT(n107091), .S0(n2_adj_2723[15]), 
          .S1(n2_adj_2723[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_10.INIT0 = 16'h5666;
    defparam add_9140_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9140_add_1_10.INJECT1_0 = "NO";
    defparam add_9140_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9350_18 (.A0(n2_adj_2718[17]), .B0(n15956[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[18]), .B1(n15975), .C1(GND_net), 
          .D1(GND_net), .CIN(n107329), .COUT(n107330), .S0(n19[17]), 
          .S1(n19[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_18.INIT0 = 16'h5666;
    defparam add_9350_18.INIT1 = 16'h5666;
    defparam add_9350_18.INJECT1_0 = "NO";
    defparam add_9350_18.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[13] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(\ch0_dat[14] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107089), .COUT(n107090), .S0(n2_adj_2723[13]), 
          .S1(n2_adj_2723[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_8.INIT0 = 16'h5666;
    defparam add_9140_add_1_8.INIT1 = 16'h5666;
    defparam add_9140_add_1_8.INJECT1_0 = "NO";
    defparam add_9140_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9350_16 (.A0(n2_adj_2718[15]), .B0(n15956[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[16]), .B1(n15956[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107328), .COUT(n107329), .S0(n19[15]), 
          .S1(n19[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_16.INIT0 = 16'h5666;
    defparam add_9350_16.INIT1 = 16'h5666;
    defparam add_9350_16.INJECT1_0 = "NO";
    defparam add_9350_16.INJECT1_1 = "NO";
    CCU2D add_9350_14 (.A0(n2_adj_2718[13]), .B0(n15956[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[14]), .B1(n15956[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107327), .COUT(n107328), .S0(n19[13]), 
          .S1(n19[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_14.INIT0 = 16'h5666;
    defparam add_9350_14.INIT1 = 16'h5666;
    defparam add_9350_14.INJECT1_0 = "NO";
    defparam add_9350_14.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[11] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[12] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107088), .COUT(n107089), .S0(n2_adj_2723[11]), 
          .S1(n2_adj_2723[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_6.INIT0 = 16'h5666;
    defparam add_9140_add_1_6.INIT1 = 16'h5666;
    defparam add_9140_add_1_6.INJECT1_0 = "NO";
    defparam add_9140_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9350_12 (.A0(n2_adj_2718[11]), .B0(n15956[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[12]), .B1(n15956[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107326), .COUT(n107327), .S0(n19[11]), 
          .S1(n19[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_12.INIT0 = 16'h5666;
    defparam add_9350_12.INIT1 = 16'h5666;
    defparam add_9350_12.INJECT1_0 = "NO";
    defparam add_9350_12.INJECT1_1 = "NO";
    CCU2D add_9350_10 (.A0(n2_adj_2718[9]), .B0(n15956[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2718[10]), .B1(n15956[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107325), .COUT(n107326), .S0(n19[9]), 
          .S1(n19[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_10.INIT0 = 16'h5666;
    defparam add_9350_10.INIT1 = 16'h5666;
    defparam add_9350_10.INJECT1_0 = "NO";
    defparam add_9350_10.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[9] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[10] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107087), .COUT(n107088), 
          .S0(n2_adj_2723[9]), .S1(n2_adj_2723[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_4.INIT0 = 16'h5666;
    defparam add_9140_add_1_4.INIT1 = 16'h5666;
    defparam add_9140_add_1_4.INJECT1_0 = "NO";
    defparam add_9140_add_1_4.INJECT1_1 = "NO";
    LUT4 i101779_2_lut_rep_1164 (.A(prox_dat2[10]), .B(prox_dat2[11]), .Z(n111222)) /* synthesis lut_function=(!(A (B))) */ ;
    defparam i101779_2_lut_rep_1164.init = 16'h7777;
    LUT4 i101781_2_lut_3_lut (.A(prox_dat2[10]), .B(prox_dat2[11]), .C(prox_dat2[9]), 
         .Z(led_c_7)) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i101781_2_lut_3_lut.init = 16'h7f7f;
    LUT4 i99338_2_lut_rep_1174 (.A(\lux_31__N_625[3] ), .B(\lux_31__N_754[0] ), 
         .Z(n111232)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99338_2_lut_rep_1174.init = 16'h6666;
    LUT4 LessThan_1522_i6_3_lut_3_lut_4_lut (.A(\lux_31__N_625[3] ), .B(\lux_31__N_754[0] ), 
         .C(n15065), .D(\ch1_dat[3] ), .Z(n6)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1522_i6_3_lut_3_lut_4_lut.init = 16'h60f6;
    LUT4 LessThan_1522_i5_2_lut_3_lut (.A(\lux_31__N_625[3] ), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[2] ), .Z(n5)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1522_i5_2_lut_3_lut.init = 16'h9696;
    CCU2D add_9350_8 (.A0(\ch0_dat[7] ), .B0(n15956[7]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(n15956[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107324), .COUT(n107325), .S0(n19[7]), 
          .S1(n19[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_8.INIT0 = 16'h5666;
    defparam add_9350_8.INIT1 = 16'h5666;
    defparam add_9350_8.INJECT1_0 = "NO";
    defparam add_9350_8.INJECT1_1 = "NO";
    CCU2D add_9140_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[7] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[8] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107087), .S1(n2_adj_2723[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9140_add_1_2.INIT0 = 16'h7000;
    defparam add_9140_add_1_2.INIT1 = 16'h5666;
    defparam add_9140_add_1_2.INJECT1_0 = "NO";
    defparam add_9140_add_1_2.INJECT1_1 = "NO";
    CCU2D add_1960_19 (.A0(n15857[16]), .B0(n24_adj_2720[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[17]), .B1(n24_adj_2720[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106957), .COUT(n106958), .S0(n764[17]), 
          .S1(n764[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_19.INIT0 = 16'h5999;
    defparam add_1960_19.INIT1 = 16'h5999;
    defparam add_1960_19.INJECT1_0 = "NO";
    defparam add_1960_19.INJECT1_1 = "NO";
    LUT4 i99326_2_lut_rep_1181 (.A(\ch0_dat[3] ), .B(\lux_31__N_754[0] ), 
         .Z(n111239)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99326_2_lut_rep_1181.init = 16'h6666;
    LUT4 LessThan_1519_i13_2_lut_rep_1161_3_lut (.A(\ch0_dat[3] ), .B(\lux_31__N_754[0] ), 
         .C(\ch1_dat[6] ), .Z(n111219)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam LessThan_1519_i13_2_lut_rep_1161_3_lut.init = 16'h9696;
    LUT4 LessThan_1519_i12_3_lut_3_lut_4_lut (.A(\ch0_dat[3] ), .B(\lux_31__N_754[0] ), 
         .C(\lux_31__N_625[3] ), .D(\ch1_dat[6] ), .Z(n12_adj_113)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam LessThan_1519_i12_3_lut_3_lut_4_lut.init = 16'h60f6;
    LUT4 i99364_2_lut_rep_1182 (.A(\lux_31__N_625[2] ), .B(\lux_31__N_754[0] ), 
         .Z(n111240)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99364_2_lut_rep_1182.init = 16'h6666;
    CCU2D add_9350_6 (.A0(\ch0_dat[5] ), .B0(n15956[5]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(n15956[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107323), .COUT(n107324), .S0(n19[5]), 
          .S1(n19[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_6.INIT0 = 16'h5666;
    defparam add_9350_6.INIT1 = 16'h5666;
    defparam add_9350_6.INJECT1_0 = "NO";
    defparam add_9350_6.INJECT1_1 = "NO";
    CCU2D add_9350_4 (.A0(\ch0_dat[3] ), .B0(n15956[3]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(n15956[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107322), .COUT(n107323), .S0(\lux_31__N_754[3] ), 
          .S1(n19[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_4.INIT0 = 16'h5666;
    defparam add_9350_4.INIT1 = 16'h5666;
    defparam add_9350_4.INJECT1_0 = "NO";
    defparam add_9350_4.INJECT1_1 = "NO";
    CCU2D add_9350_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(n111240), 
          .C1(GND_net), .D1(GND_net), .COUT(n107322), .S1(\lux_31__N_754[2] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[18:28])
    defparam add_9350_2.INIT0 = 16'h7000;
    defparam add_9350_2.INIT1 = 16'h5666;
    defparam add_9350_2.INJECT1_0 = "NO";
    defparam add_9350_2.INJECT1_1 = "NO";
    LUT4 mux_19_i9_3_lut (.A(\lux_31__N_511[9] ), .B(\lux_31__N_543[9] ), 
         .C(lux_31__N_575), .Z(\lux[9] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i9_3_lut.init = 16'hcaca;
    LUT4 mux_27_i9_4_lut (.A(n764[9]), .B(lux_31__N_721[9]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[9] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i9_4_lut.init = 16'hcac0;
    LUT4 i101796_2_lut_3_lut (.A(prox_dat2[9]), .B(prox_dat2[10]), .C(prox_dat2[11]), 
         .Z(led_c_1)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;
    defparam i101796_2_lut_3_lut.init = 16'h0101;
    LUT4 i101784_2_lut_3_lut (.A(prox_dat2[9]), .B(prox_dat2[10]), .C(prox_dat2[11]), 
         .Z(led_c_5)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
    defparam i101784_2_lut_3_lut.init = 16'h1f1f;
    LUT4 mux_19_i8_3_lut (.A(\lux_31__N_511[8] ), .B(\lux_31__N_543[8] ), 
         .C(lux_31__N_575), .Z(\lux[8] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i8_3_lut.init = 16'hcaca;
    LUT4 mux_27_i8_4_lut (.A(n764[8]), .B(lux_31__N_721[8]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[8] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i8_4_lut.init = 16'hcac0;
    LUT4 i99342_2_lut (.A(\lux_31__N_657[0] ), .B(\ch1_dat[7] ), .Z(n2_adj_2712[7])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99342_2_lut.init = 16'h6666;
    LUT4 i99341_2_lut (.A(\ch1_dat[3] ), .B(\lux_31__N_657[0] ), .Z(n15693[4])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99341_2_lut.init = 16'h6666;
    LUT4 i99363_2_lut (.A(n15976[6]), .B(\lux_31__N_754[0] ), .Z(n16024[6])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99363_2_lut.init = 16'h6666;
    LUT4 mux_19_i7_3_lut (.A(\lux_31__N_511[7] ), .B(\lux_31__N_543[7] ), 
         .C(lux_31__N_575), .Z(\lux[7] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i7_3_lut.init = 16'hcaca;
    LUT4 mux_27_i7_4_lut (.A(n764[7]), .B(lux_31__N_721[7]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[7] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i7_4_lut.init = 16'hcac0;
    LUT4 i99325_2_lut (.A(n56_adj_2711[8]), .B(\lux_31__N_754[0] ), .Z(lux_31__N_625[9])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99325_2_lut.init = 16'h6666;
    LUT4 i99365_2_lut (.A(n24[6]), .B(\lux_31__N_657[0] ), .Z(lux_31__N_657[6])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99365_2_lut.init = 16'h6666;
    LUT4 i99314_2_lut (.A(\lux_31__N_657[0] ), .B(\ch1_dat[10] ), .Z(n2_adj_2713[10])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99314_2_lut.init = 16'h6666;
    LUT4 i99337_2_lut (.A(n15585[7]), .B(\lux_31__N_754[0] ), .Z(n15635[7])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99337_2_lut.init = 16'h6666;
    LUT4 i99311_2_lut (.A(\ch1_dat[2] ), .B(\lux_31__N_657[0] ), .Z(n15351[4])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i99311_2_lut.init = 16'h6666;
    LUT4 mux_19_i6_3_lut (.A(\lux_31__N_511[6] ), .B(\lux_31__N_543[6] ), 
         .C(lux_31__N_575), .Z(\lux[6] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i6_3_lut.init = 16'hcaca;
    LUT4 mux_27_i6_4_lut (.A(n764[6]), .B(lux_31__N_721[6]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[6] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i6_4_lut.init = 16'hcac0;
    CCU2D add_9241_23 (.A0(n15856), .B0(n486), .C0(n15929[22]), .D0(n25[23]), 
          .A1(GND_net), .B1(n486), .C1(n15929[23]), .D1(n25[24]), .CIN(n107319), 
          .S0(n15857[23]), .S1(n15857[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_23.INIT0 = 16'hd1e2;
    defparam add_9241_23.INIT1 = 16'h596a;
    defparam add_9241_23.INJECT1_0 = "NO";
    defparam add_9241_23.INJECT1_1 = "NO";
    CCU2D add_9241_21 (.A0(n15832[21]), .B0(n486), .C0(n15929[20]), .D0(n25[21]), 
          .A1(n15832[22]), .B1(n486), .C1(n15929[21]), .D1(n25[22]), 
          .CIN(n107318), .COUT(n107319), .S0(n15857[21]), .S1(n15857[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_21.INIT0 = 16'hd1e2;
    defparam add_9241_21.INIT1 = 16'hd1e2;
    defparam add_9241_21.INJECT1_0 = "NO";
    defparam add_9241_21.INJECT1_1 = "NO";
    CCU2D add_9241_19 (.A0(n15832[19]), .B0(n486), .C0(n15929[18]), .D0(n25[19]), 
          .A1(n15832[20]), .B1(n486), .C1(n15929[19]), .D1(n25[20]), 
          .CIN(n107317), .COUT(n107318), .S0(n15857[19]), .S1(n15857[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_19.INIT0 = 16'hd1e2;
    defparam add_9241_19.INIT1 = 16'hd1e2;
    defparam add_9241_19.INJECT1_0 = "NO";
    defparam add_9241_19.INJECT1_1 = "NO";
    CCU2D add_9241_17 (.A0(n15832[17]), .B0(n486), .C0(n15929[16]), .D0(n25[17]), 
          .A1(n15832[18]), .B1(n486), .C1(n15929[17]), .D1(n25[18]), 
          .CIN(n107316), .COUT(n107317), .S0(n15857[17]), .S1(n15857[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_17.INIT0 = 16'hd1e2;
    defparam add_9241_17.INIT1 = 16'hd1e2;
    defparam add_9241_17.INJECT1_0 = "NO";
    defparam add_9241_17.INJECT1_1 = "NO";
    LUT4 mux_19_i5_3_lut (.A(\lux_31__N_511[5] ), .B(\lux_31__N_543[5] ), 
         .C(lux_31__N_575), .Z(\lux[5] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i5_3_lut.init = 16'hcaca;
    LUT4 mux_27_i5_4_lut (.A(n764[5]), .B(lux_31__N_721[5]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[5] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i5_4_lut.init = 16'hcac0;
    LUT4 mux_19_i4_3_lut (.A(\lux_31__N_511[4] ), .B(\lux_31__N_543[4] ), 
         .C(lux_31__N_575), .Z(\lux[4] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i4_3_lut.init = 16'hcaca;
    LUT4 mux_27_i4_4_lut (.A(n764[4]), .B(lux_31__N_721[4]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[4] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i4_4_lut.init = 16'hcac0;
    CCU2D add_9241_15 (.A0(n15832[15]), .B0(n486), .C0(n15929[14]), .D0(n25[15]), 
          .A1(n15832[16]), .B1(n486), .C1(n15929[15]), .D1(n25[16]), 
          .CIN(n107315), .COUT(n107316), .S0(n15857[15]), .S1(n15857[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_15.INIT0 = 16'hd1e2;
    defparam add_9241_15.INIT1 = 16'hd1e2;
    defparam add_9241_15.INJECT1_0 = "NO";
    defparam add_9241_15.INJECT1_1 = "NO";
    CCU2D add_9241_13 (.A0(n15832[13]), .B0(n486), .C0(n15929[12]), .D0(n25[13]), 
          .A1(n15832[14]), .B1(n486), .C1(n15929[13]), .D1(n25[14]), 
          .CIN(n107314), .COUT(n107315), .S0(n15857[13]), .S1(n15857[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_13.INIT0 = 16'hd1e2;
    defparam add_9241_13.INIT1 = 16'hd1e2;
    defparam add_9241_13.INJECT1_0 = "NO";
    defparam add_9241_13.INJECT1_1 = "NO";
    CCU2D add_9241_11 (.A0(n15832[11]), .B0(n486), .C0(n15929[10]), .D0(n25[11]), 
          .A1(n15832[12]), .B1(n486), .C1(n15929[11]), .D1(n25[12]), 
          .CIN(n107313), .COUT(n107314), .S0(n15857[11]), .S1(n15857[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_11.INIT0 = 16'hd1e2;
    defparam add_9241_11.INIT1 = 16'hd1e2;
    defparam add_9241_11.INJECT1_0 = "NO";
    defparam add_9241_11.INJECT1_1 = "NO";
    CCU2D add_9218_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107085), 
          .S0(n15559));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_cout.INIT0 = 16'h0000;
    defparam add_9218_cout.INIT1 = 16'h0000;
    defparam add_9218_cout.INJECT1_0 = "NO";
    defparam add_9218_cout.INJECT1_1 = "NO";
    CCU2D add_1960_17 (.A0(n15857[14]), .B0(n24_adj_2720[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[15]), .B1(n24_adj_2720[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106956), .COUT(n106957), .S0(n764[15]), 
          .S1(n764[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_17.INIT0 = 16'h5999;
    defparam add_1960_17.INIT1 = 16'h5999;
    defparam add_1960_17.INJECT1_0 = "NO";
    defparam add_1960_17.INJECT1_1 = "NO";
    CCU2D add_9218_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107084), .COUT(n107085), .S0(n15537[19]), 
          .S1(n15537[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_16.INIT0 = 16'hfaaa;
    defparam add_9218_16.INIT1 = 16'hfaaa;
    defparam add_9218_16.INJECT1_0 = "NO";
    defparam add_9218_16.INJECT1_1 = "NO";
    CCU2D add_1960_15 (.A0(n15857[12]), .B0(n24_adj_2720[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[13]), .B1(n24_adj_2720[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106955), .COUT(n106956), .S0(n764[13]), 
          .S1(n764[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_15.INIT0 = 16'h5999;
    defparam add_1960_15.INIT1 = 16'h5999;
    defparam add_1960_15.INJECT1_0 = "NO";
    defparam add_1960_15.INJECT1_1 = "NO";
    CCU2D add_1960_13 (.A0(n15857[10]), .B0(n24_adj_2720[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[11]), .B1(n24_adj_2720[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106954), .COUT(n106955), .S0(n764[11]), 
          .S1(n764[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_13.INIT0 = 16'h5999;
    defparam add_1960_13.INIT1 = 16'h5999;
    defparam add_1960_13.INJECT1_0 = "NO";
    defparam add_1960_13.INJECT1_1 = "NO";
    CCU2D add_9218_14 (.A0(\ch0_dat[14] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107083), .COUT(n107084), .S0(n15537[17]), 
          .S1(n15537[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_14.INIT0 = 16'h5666;
    defparam add_9218_14.INIT1 = 16'h5666;
    defparam add_9218_14.INJECT1_0 = "NO";
    defparam add_9218_14.INJECT1_1 = "NO";
    CCU2D add_1960_11 (.A0(n15857[8]), .B0(n24_adj_2720[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[9]), .B1(n24_adj_2720[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106953), .COUT(n106954), .S0(n764[9]), 
          .S1(n764[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_11.INIT0 = 16'h5999;
    defparam add_1960_11.INIT1 = 16'h5999;
    defparam add_1960_11.INJECT1_0 = "NO";
    defparam add_1960_11.INJECT1_1 = "NO";
    CCU2D add_1960_9 (.A0(n15857[6]), .B0(n24_adj_2720[7]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[7]), .B1(n24_adj_2720[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106952), .COUT(n106953), .S0(n764[7]), 
          .S1(n764[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_9.INIT0 = 16'h5999;
    defparam add_1960_9.INIT1 = 16'h5999;
    defparam add_1960_9.INJECT1_0 = "NO";
    defparam add_1960_9.INJECT1_1 = "NO";
    CCU2D add_9218_12 (.A0(\ch0_dat[12] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107082), .COUT(n107083), .S0(n15537[15]), 
          .S1(n15537[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_12.INIT0 = 16'h5666;
    defparam add_9218_12.INIT1 = 16'h5666;
    defparam add_9218_12.INJECT1_0 = "NO";
    defparam add_9218_12.INJECT1_1 = "NO";
    CCU2D add_1960_7 (.A0(n15857[4]), .B0(n24_adj_2720[5]), .C0(GND_net), 
          .D0(GND_net), .A1(n15857[5]), .B1(n24_adj_2720[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106951), .COUT(n106952), .S0(n764[5]), 
          .S1(n764[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_7.INIT0 = 16'h5999;
    defparam add_1960_7.INIT1 = 16'h5999;
    defparam add_1960_7.INJECT1_0 = "NO";
    defparam add_1960_7.INJECT1_1 = "NO";
    CCU2D add_9241_9 (.A0(n15832[9]), .B0(n486), .C0(n15929[8]), .D0(n25[9]), 
          .A1(n15832[10]), .B1(n486), .C1(n15929[9]), .D1(n25[10]), 
          .CIN(n107312), .COUT(n107313), .S0(n15857[9]), .S1(n15857[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_9.INIT0 = 16'hd1e2;
    defparam add_9241_9.INIT1 = 16'hd1e2;
    defparam add_9241_9.INJECT1_0 = "NO";
    defparam add_9241_9.INJECT1_1 = "NO";
    CCU2D add_9241_7 (.A0(n15832[7]), .B0(n486), .C0(n15929[6]), .D0(n25[7]), 
          .A1(n15832[8]), .B1(n486), .C1(n15929[7]), .D1(n25[8]), .CIN(n107311), 
          .COUT(n107312), .S0(n15857[7]), .S1(n15857[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_7.INIT0 = 16'hd1e2;
    defparam add_9241_7.INIT1 = 16'hd1e2;
    defparam add_9241_7.INJECT1_0 = "NO";
    defparam add_9241_7.INJECT1_1 = "NO";
    CCU2D add_9241_5 (.A0(n15832[5]), .B0(n486), .C0(n15929[4]), .D0(n25[5]), 
          .A1(n15832[6]), .B1(n486), .C1(n15929[5]), .D1(n25[6]), .CIN(n107310), 
          .COUT(n107311), .S0(n15857[5]), .S1(n15857[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_5.INIT0 = 16'hd1e2;
    defparam add_9241_5.INIT1 = 16'hd1e2;
    defparam add_9241_5.INJECT1_0 = "NO";
    defparam add_9241_5.INJECT1_1 = "NO";
    CCU2D add_9241_3 (.A0(\lux_31__N_754[0] ), .B0(n486), .C0(n111232), 
          .D0(n25[3]), .A1(n111240), .B1(n486), .C1(n77_adj_2719[3]), 
          .D1(n25[4]), .CIN(n107309), .COUT(n107310), .S0(n15857[3]), 
          .S1(n15857[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_3.INIT0 = 16'hd1e2;
    defparam add_9241_3.INIT1 = 16'hd1e2;
    defparam add_9241_3.INJECT1_0 = "NO";
    defparam add_9241_3.INJECT1_1 = "NO";
    CCU2D add_9241_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n2356), .B1(n21676), .C1(GND_net), .D1(GND_net), .COUT(n107309));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9241_1.INIT0 = 16'hF000;
    defparam add_9241_1.INIT1 = 16'hffff;
    defparam add_9241_1.INJECT1_0 = "NO";
    defparam add_9241_1.INJECT1_1 = "NO";
    LUT4 mux_19_i3_3_lut (.A(\lux_31__N_511[3] ), .B(\lux_31__N_543[3] ), 
         .C(lux_31__N_575), .Z(\lux[3] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i3_3_lut.init = 16'hcaca;
    CCU2D add_9240_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107305), 
          .S0(n15856));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_cout.INIT0 = 16'h0000;
    defparam add_9240_cout.INIT1 = 16'h0000;
    defparam add_9240_cout.INJECT1_0 = "NO";
    defparam add_9240_cout.INJECT1_1 = "NO";
    CCU2D add_9240_18 (.A0(n15808[21]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n15831), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107304), 
          .COUT(n107305), .S0(n15832[21]), .S1(n15832[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_18.INIT0 = 16'hfaaa;
    defparam add_9240_18.INIT1 = 16'hfaaa;
    defparam add_9240_18.INJECT1_0 = "NO";
    defparam add_9240_18.INJECT1_1 = "NO";
    CCU2D add_9240_16 (.A0(n15786[19]), .B0(n15808[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n15807), .B1(n15808[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107303), .COUT(n107304), .S0(n15832[19]), 
          .S1(n15832[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_16.INIT0 = 16'h5666;
    defparam add_9240_16.INIT1 = 16'h5666;
    defparam add_9240_16.INJECT1_0 = "NO";
    defparam add_9240_16.INJECT1_1 = "NO";
    CCU2D add_9218_10 (.A0(\ch0_dat[10] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107081), .COUT(n107082), .S0(n15537[13]), 
          .S1(n15537[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_10.INIT0 = 16'h5666;
    defparam add_9218_10.INIT1 = 16'h5666;
    defparam add_9218_10.INJECT1_0 = "NO";
    defparam add_9218_10.INJECT1_1 = "NO";
    CCU2D add_1960_5 (.A0(n24_adj_2720[3]), .B0(n25[2]), .C0(\lux_31__N_625[2] ), 
          .D0(n486), .A1(n15857[3]), .B1(n24_adj_2720[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n106950), .COUT(n106951), .S0(n764[3]), 
          .S1(n764[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_5.INIT0 = 16'ha599;
    defparam add_1960_5.INIT1 = 16'h5999;
    defparam add_1960_5.INJECT1_0 = "NO";
    defparam add_1960_5.INJECT1_1 = "NO";
    CCU2D add_1960_3 (.A0(\lux_31__N_754[0] ), .B0(n486), .C0(n16171), 
          .D0(GND_net), .A1(n16181), .B1(n111240), .C1(\lux_31__N_754[0] ), 
          .D1(n486), .CIN(n106949), .COUT(n106950), .S0(n764[1]), .S1(n764[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_3.INIT0 = 16'hdd2d;
    defparam add_1960_3.INIT1 = 16'ha599;
    defparam add_1960_3.INJECT1_0 = "NO";
    defparam add_1960_3.INJECT1_1 = "NO";
    CCU2D add_9218_8 (.A0(\ch0_dat[8] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107080), .COUT(n107081), .S0(n15537[11]), 
          .S1(n15537[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_8.INIT0 = 16'h5666;
    defparam add_9218_8.INIT1 = 16'h5666;
    defparam add_9218_8.INJECT1_0 = "NO";
    defparam add_9218_8.INJECT1_1 = "NO";
    CCU2D add_1960_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(\lux_31__N_657[0] ), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n106949));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam add_1960_1.INIT0 = 16'hF000;
    defparam add_1960_1.INIT1 = 16'h0aaa;
    defparam add_1960_1.INJECT1_0 = "NO";
    defparam add_1960_1.INJECT1_1 = "NO";
    LUT4 mux_27_i3_4_lut (.A(n764[3]), .B(lux_31__N_721[3]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[3] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i3_4_lut.init = 16'hcac0;
    CCU2D add_9240_14 (.A0(n15786[17]), .B0(n15808[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n15786[18]), .B1(n15808[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107302), .COUT(n107303), .S0(n15832[17]), 
          .S1(n15832[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_14.INIT0 = 16'h5666;
    defparam add_9240_14.INIT1 = 16'h5666;
    defparam add_9240_14.INJECT1_0 = "NO";
    defparam add_9240_14.INJECT1_1 = "NO";
    CCU2D add_9218_6 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107079), .COUT(n107080), .S0(n15537[9]), 
          .S1(n15537[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_6.INIT0 = 16'h5666;
    defparam add_9218_6.INIT1 = 16'h5666;
    defparam add_9218_6.INJECT1_0 = "NO";
    defparam add_9218_6.INJECT1_1 = "NO";
    CCU2D add_9208_20 (.A0(n56[24]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n56[25]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106944), 
          .S0(\lux_31__N_576[24] ), .S1(\lux_31__N_576[25] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_20.INIT0 = 16'h5aaa;
    defparam add_9208_20.INIT1 = 16'h5aaa;
    defparam add_9208_20.INJECT1_0 = "NO";
    defparam add_9208_20.INJECT1_1 = "NO";
    CCU2D add_9218_4 (.A0(\ch0_dat[4] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107078), .COUT(n107079), .S0(n15537[7]), 
          .S1(n15537[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_4.INIT0 = 16'h5666;
    defparam add_9218_4.INIT1 = 16'h5666;
    defparam add_9218_4.INJECT1_0 = "NO";
    defparam add_9218_4.INJECT1_1 = "NO";
    CCU2D add_9208_18 (.A0(n56[22]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n56[23]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106943), 
          .COUT(n106944), .S0(\lux_31__N_576[22] ), .S1(\lux_31__N_576[23] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_18.INIT0 = 16'h5aaa;
    defparam add_9208_18.INIT1 = 16'h5aaa;
    defparam add_9208_18.INJECT1_0 = "NO";
    defparam add_9208_18.INJECT1_1 = "NO";
    CCU2D add_9240_12 (.A0(n15786[15]), .B0(n15808[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n15786[16]), .B1(n15808[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107301), .COUT(n107302), .S0(n15832[15]), 
          .S1(n15832[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_12.INIT0 = 16'h5666;
    defparam add_9240_12.INIT1 = 16'h5666;
    defparam add_9240_12.INJECT1_0 = "NO";
    defparam add_9240_12.INJECT1_1 = "NO";
    CCU2D add_9218_2 (.A0(\lux_31__N_625[3] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107078), .S1(n15537[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[18:28])
    defparam add_9218_2.INIT0 = 16'h7000;
    defparam add_9218_2.INIT1 = 16'h5666;
    defparam add_9218_2.INJECT1_0 = "NO";
    defparam add_9218_2.INJECT1_1 = "NO";
    CCU2D add_9208_16 (.A0(n56[20]), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[21]), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106942), .COUT(n106943), .S0(\lux_31__N_576[20] ), 
          .S1(\lux_31__N_576[21] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_16.INIT0 = 16'h5666;
    defparam add_9208_16.INIT1 = 16'h5666;
    defparam add_9208_16.INJECT1_0 = "NO";
    defparam add_9208_16.INJECT1_1 = "NO";
    LUT4 mux_2242_i2_3_lut_4_lut (.A(\ch1_dat[2] ), .B(n77[2]), .C(n2356), 
         .D(n21676), .Z(n16181)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam mux_2242_i2_3_lut_4_lut.init = 16'hccca;
    CCU2D add_9240_10 (.A0(n15786[13]), .B0(n15808[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n15786[14]), .B1(n15808[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107300), .COUT(n107301), .S0(n15832[13]), 
          .S1(n15832[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_10.INIT0 = 16'h5666;
    defparam add_9240_10.INIT1 = 16'h5666;
    defparam add_9240_10.INJECT1_0 = "NO";
    defparam add_9240_10.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_24 (.A0(n1_adj_2419), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107076), .S0(n56_adj_2711[25]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_24.INIT0 = 16'h5aaa;
    defparam add_9143_add_3_24.INIT1 = 16'h0000;
    defparam add_9143_add_3_24.INJECT1_0 = "NO";
    defparam add_9143_add_3_24.INJECT1_1 = "NO";
    CCU2D add_9240_8 (.A0(n15786[11]), .B0(n15808[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n15786[12]), .B1(n15808[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107299), .COUT(n107300), .S0(n15832[11]), 
          .S1(n15832[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_8.INIT0 = 16'h5666;
    defparam add_9240_8.INIT1 = 16'h5666;
    defparam add_9240_8.INJECT1_0 = "NO";
    defparam add_9240_8.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_22 (.A0(n2_adj_2714[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[24]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107075), .COUT(n107076), .S0(n56_adj_2711[23]), 
          .S1(n56_adj_2711[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_22.INIT0 = 16'h5aaa;
    defparam add_9143_add_3_22.INIT1 = 16'h5aaa;
    defparam add_9143_add_3_22.INJECT1_0 = "NO";
    defparam add_9143_add_3_22.INJECT1_1 = "NO";
    CCU2D add_9240_6 (.A0(n15786[9]), .B0(n15808[9]), .C0(GND_net), .D0(GND_net), 
          .A1(n15786[10]), .B1(n15808[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107298), .COUT(n107299), .S0(n15832[9]), .S1(n15832[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_6.INIT0 = 16'h5666;
    defparam add_9240_6.INIT1 = 16'h5666;
    defparam add_9240_6.INJECT1_0 = "NO";
    defparam add_9240_6.INJECT1_1 = "NO";
    CCU2D add_9240_4 (.A0(n15786[7]), .B0(n15808[7]), .C0(GND_net), .D0(GND_net), 
          .A1(n15786[8]), .B1(n15808[8]), .C1(GND_net), .D1(GND_net), 
          .CIN(n107297), .COUT(n107298), .S0(n15832[7]), .S1(n15832[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_4.INIT0 = 16'h5666;
    defparam add_9240_4.INIT1 = 16'h5666;
    defparam add_9240_4.INJECT1_0 = "NO";
    defparam add_9240_4.INJECT1_1 = "NO";
    CCU2D add_9240_2 (.A0(n15786[5]), .B0(\lux_31__N_754[0] ), .C0(GND_net), 
          .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(n15786[6]), .D1(GND_net), .COUT(n107297), .S1(n15832[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9240_2.INIT0 = 16'h7000;
    defparam add_9240_2.INIT1 = 16'h9696;
    defparam add_9240_2.INJECT1_0 = "NO";
    defparam add_9240_2.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_20 (.A0(n2_adj_2714[21]), .B0(n15484[21]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[22]), .B1(n15507), .C1(GND_net), 
          .D1(GND_net), .CIN(n107074), .COUT(n107075), .S0(n56_adj_2711[21]), 
          .S1(n56_adj_2711[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_20.INIT0 = 16'h5666;
    defparam add_9143_add_3_20.INIT1 = 16'h5666;
    defparam add_9143_add_3_20.INJECT1_0 = "NO";
    defparam add_9143_add_3_20.INJECT1_1 = "NO";
    LUT4 mux_2242_i1_3_lut_4_lut (.A(\lux_31__N_657[1] ), .B(\lux_31__N_657[0] ), 
         .C(n2356), .D(n21676), .Z(n16171)) /* synthesis lut_function=(!(A (B (C+(D)))+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(68[3:11])
    defparam mux_2242_i1_3_lut_4_lut.init = 16'h666a;
    CCU2D add_9239_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107295), 
          .S0(n15831));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_cout.INIT0 = 16'h0000;
    defparam add_9239_cout.INIT1 = 16'h0000;
    defparam add_9239_cout.INJECT1_0 = "NO";
    defparam add_9239_cout.INJECT1_1 = "NO";
    CCU2D add_9239_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107294), .COUT(n107295), .S0(n15808[20]), 
          .S1(n15808[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_16.INIT0 = 16'h5666;
    defparam add_9239_16.INIT1 = 16'hfaaa;
    defparam add_9239_16.INJECT1_0 = "NO";
    defparam add_9239_16.INJECT1_1 = "NO";
    CCU2D add_9239_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107293), .COUT(n107294), .S0(n15808[18]), 
          .S1(n15808[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_14.INIT0 = 16'h5666;
    defparam add_9239_14.INIT1 = 16'h5666;
    defparam add_9239_14.INJECT1_0 = "NO";
    defparam add_9239_14.INJECT1_1 = "NO";
    CCU2D add_9239_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107292), .COUT(n107293), .S0(n15808[16]), 
          .S1(n15808[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_12.INIT0 = 16'h5666;
    defparam add_9239_12.INIT1 = 16'h5666;
    defparam add_9239_12.INJECT1_0 = "NO";
    defparam add_9239_12.INJECT1_1 = "NO";
    CCU2D add_9239_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107291), .COUT(n107292), .S0(n15808[14]), 
          .S1(n15808[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_10.INIT0 = 16'h5666;
    defparam add_9239_10.INIT1 = 16'h5666;
    defparam add_9239_10.INJECT1_0 = "NO";
    defparam add_9239_10.INJECT1_1 = "NO";
    CCU2D add_9239_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107290), .COUT(n107291), .S0(n15808[12]), 
          .S1(n15808[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_8.INIT0 = 16'h5666;
    defparam add_9239_8.INIT1 = 16'h5666;
    defparam add_9239_8.INJECT1_0 = "NO";
    defparam add_9239_8.INJECT1_1 = "NO";
    LUT4 mux_19_i2_3_lut (.A(\lux_31__N_511[2] ), .B(\lux_31__N_543[2] ), 
         .C(lux_31__N_575), .Z(\lux[2] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i2_3_lut.init = 16'hcaca;
    LUT4 mux_27_i2_4_lut (.A(n764[2]), .B(lux_31__N_721[2]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[2] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i2_4_lut.init = 16'hcac0;
    LUT4 mux_19_i1_4_lut (.A(n82919), .B(lux_31__N_543[1]), .C(lux_31__N_575), 
         .D(n109173), .Z(lux[1])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i1_4_lut.init = 16'hcac0;
    LUT4 i1_2_lut_adj_206 (.A(n764[1]), .B(lux_31__N_753), .Z(n109173)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_adj_206.init = 16'h2222;
    CCU2D add_9239_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107289), .COUT(n107290), .S0(n15808[10]), 
          .S1(n15808[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_6.INIT0 = 16'h5666;
    defparam add_9239_6.INIT1 = 16'h5666;
    defparam add_9239_6.INJECT1_0 = "NO";
    defparam add_9239_6.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_18 (.A0(n2_adj_2714[19]), .B0(n15484[19]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[20]), .B1(n15484[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107073), .COUT(n107074), .S0(n56_adj_2711[19]), 
          .S1(n56_adj_2711[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_18.INIT0 = 16'h5666;
    defparam add_9143_add_3_18.INIT1 = 16'h5666;
    defparam add_9143_add_3_18.INJECT1_0 = "NO";
    defparam add_9143_add_3_18.INJECT1_1 = "NO";
    LUT4 mux_19_i20_3_lut (.A(\lux_31__N_511[20] ), .B(\lux_31__N_543[20] ), 
         .C(lux_31__N_575), .Z(\lux[20] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i20_3_lut.init = 16'hcaca;
    LUT4 mux_27_i20_4_lut (.A(n764[20]), .B(lux_31__N_721[20]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[20] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i20_4_lut.init = 16'hcac0;
    LUT4 mux_19_i21_3_lut (.A(\lux_31__N_511[21] ), .B(\lux_31__N_543[21] ), 
         .C(lux_31__N_575), .Z(\lux[21] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i21_3_lut.init = 16'hcaca;
    CCU2D add_9239_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107288), .COUT(n107289), .S0(n15808[8]), 
          .S1(n15808[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_4.INIT0 = 16'h5666;
    defparam add_9239_4.INIT1 = 16'h5666;
    defparam add_9239_4.INJECT1_0 = "NO";
    defparam add_9239_4.INJECT1_1 = "NO";
    CCU2D add_9239_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107288), .S1(n15808[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9239_2.INIT0 = 16'h7000;
    defparam add_9239_2.INIT1 = 16'h5666;
    defparam add_9239_2.INJECT1_0 = "NO";
    defparam add_9239_2.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_16 (.A0(n2_adj_2714[17]), .B0(n15484[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[18]), .B1(n15484[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107072), .COUT(n107073), .S0(n56_adj_2711[17]), 
          .S1(n56_adj_2711[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_16.INIT0 = 16'h5666;
    defparam add_9143_add_3_16.INIT1 = 16'h5666;
    defparam add_9143_add_3_16.INJECT1_0 = "NO";
    defparam add_9143_add_3_16.INJECT1_1 = "NO";
    LUT4 mux_27_i21_4_lut (.A(n764[21]), .B(lux_31__N_721[21]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[21] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i21_4_lut.init = 16'hcac0;
    LUT4 mux_19_i22_3_lut (.A(\lux_31__N_511[22] ), .B(\lux_31__N_543[22] ), 
         .C(lux_31__N_575), .Z(\lux[22] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i22_3_lut.init = 16'hcaca;
    LUT4 mux_27_i22_4_lut (.A(n764[22]), .B(lux_31__N_721[22]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[22] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i22_4_lut.init = 16'hcac0;
    LUT4 mux_19_i23_3_lut (.A(\lux_31__N_511[23] ), .B(\lux_31__N_543[23] ), 
         .C(lux_31__N_575), .Z(\lux[23] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i23_3_lut.init = 16'hcaca;
    CCU2D add_9238_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107286), 
          .S0(n15807));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_cout.INIT0 = 16'h0000;
    defparam add_9238_cout.INIT1 = 16'h0000;
    defparam add_9238_cout.INJECT1_0 = "NO";
    defparam add_9238_cout.INJECT1_1 = "NO";
    CCU2D add_9238_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107285), .COUT(n107286), .S0(n15786[18]), 
          .S1(n15786[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_16.INIT0 = 16'h5666;
    defparam add_9238_16.INIT1 = 16'hfaaa;
    defparam add_9238_16.INJECT1_0 = "NO";
    defparam add_9238_16.INJECT1_1 = "NO";
    LUT4 mux_27_i23_4_lut (.A(n764[23]), .B(lux_31__N_721[23]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[23] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i23_4_lut.init = 16'hcac0;
    LUT4 mux_19_i24_3_lut (.A(\lux_31__N_511[24] ), .B(\lux_31__N_543[24] ), 
         .C(lux_31__N_575), .Z(\lux[24] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i24_3_lut.init = 16'hcaca;
    CCU2D add_9238_14 (.A0(\ch0_dat[13] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[14] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107284), .COUT(n107285), .S0(n15786[16]), 
          .S1(n15786[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_14.INIT0 = 16'h5666;
    defparam add_9238_14.INIT1 = 16'h5666;
    defparam add_9238_14.INJECT1_0 = "NO";
    defparam add_9238_14.INJECT1_1 = "NO";
    CCU2D add_9238_12 (.A0(\ch0_dat[11] ), .B0(\ch0_dat[10] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[12] ), .B1(\ch0_dat[11] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107283), .COUT(n107284), .S0(n15786[14]), 
          .S1(n15786[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_12.INIT0 = 16'h5666;
    defparam add_9238_12.INIT1 = 16'h5666;
    defparam add_9238_12.INJECT1_0 = "NO";
    defparam add_9238_12.INJECT1_1 = "NO";
    CCU2D add_9238_10 (.A0(\ch0_dat[9] ), .B0(\ch0_dat[8] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[10] ), .B1(\ch0_dat[9] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107282), .COUT(n107283), .S0(n15786[12]), 
          .S1(n15786[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_10.INIT0 = 16'h5666;
    defparam add_9238_10.INIT1 = 16'h5666;
    defparam add_9238_10.INJECT1_0 = "NO";
    defparam add_9238_10.INJECT1_1 = "NO";
    CCU2D add_9238_8 (.A0(\ch0_dat[7] ), .B0(\ch0_dat[6] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(\ch0_dat[7] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107281), .COUT(n107282), .S0(n15786[10]), 
          .S1(n15786[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_8.INIT0 = 16'h5666;
    defparam add_9238_8.INIT1 = 16'h5666;
    defparam add_9238_8.INJECT1_0 = "NO";
    defparam add_9238_8.INJECT1_1 = "NO";
    CCU2D add_9238_6 (.A0(\ch0_dat[5] ), .B0(\ch0_dat[4] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(\ch0_dat[5] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107280), .COUT(n107281), .S0(n15786[8]), 
          .S1(n15786[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_6.INIT0 = 16'h5666;
    defparam add_9238_6.INIT1 = 16'h5666;
    defparam add_9238_6.INJECT1_0 = "NO";
    defparam add_9238_6.INJECT1_1 = "NO";
    CCU2D add_9238_4 (.A0(\ch0_dat[3] ), .B0(\lux_31__N_625[3] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(\ch0_dat[3] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107279), .COUT(n107280), .S0(n15786[6]), 
          .S1(n15786[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_4.INIT0 = 16'h5666;
    defparam add_9238_4.INIT1 = 16'h5666;
    defparam add_9238_4.INJECT1_0 = "NO";
    defparam add_9238_4.INJECT1_1 = "NO";
    LUT4 mux_27_i24_4_lut (.A(n764[24]), .B(lux_31__N_721[24]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[24] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i24_4_lut.init = 16'hcac0;
    CCU2D add_9238_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[3] ), .B1(\lux_31__N_625[2] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107279), .S1(n15786[5]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9238_2.INIT0 = 16'h7000;
    defparam add_9238_2.INIT1 = 16'h5666;
    defparam add_9238_2.INJECT1_0 = "NO";
    defparam add_9238_2.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n107277), .S0(n1_adj_2635));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_cout.INIT0 = 16'h0000;
    defparam add_9118_add_1_cout.INIT1 = 16'h0000;
    defparam add_9118_add_1_cout.INJECT1_0 = "NO";
    defparam add_9118_add_1_cout.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_16 (.A0(\ch0_dat[14] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107276), .COUT(n107277), .S0(n2_adj_2721[22]), 
          .S1(n2_adj_2721[23]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_16.INIT0 = 16'h5aaa;
    defparam add_9118_add_1_16.INIT1 = 16'h5aaa;
    defparam add_9118_add_1_16.INJECT1_0 = "NO";
    defparam add_9118_add_1_16.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_14 (.A0(\ch0_dat[12] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[13] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107275), .COUT(n107276), .S0(n2_adj_2721[20]), 
          .S1(n2_adj_2721[21]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_14.INIT0 = 16'h5aaa;
    defparam add_9118_add_1_14.INIT1 = 16'h5aaa;
    defparam add_9118_add_1_14.INJECT1_0 = "NO";
    defparam add_9118_add_1_14.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_12 (.A0(\ch0_dat[10] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[11] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107274), .COUT(n107275), .S0(n2_adj_2721[18]), 
          .S1(n2_adj_2721[19]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_12.INIT0 = 16'h5aaa;
    defparam add_9118_add_1_12.INIT1 = 16'h5aaa;
    defparam add_9118_add_1_12.INJECT1_0 = "NO";
    defparam add_9118_add_1_12.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_10 (.A0(\ch0_dat[8] ), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[9] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107273), .COUT(n107274), .S0(n2_adj_2721[16]), 
          .S1(n2_adj_2721[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_10.INIT0 = 16'h5aaa;
    defparam add_9118_add_1_10.INIT1 = 16'h5aaa;
    defparam add_9118_add_1_10.INJECT1_0 = "NO";
    defparam add_9118_add_1_10.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_8 (.A0(\ch0_dat[6] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[7] ), .B1(\ch0_dat[15] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107272), .COUT(n107273), .S0(n2_adj_2721[14]), 
          .S1(n2_adj_2721[15]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_8.INIT0 = 16'h5666;
    defparam add_9118_add_1_8.INIT1 = 16'h5666;
    defparam add_9118_add_1_8.INJECT1_0 = "NO";
    defparam add_9118_add_1_8.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_6 (.A0(\ch0_dat[4] ), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[5] ), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n107271), .COUT(n107272), .S0(n2_adj_2721[12]), 
          .S1(n2_adj_2721[13]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_6.INIT0 = 16'h5666;
    defparam add_9118_add_1_6.INIT1 = 16'h5666;
    defparam add_9118_add_1_6.INJECT1_0 = "NO";
    defparam add_9118_add_1_6.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_14 (.A0(n2_adj_2714[15]), .B0(n15484[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[16]), .B1(n15484[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107071), .COUT(n107072), .S0(n56_adj_2711[15]), 
          .S1(n56_adj_2711[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_14.INIT0 = 16'h5666;
    defparam add_9143_add_3_14.INIT1 = 16'h5666;
    defparam add_9143_add_3_14.INJECT1_0 = "NO";
    defparam add_9143_add_3_14.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_4 (.A0(\lux_31__N_625[3] ), .B0(\ch0_dat[10] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\ch0_dat[11] ), 
          .C1(GND_net), .D1(GND_net), .CIN(n107270), .COUT(n107271), 
          .S0(n2_adj_2721[10]), .S1(n2_adj_2721[11]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_4.INIT0 = 16'h5666;
    defparam add_9118_add_1_4.INIT1 = 16'h5666;
    defparam add_9118_add_1_4.INJECT1_0 = "NO";
    defparam add_9118_add_1_4.INJECT1_1 = "NO";
    CCU2D add_9118_add_1_2 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[8] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\ch0_dat[9] ), 
          .C1(GND_net), .D1(GND_net), .COUT(n107270), .S1(n2_adj_2721[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9118_add_1_2.INIT0 = 16'h7000;
    defparam add_9118_add_1_2.INIT1 = 16'h5666;
    defparam add_9118_add_1_2.INJECT1_0 = "NO";
    defparam add_9118_add_1_2.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_12 (.A0(n2_adj_2714[13]), .B0(n15484[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[14]), .B1(n15484[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107070), .COUT(n107071), .S0(n56_adj_2711[13]), 
          .S1(n56_adj_2711[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_12.INIT0 = 16'h5666;
    defparam add_9143_add_3_12.INIT1 = 16'h5666;
    defparam add_9143_add_3_12.INJECT1_0 = "NO";
    defparam add_9143_add_3_12.INJECT1_1 = "NO";
    CCU2D add_9349_24 (.A0(n2_adj_2721[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n1_adj_2635), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107267), .S0(n25[23]), .S1(n25[24]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_24.INIT0 = 16'h5aaa;
    defparam add_9349_24.INIT1 = 16'h5aaa;
    defparam add_9349_24.INJECT1_0 = "NO";
    defparam add_9349_24.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_10 (.A0(n2_adj_2714[11]), .B0(n15484[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2714[12]), .B1(n15484[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107069), .COUT(n107070), .S0(n56_adj_2711[11]), 
          .S1(n56_adj_2711[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_10.INIT0 = 16'h5666;
    defparam add_9143_add_3_10.INIT1 = 16'h5666;
    defparam add_9143_add_3_10.INJECT1_0 = "NO";
    defparam add_9143_add_3_10.INJECT1_1 = "NO";
    CCU2D add_9349_22 (.A0(n2_adj_2721[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107266), .COUT(n107267), .S0(n25[21]), 
          .S1(n25[22]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_22.INIT0 = 16'h5aaa;
    defparam add_9349_22.INIT1 = 16'h5aaa;
    defparam add_9349_22.INJECT1_0 = "NO";
    defparam add_9349_22.INJECT1_1 = "NO";
    CCU2D add_9349_20 (.A0(n2_adj_2721[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107265), .COUT(n107266), .S0(n25[19]), 
          .S1(n25[20]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_20.INIT0 = 16'h5aaa;
    defparam add_9349_20.INIT1 = 16'h5aaa;
    defparam add_9349_20.INJECT1_0 = "NO";
    defparam add_9349_20.INJECT1_1 = "NO";
    CCU2D add_9349_18 (.A0(n2_adj_2721[17]), .B0(n15766[17]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[18]), .B1(n15785), .C1(GND_net), 
          .D1(GND_net), .CIN(n107264), .COUT(n107265), .S0(n25[17]), 
          .S1(n25[18]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_18.INIT0 = 16'h5666;
    defparam add_9349_18.INIT1 = 16'h5666;
    defparam add_9349_18.INJECT1_0 = "NO";
    defparam add_9349_18.INJECT1_1 = "NO";
    CCU2D add_9349_16 (.A0(n2_adj_2721[15]), .B0(n15766[15]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[16]), .B1(n15766[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107263), .COUT(n107264), .S0(n25[15]), 
          .S1(n25[16]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_16.INIT0 = 16'h5666;
    defparam add_9349_16.INIT1 = 16'h5666;
    defparam add_9349_16.INJECT1_0 = "NO";
    defparam add_9349_16.INJECT1_1 = "NO";
    CCU2D add_9349_14 (.A0(n2_adj_2721[13]), .B0(n15766[13]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[14]), .B1(n15766[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107262), .COUT(n107263), .S0(n25[13]), 
          .S1(n25[14]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_14.INIT0 = 16'h5666;
    defparam add_9349_14.INIT1 = 16'h5666;
    defparam add_9349_14.INJECT1_0 = "NO";
    defparam add_9349_14.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_8 (.A0(\lux_31__N_754[0] ), .B0(\ch0_dat[9] ), 
          .C0(n15484[9]), .D0(GND_net), .A1(n2_adj_2714[10]), .B1(n15484[10]), 
          .C1(GND_net), .D1(GND_net), .CIN(n107068), .COUT(n107069), 
          .S0(n56_adj_2711[9]), .S1(n56_adj_2711[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_8.INIT0 = 16'h9696;
    defparam add_9143_add_3_8.INIT1 = 16'h5666;
    defparam add_9143_add_3_8.INJECT1_0 = "NO";
    defparam add_9143_add_3_8.INJECT1_1 = "NO";
    CCU2D add_9349_12 (.A0(n2_adj_2721[11]), .B0(n15766[11]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[12]), .B1(n15766[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107261), .COUT(n107262), .S0(n25[11]), 
          .S1(n25[12]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_12.INIT0 = 16'h5666;
    defparam add_9349_12.INIT1 = 16'h5666;
    defparam add_9349_12.INJECT1_0 = "NO";
    defparam add_9349_12.INJECT1_1 = "NO";
    CCU2D add_9349_10 (.A0(n2_adj_2721[9]), .B0(n15766[9]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[10]), .B1(n15766[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107260), .COUT(n107261), .S0(n25[9]), 
          .S1(n25[10]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_10.INIT0 = 16'h5666;
    defparam add_9349_10.INIT1 = 16'h5666;
    defparam add_9349_10.INJECT1_0 = "NO";
    defparam add_9349_10.INJECT1_1 = "NO";
    CCU2D add_9349_8 (.A0(\ch0_dat[7] ), .B0(n15766[7]), .C0(GND_net), 
          .D0(GND_net), .A1(n2_adj_2721[8]), .B1(n15766[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107259), .COUT(n107260), .S0(n25[7]), 
          .S1(n25[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_8.INIT0 = 16'h5666;
    defparam add_9349_8.INIT1 = 16'h5666;
    defparam add_9349_8.INJECT1_0 = "NO";
    defparam add_9349_8.INJECT1_1 = "NO";
    CCU2D add_9349_6 (.A0(\ch0_dat[5] ), .B0(n15766[5]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[6] ), .B1(n15766[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107258), .COUT(n107259), .S0(n25[5]), 
          .S1(n25[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_6.INIT0 = 16'h5666;
    defparam add_9349_6.INIT1 = 16'h5666;
    defparam add_9349_6.INJECT1_0 = "NO";
    defparam add_9349_6.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_6 (.A0(\ch0_dat[7] ), .B0(n15484[7]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[8] ), .B1(n15484[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107067), .COUT(n107068), .S0(lux_31__N_625[8]), 
          .S1(n56_adj_2711[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_6.INIT0 = 16'h5666;
    defparam add_9143_add_3_6.INIT1 = 16'h5666;
    defparam add_9143_add_3_6.INJECT1_0 = "NO";
    defparam add_9143_add_3_6.INJECT1_1 = "NO";
    CCU2D add_9208_14 (.A0(n56[18]), .B0(\ch0_dat[12] ), .C0(GND_net), 
          .D0(GND_net), .A1(n56[19]), .B1(\ch0_dat[13] ), .C1(GND_net), 
          .D1(GND_net), .CIN(n106941), .COUT(n106942), .S0(\lux_31__N_576[18] ), 
          .S1(\lux_31__N_576[19] ));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(59[13:22])
    defparam add_9208_14.INIT0 = 16'h5666;
    defparam add_9208_14.INIT1 = 16'h5666;
    defparam add_9208_14.INJECT1_0 = "NO";
    defparam add_9208_14.INJECT1_1 = "NO";
    LUT4 mux_27_i25_4_lut (.A(n764[25]), .B(lux_31__N_721[25]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[25] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i25_4_lut.init = 16'hcac0;
    CCU2D add_9349_4 (.A0(\ch0_dat[3] ), .B0(n15766[3]), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[4] ), .B1(n15766[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n107257), .COUT(n107258), .S0(n25[3]), 
          .S1(n25[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_4.INIT0 = 16'h5666;
    defparam add_9349_4.INIT1 = 16'h5666;
    defparam add_9349_4.INJECT1_0 = "NO";
    defparam add_9349_4.INJECT1_1 = "NO";
    CCU2D add_9143_add_3_4 (.A0(\ch0_dat[5] ), .B0(\lux_31__N_625[3] ), 
          .C0(GND_net), .D0(GND_net), .A1(\ch0_dat[3] ), .B1(\lux_31__N_754[0] ), 
          .C1(\ch0_dat[6] ), .D1(GND_net), .CIN(n107066), .COUT(n107067), 
          .S0(lux_31__N_625[6]), .S1(lux_31__N_625[7]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(60[9:19])
    defparam add_9143_add_3_4.INIT0 = 16'h5666;
    defparam add_9143_add_3_4.INIT1 = 16'h9696;
    defparam add_9143_add_3_4.INJECT1_0 = "NO";
    defparam add_9143_add_3_4.INJECT1_1 = "NO";
    LUT4 mux_19_i10_3_lut (.A(\lux_31__N_511[10] ), .B(\lux_31__N_543[10] ), 
         .C(lux_31__N_575), .Z(\lux[10] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i10_3_lut.init = 16'hcaca;
    CCU2D add_9349_2 (.A0(\lux_31__N_625[2] ), .B0(\lux_31__N_754[0] ), 
          .C0(GND_net), .D0(GND_net), .A1(\lux_31__N_625[2] ), .B1(\lux_31__N_754[0] ), 
          .C1(\lux_31__N_625[3] ), .D1(GND_net), .COUT(n107257), .S1(n25[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9349_2.INIT0 = 16'h7000;
    defparam add_9349_2.INIT1 = 16'h9696;
    defparam add_9349_2.INJECT1_0 = "NO";
    defparam add_9349_2.INJECT1_1 = "NO";
    CCU2D add_9237_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n107255), 
          .S0(n15785));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_cout.INIT0 = 16'h0000;
    defparam add_9237_cout.INIT1 = 16'h0000;
    defparam add_9237_cout.INJECT1_0 = "NO";
    defparam add_9237_cout.INJECT1_1 = "NO";
    CCU2D add_9237_16 (.A0(\ch0_dat[15] ), .B0(\ch0_dat[14] ), .C0(GND_net), 
          .D0(GND_net), .A1(\ch0_dat[15] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n107254), .COUT(n107255), .S0(n15766[16]), 
          .S1(n15766[17]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(66[9:18])
    defparam add_9237_16.INIT0 = 16'h5666;
    defparam add_9237_16.INIT1 = 16'hfaaa;
    defparam add_9237_16.INJECT1_0 = "NO";
    defparam add_9237_16.INJECT1_1 = "NO";
    LUT4 mux_19_i11_3_lut (.A(\lux_31__N_511[11] ), .B(\lux_31__N_543[11] ), 
         .C(lux_31__N_575), .Z(\lux[11] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i11_3_lut.init = 16'hcaca;
    LUT4 mux_27_i11_4_lut (.A(n764[11]), .B(lux_31__N_721[11]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[11] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i11_4_lut.init = 16'hcac0;
    LUT4 mux_19_i12_3_lut (.A(\lux_31__N_511[12] ), .B(\lux_31__N_543[12] ), 
         .C(lux_31__N_575), .Z(\lux[12] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i12_3_lut.init = 16'hcaca;
    LUT4 mux_27_i12_4_lut (.A(n764[12]), .B(lux_31__N_721[12]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[12] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i12_4_lut.init = 16'hcac0;
    LUT4 mux_19_i13_3_lut (.A(\lux_31__N_511[13] ), .B(\lux_31__N_543[13] ), 
         .C(lux_31__N_575), .Z(\lux[13] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i13_3_lut.init = 16'hcaca;
    LUT4 mux_27_i13_4_lut (.A(n764[13]), .B(lux_31__N_721[13]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[13] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i13_4_lut.init = 16'hcac0;
    LUT4 mux_19_i14_3_lut (.A(\lux_31__N_511[14] ), .B(\lux_31__N_543[14] ), 
         .C(lux_31__N_575), .Z(\lux[14] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i14_3_lut.init = 16'hcaca;
    LUT4 mux_27_i14_4_lut (.A(n764[14]), .B(lux_31__N_721[14]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[14] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i14_4_lut.init = 16'hcac0;
    LUT4 mux_19_i15_3_lut (.A(\lux_31__N_511[15] ), .B(\lux_31__N_543[15] ), 
         .C(lux_31__N_575), .Z(\lux[15] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i15_3_lut.init = 16'hcaca;
    LUT4 mux_27_i15_4_lut (.A(n764[15]), .B(lux_31__N_721[15]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[15] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i15_4_lut.init = 16'hcac0;
    LUT4 mux_19_i16_3_lut (.A(\lux_31__N_511[16] ), .B(\lux_31__N_543[16] ), 
         .C(lux_31__N_575), .Z(\lux[16] )) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(61[7] 68[11])
    defparam mux_19_i16_3_lut.init = 16'hcaca;
    LUT4 mux_27_i16_4_lut (.A(n764[16]), .B(lux_31__N_721[16]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[16] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i16_4_lut.init = 16'hcac0;
    LUT4 mux_27_i26_4_lut (.A(n764[26]), .B(lux_31__N_721[26]), .C(lux_31__N_753), 
         .D(n82919), .Z(\lux_31__N_511[26] )) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(63[7] 68[11])
    defparam mux_27_i26_4_lut.init = 16'hcac0;
    bin_to_bcd u1 (.bcd_code_31__N_965(bcd_code_31__N_965), .n110806(n110806), 
            .n5695(n5695), .n110905(n110905), .n6295(n6295), .bcd_code_31__N_960(bcd_code_31__N_960), 
            .n111044(n111044), .n110966(n110966), .n110278(n110278), .\lux[18] (\lux[18] ), 
            .bcd_code_31__N_1130(bcd_code_31__N_1130), .bcd_code_31__N_1134(bcd_code_31__N_1134), 
            .n111067(n111067), .n5740(n5740), .n6358(n6358), .n6354(n6354), 
            .lux_31__N_575(lux_31__N_575), .\lux_31__N_511[27] (\lux_31__N_511[27] ), 
            .rst_n_c(rst_n_c), .n110534(n110534), .bcd_code_31__N_841(bcd_code_31__N_841), 
            .bcd_code_31__N_855(bcd_code_31__N_855), .bcd_code_31__N_851(bcd_code_31__N_851), 
            .bcd_code_31__N_859(bcd_code_31__N_859), .n6264(n6264), .n5653(n5653), 
            .bcd_code_31__N_797(bcd_code_31__N_797), .n110788(n110788), 
            .n6268(n6268), .n110521(n110521), .n110506(n110506), .n110515(n110515), 
            .n110514(n110514), .n110491(n110491), .n110497(n110497), .n110490(n110490), 
            .n16726(n16726), .bcd_code_31__N_2024(bcd_code_31__N_2024), 
            .n110559(n110559), .n110530(n110530), .n110533(n110533), .n110545(n110545), 
            .n110547(n110547), .n14(n14_adj_114), .n14_adj_55(n14_adj_115), 
            .bcd_code_31__N_1042(bcd_code_31__N_1042), .n110980(n110980), 
            .n110885(n110885), .n14_adj_56(n14_adj_116), .n83313(n83313), 
            .n110532(n110532), .n7(n7), .n110481(n110481), .n14_adj_57(n14_adj_117), 
            .bcd_code_31__N_1180(bcd_code_31__N_1180), .n14_adj_58(n14_adj_118), 
            .bcd_code_31__N_1129(bcd_code_31__N_1129), .n107666(n107666), 
            .bcd_code_31__N_961(bcd_code_31__N_961), .n14_adj_59(n14_adj_119), 
            .n111031(n111031), .n23(n23), .n16565(n16565), .n7_adj_60(n7_adj_120), 
            .n5948(n5948), .bcd_code_31__N_1078(bcd_code_31__N_1078), .n110476(n110476), 
            .n110546(n110546), .n14_adj_61(n14_adj_121), .\lux[19] (\lux[19] ), 
            .bcd_code_31__N_1079(bcd_code_31__N_1079), .bcd_code_31__N_1083(bcd_code_31__N_1083), 
            .n111075(n111075), .n5845(n5845), .n5465(n5465), .bcd_code_31__N_1029(bcd_code_31__N_1029), 
            .n111092(n111092), .\lux_data[15] (\lux_data[15] ), .n110513(n110513), 
            .bcd_code_31__N_895(bcd_code_31__N_895), .n110282(n110282), 
            .n14_adj_62(n14_adj_122), .n110480(n110480), .n110487(n110487), 
            .n16456(n16456), .bcd_code_31__N_900(bcd_code_31__N_900), .n14_adj_63(n14_adj_123), 
            .n14_adj_64(n14_adj_124), .n7_adj_65(n7_adj_125), .bcd_code_31__N_987(bcd_code_31__N_987), 
            .n14_adj_66(n14_adj_126), .bcd_code_31__N_896(bcd_code_31__N_896), 
            .n107670(n107670), .n16625(n16625), .n111113(n111113), .n14_adj_67(n14_adj_127), 
            .bcd_code_31__N_951(bcd_code_31__N_951), .n14_adj_68(n14_adj_128), 
            .n23_adj_69(n23_adj_129), .n7_adj_70(n7_adj_130), .bcd_code_31__N_850(bcd_code_31__N_850), 
            .n111082(n111082), .n110522(n110522), .n110485(n110485), .n110520(n110520), 
            .bcd_code_31__N_913(bcd_code_31__N_913), .n110484(n110484), 
            .n110281(n110281), .bcd_code_31__N_886(bcd_code_31__N_886), 
            .n110285(n110285), .\lux[29] (lux[29]), .n110284(n110284), 
            .n110289(n110289), .n110720(n110720), .n110568(n110568), .n110582(n110582), 
            .n110567(n110567), .n16700(n16700), .bcd_code_31__N_1519(bcd_code_31__N_1519), 
            .\lux[27] (\lux[27] ), .n83413(n83413), .n110486(n110486), 
            .n110478(n110478), .n110930(n110930), .n23_adj_71(n23_adj_131), 
            .n110482(n110482), .n14_adj_72(n14_adj_132), .n4(n4), .n110475(n110475), 
            .n110721(n110721), .bcd_code_31__N_1384(bcd_code_31__N_1384), 
            .n110701(n110701), .\lux_data[11] (\lux_data[11] ), .n107662(n107662), 
            .n14_adj_73(n14_adj_133), .n7_adj_74(n7_adj_134), .n110523(n110523), 
            .n14_adj_75(n14_adj_135), .n110535(n110535), .n14_adj_76(n14_adj_136), 
            .n14_adj_77(n14_adj_137), .n110524(n110524), .\lux[9] (\lux[9] ), 
            .bcd_code_31__N_1769(bcd_code_31__N_1769), .bcd_code_31__N_1773(bcd_code_31__N_1773), 
            .n110965(n110965), .n5621(n5621), .n110536(n110536), .n110507(n110507), 
            .n110508(n110508), .n14_adj_78(n14_adj_138), .\lux[8] (\lux[8] ), 
            .bcd_code_31__N_1845(bcd_code_31__N_1845), .bcd_code_31__N_1849(bcd_code_31__N_1849), 
            .n110952(n110952), .n5502(n5502), .\lux_data[31] (\lux_data[31] ), 
            .bcd_code_31__N_1973(bcd_code_31__N_1973), .\lux[7] (\lux[7] ), 
            .bcd_code_31__N_1914(bcd_code_31__N_1914), .bcd_code_31__N_1918(bcd_code_31__N_1918), 
            .n110936(n110936), .n5022(n5022), .n14_adj_79(n14_adj_139), 
            .\lux[6] (\lux[6] ), .bcd_code_31__N_1974(bcd_code_31__N_1974), 
            .bcd_code_31__N_1978(bcd_code_31__N_1978), .n110921(n110921), 
            .n5660(n5660), .n110269(n110269), .n14_adj_80(n14_adj_140), 
            .\bcd_code_31__N_1380[2] (\bcd_code_31__N_1380[2] ), .\lux[5] (\lux[5] ), 
            .bcd_code_31__N_2025(bcd_code_31__N_2025), .bcd_code_31__N_2029(bcd_code_31__N_2029), 
            .n110902(n110902), .n5260(n5260), .n7_adj_81(n7_adj_141), 
            .\lux[4] (\lux[4] ), .bcd_code_31__N_2067(bcd_code_31__N_2067), 
            .bcd_code_31__N_2071(bcd_code_31__N_2071), .n110884(n110884), 
            .n5292(n5292), .n16584(n16584), .n83307(n83307), .n14_adj_82(n14_adj_142), 
            .\lux[3] (\lux[3] ), .bcd_code_31__N_2100(bcd_code_31__N_2100), 
            .bcd_code_31__N_2104(bcd_code_31__N_2104), .n110868(n110868), 
            .n5181(n5181), .n14_adj_83(n14_adj_143), .n14_adj_84(n14_adj_144), 
            .n14_adj_85(n14_adj_145), .n16558(n16558), .n107664(n107664), 
            .n7_adj_86(n7_adj_146), .n7_adj_87(n7_adj_147), .bcd_code_31__N_795(bcd_code_31__N_795), 
            .n14_adj_88(n14_adj_148), .bcd_code_31__N_1257(bcd_code_31__N_1257), 
            .n7_adj_89(n7_adj_149), .n14_adj_90(n14_adj_150), .n14_adj_91(n14_adj_151), 
            .n110557(n110557), .n110556(n110556), .n110558(n110558), .bcd_code_31__N_1913(bcd_code_31__N_1913), 
            .n110495(n110495), .n110494(n110494), .n7_adj_92(n7_adj_152), 
            .n16471(n16471), .n16601(n16601), .n110592(n110592), .n83295(n83295), 
            .n14_adj_93(n14_adj_153), .n16738(n16738), .n110591(n110591), 
            .bcd_code_31__N_2138(bcd_code_31__N_2138), .n16428(n16428), 
            .n83319(n83319), .\lux_data[7] (\lux_data[7] ), .n110493(n110493), 
            .n922({n922}), .n110578(n110578), .n110496(n110496), .n110581(n110581), 
            .n110817(n110817), .n14_adj_94(n14_adj_154), .n110580(n110580), 
            .n14_adj_95(n14_adj_155), .n107668(n107668), .\lux[2] (\lux[2] ), 
            .bcd_code_31__N_2124(bcd_code_31__N_2124), .bcd_code_31__N_2128(bcd_code_31__N_2128), 
            .n110850(n110850), .n5141(n5141), .\lux[1] (lux[1]), .n14_adj_96(n14_adj_156), 
            .n14_adj_97(n14_adj_157), .n14_adj_98(n14_adj_158), .n14_adj_99(n14_adj_159), 
            .n7_adj_100(n7_adj_160), .\lux[20] (\lux[20] ), .bcd_code_31__N_1030(bcd_code_31__N_1030), 
            .bcd_code_31__N_1034(bcd_code_31__N_1034), .n111081(n111081), 
            .n5916(n5916), .n107675(n107675), .n14_adj_101(n14_adj_161), 
            .n7_adj_102(n7_adj_162), .n14_adj_103(n14_adj_163), .n16300(n16300), 
            .n110504(n110504), .n110503(n110503), .\lux_data[3] (\lux_data[3] ), 
            .n110505(n110505), .n110566(n110566), .\lux[21] (\lux[21] ), 
            .bcd_code_31__N_988(bcd_code_31__N_988), .bcd_code_31__N_992(bcd_code_31__N_992), 
            .n111089(n111089), .n6021(n6021), .\lux_data[23] (\lux_data[23] ), 
            .n110489(n110489), .bcd_code_31__N_1844(bcd_code_31__N_1844), 
            .\lux_data[27] (\lux_data[27] ), .n83415(n83415), .\lux[22] (\lux[22] ), 
            .bcd_code_31__N_952(bcd_code_31__N_952), .bcd_code_31__N_956(bcd_code_31__N_956), 
            .n111098(n111098), .n6059(n6059), .bcd_code_31__N_1768(bcd_code_31__N_1768), 
            .n6291(n6291), .n110272(n110272), .\lux[23] (\lux[23] ), .bcd_code_31__N_914(bcd_code_31__N_914), 
            .bcd_code_31__N_918(bcd_code_31__N_918), .n111102(n111102), 
            .n5329(n5329), .n14_adj_104(n14_adj_164), .n107610(n107610), 
            .n7_adj_105(n7_adj_165), .n14_adj_106(n14_adj_166), .n14_adj_107(n14_adj_167), 
            .n7_adj_108(n7_adj_168), .n14_adj_109(n14_adj_169), .n16550(n16550), 
            .n14_adj_110(n14_adj_170), .bcd_code_31__N_1140(bcd_code_31__N_1140), 
            .bcd_code_31__N_1690(bcd_code_31__N_1690), .\lux[24] (\lux[24] ), 
            .bcd_code_31__N_887(bcd_code_31__N_887), .bcd_code_31__N_891(bcd_code_31__N_891), 
            .n111108(n111108), .n5433(n5433), .n16351(n16351), .bcd_code_31__N_798(bcd_code_31__N_798), 
            .\lux[25] (\lux[25] ), .bcd_code_31__N_860(bcd_code_31__N_860), 
            .bcd_code_31__N_864(bcd_code_31__N_864), .n111110(n111110), 
            .n5548(n5548), .bcd_code_31__N_2099(bcd_code_31__N_2099), .bcd_code_31__N_1588(bcd_code_31__N_1588), 
            .bcd_code_31__N_1394(bcd_code_31__N_1394), .bcd_code_31__N_1450(bcd_code_31__N_1450), 
            .\lux_data[19] (\lux_data[19] ), .bcd_code_31__N_1246(bcd_code_31__N_1246), 
            .n110276(n110276), .bcd_code_31__N_1047(bcd_code_31__N_1047), 
            .bcd_code_31__N_1366(bcd_code_31__N_1366), .bcd_code_31__N_1043(bcd_code_31__N_1043), 
            .bcd_code_31__N_1392(bcd_code_31__N_1392), .n83303(n83303), 
            .\lux[10] (\lux[10] ), .bcd_code_31__N_1691(bcd_code_31__N_1691), 
            .bcd_code_31__N_1695(bcd_code_31__N_1695), .n110987(n110987), 
            .n5701(n5701), .n110944(n110944), .\lux[26] (\lux[26] ), .bcd_code_31__N_842(bcd_code_31__N_842), 
            .bcd_code_31__N_846(bcd_code_31__N_846), .n111115(n111115), 
            .n5804(n5804), .bcd_code_31__N_1306(bcd_code_31__N_1306), .n83327(n83327), 
            .\lux[11] (\lux[11] ), .bcd_code_31__N_1589(bcd_code_31__N_1589), 
            .bcd_code_31__N_1593(bcd_code_31__N_1593), .n110994(n110994), 
            .n5956(n5956), .\lux[12] (\lux[12] ), .bcd_code_31__N_1520(bcd_code_31__N_1520), 
            .bcd_code_31__N_1524(bcd_code_31__N_1524), .n111006(n111006), 
            .n5470(n5470), .\lux[13] (\lux[13] ), .bcd_code_31__N_1451(bcd_code_31__N_1451), 
            .bcd_code_31__N_1455(bcd_code_31__N_1455), .n111016(n111016), 
            .n5988(n5988), .bcd_code_31__N_2066(bcd_code_31__N_2066), .\lux[14] (\lux[14] ), 
            .bcd_code_31__N_1367(bcd_code_31__N_1367), .bcd_code_31__N_1371(bcd_code_31__N_1371), 
            .n111026(n111026), .n5369(n5369), .n16541(n16541), .\lux[15] (\lux[15] ), 
            .bcd_code_31__N_1307(bcd_code_31__N_1307), .bcd_code_31__N_1311(bcd_code_31__N_1311), 
            .n111037(n111037), .n5883(n5883), .n110979(n110979), .n110275(n110275), 
            .\lux[16] (\lux[16] ), .bcd_code_31__N_1247(bcd_code_31__N_1247), 
            .bcd_code_31__N_1251(bcd_code_31__N_1251), .n111050(n111050), 
            .n5225(n5225), .GND_net(GND_net), .\lux[17] (\lux[17] ), .bcd_code_31__N_1181(bcd_code_31__N_1181), 
            .bcd_code_31__N_1185(bcd_code_31__N_1185), .n111059(n111059), 
            .n5401(n5401)) /* synthesis syn_module_defined=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/decoder.v(73[12] 78[2])
    
endmodule
//
// Verilog Description of module bin_to_bcd
//

module bin_to_bcd (bcd_code_31__N_965, n110806, n5695, n110905, n6295, 
            bcd_code_31__N_960, n111044, n110966, n110278, \lux[18] , 
            bcd_code_31__N_1130, bcd_code_31__N_1134, n111067, n5740, 
            n6358, n6354, lux_31__N_575, \lux_31__N_511[27] , rst_n_c, 
            n110534, bcd_code_31__N_841, bcd_code_31__N_855, bcd_code_31__N_851, 
            bcd_code_31__N_859, n6264, n5653, bcd_code_31__N_797, n110788, 
            n6268, n110521, n110506, n110515, n110514, n110491, 
            n110497, n110490, n16726, bcd_code_31__N_2024, n110559, 
            n110530, n110533, n110545, n110547, n14, n14_adj_55, 
            bcd_code_31__N_1042, n110980, n110885, n14_adj_56, n83313, 
            n110532, n7, n110481, n14_adj_57, bcd_code_31__N_1180, 
            n14_adj_58, bcd_code_31__N_1129, n107666, bcd_code_31__N_961, 
            n14_adj_59, n111031, n23, n16565, n7_adj_60, n5948, 
            bcd_code_31__N_1078, n110476, n110546, n14_adj_61, \lux[19] , 
            bcd_code_31__N_1079, bcd_code_31__N_1083, n111075, n5845, 
            n5465, bcd_code_31__N_1029, n111092, \lux_data[15] , n110513, 
            bcd_code_31__N_895, n110282, n14_adj_62, n110480, n110487, 
            n16456, bcd_code_31__N_900, n14_adj_63, n14_adj_64, n7_adj_65, 
            bcd_code_31__N_987, n14_adj_66, bcd_code_31__N_896, n107670, 
            n16625, n111113, n14_adj_67, bcd_code_31__N_951, n14_adj_68, 
            n23_adj_69, n7_adj_70, bcd_code_31__N_850, n111082, n110522, 
            n110485, n110520, bcd_code_31__N_913, n110484, n110281, 
            bcd_code_31__N_886, n110285, \lux[29] , n110284, n110289, 
            n110720, n110568, n110582, n110567, n16700, bcd_code_31__N_1519, 
            \lux[27] , n83413, n110486, n110478, n110930, n23_adj_71, 
            n110482, n14_adj_72, n4, n110475, n110721, bcd_code_31__N_1384, 
            n110701, \lux_data[11] , n107662, n14_adj_73, n7_adj_74, 
            n110523, n14_adj_75, n110535, n14_adj_76, n14_adj_77, 
            n110524, \lux[9] , bcd_code_31__N_1769, bcd_code_31__N_1773, 
            n110965, n5621, n110536, n110507, n110508, n14_adj_78, 
            \lux[8] , bcd_code_31__N_1845, bcd_code_31__N_1849, n110952, 
            n5502, \lux_data[31] , bcd_code_31__N_1973, \lux[7] , bcd_code_31__N_1914, 
            bcd_code_31__N_1918, n110936, n5022, n14_adj_79, \lux[6] , 
            bcd_code_31__N_1974, bcd_code_31__N_1978, n110921, n5660, 
            n110269, n14_adj_80, \bcd_code_31__N_1380[2] , \lux[5] , 
            bcd_code_31__N_2025, bcd_code_31__N_2029, n110902, n5260, 
            n7_adj_81, \lux[4] , bcd_code_31__N_2067, bcd_code_31__N_2071, 
            n110884, n5292, n16584, n83307, n14_adj_82, \lux[3] , 
            bcd_code_31__N_2100, bcd_code_31__N_2104, n110868, n5181, 
            n14_adj_83, n14_adj_84, n14_adj_85, n16558, n107664, n7_adj_86, 
            n7_adj_87, bcd_code_31__N_795, n14_adj_88, bcd_code_31__N_1257, 
            n7_adj_89, n14_adj_90, n14_adj_91, n110557, n110556, n110558, 
            bcd_code_31__N_1913, n110495, n110494, n7_adj_92, n16471, 
            n16601, n110592, n83295, n14_adj_93, n16738, n110591, 
            bcd_code_31__N_2138, n16428, n83319, \lux_data[7] , n110493, 
            n922, n110578, n110496, n110581, n110817, n14_adj_94, 
            n110580, n14_adj_95, n107668, \lux[2] , bcd_code_31__N_2124, 
            bcd_code_31__N_2128, n110850, n5141, \lux[1] , n14_adj_96, 
            n14_adj_97, n14_adj_98, n14_adj_99, n7_adj_100, \lux[20] , 
            bcd_code_31__N_1030, bcd_code_31__N_1034, n111081, n5916, 
            n107675, n14_adj_101, n7_adj_102, n14_adj_103, n16300, 
            n110504, n110503, \lux_data[3] , n110505, n110566, \lux[21] , 
            bcd_code_31__N_988, bcd_code_31__N_992, n111089, n6021, 
            \lux_data[23] , n110489, bcd_code_31__N_1844, \lux_data[27] , 
            n83415, \lux[22] , bcd_code_31__N_952, bcd_code_31__N_956, 
            n111098, n6059, bcd_code_31__N_1768, n6291, n110272, \lux[23] , 
            bcd_code_31__N_914, bcd_code_31__N_918, n111102, n5329, 
            n14_adj_104, n107610, n7_adj_105, n14_adj_106, n14_adj_107, 
            n7_adj_108, n14_adj_109, n16550, n14_adj_110, bcd_code_31__N_1140, 
            bcd_code_31__N_1690, \lux[24] , bcd_code_31__N_887, bcd_code_31__N_891, 
            n111108, n5433, n16351, bcd_code_31__N_798, \lux[25] , 
            bcd_code_31__N_860, bcd_code_31__N_864, n111110, n5548, 
            bcd_code_31__N_2099, bcd_code_31__N_1588, bcd_code_31__N_1394, 
            bcd_code_31__N_1450, \lux_data[19] , bcd_code_31__N_1246, 
            n110276, bcd_code_31__N_1047, bcd_code_31__N_1366, bcd_code_31__N_1043, 
            bcd_code_31__N_1392, n83303, \lux[10] , bcd_code_31__N_1691, 
            bcd_code_31__N_1695, n110987, n5701, n110944, \lux[26] , 
            bcd_code_31__N_842, bcd_code_31__N_846, n111115, n5804, 
            bcd_code_31__N_1306, n83327, \lux[11] , bcd_code_31__N_1589, 
            bcd_code_31__N_1593, n110994, n5956, \lux[12] , bcd_code_31__N_1520, 
            bcd_code_31__N_1524, n111006, n5470, \lux[13] , bcd_code_31__N_1451, 
            bcd_code_31__N_1455, n111016, n5988, bcd_code_31__N_2066, 
            \lux[14] , bcd_code_31__N_1367, bcd_code_31__N_1371, n111026, 
            n5369, n16541, \lux[15] , bcd_code_31__N_1307, bcd_code_31__N_1311, 
            n111037, n5883, n110979, n110275, \lux[16] , bcd_code_31__N_1247, 
            bcd_code_31__N_1251, n111050, n5225, GND_net, \lux[17] , 
            bcd_code_31__N_1181, bcd_code_31__N_1185, n111059, n5401) /* synthesis syn_module_defined=1 */ ;
    input bcd_code_31__N_965;
    input n110806;
    output n5695;
    output n110905;
    output n6295;
    output bcd_code_31__N_960;
    output n111044;
    output n110966;
    output n110278;
    input \lux[18] ;
    input bcd_code_31__N_1130;
    input bcd_code_31__N_1134;
    input n111067;
    output n5740;
    output n6358;
    output n6354;
    input lux_31__N_575;
    input \lux_31__N_511[27] ;
    input rst_n_c;
    output n110534;
    input bcd_code_31__N_841;
    input bcd_code_31__N_855;
    input bcd_code_31__N_851;
    input bcd_code_31__N_859;
    output n6264;
    output n5653;
    output bcd_code_31__N_797;
    output n110788;
    output n6268;
    output n110521;
    output n110506;
    output n110515;
    output n110514;
    output n110491;
    output n110497;
    output n110490;
    output n16726;
    input bcd_code_31__N_2024;
    output n110559;
    output n110530;
    output n110533;
    output n110545;
    output n110547;
    output n14;
    output n14_adj_55;
    output bcd_code_31__N_1042;
    input n110980;
    output n110885;
    output n14_adj_56;
    output n83313;
    output n110532;
    output n7;
    output n110481;
    output n14_adj_57;
    input bcd_code_31__N_1180;
    output n14_adj_58;
    input bcd_code_31__N_1129;
    output n107666;
    input bcd_code_31__N_961;
    output n14_adj_59;
    output n111031;
    output n23;
    output n16565;
    output n7_adj_60;
    output n5948;
    input bcd_code_31__N_1078;
    output n110476;
    output n110546;
    output n14_adj_61;
    input \lux[19] ;
    input bcd_code_31__N_1079;
    input bcd_code_31__N_1083;
    input n111075;
    output n5845;
    output n5465;
    input bcd_code_31__N_1029;
    output n111092;
    output \lux_data[15] ;
    output n110513;
    output bcd_code_31__N_895;
    output n110282;
    output n14_adj_62;
    output n110480;
    output n110487;
    output n16456;
    input bcd_code_31__N_900;
    output n14_adj_63;
    output n14_adj_64;
    output n7_adj_65;
    input bcd_code_31__N_987;
    output n14_adj_66;
    input bcd_code_31__N_896;
    output n107670;
    output n16625;
    output n111113;
    output n14_adj_67;
    input bcd_code_31__N_951;
    output n14_adj_68;
    output n23_adj_69;
    output n7_adj_70;
    output bcd_code_31__N_850;
    output n111082;
    output n110522;
    output n110485;
    output n110520;
    input bcd_code_31__N_913;
    output n110484;
    output n110281;
    input bcd_code_31__N_886;
    output n110285;
    input \lux[29] ;
    output n110284;
    output n110289;
    input n110720;
    output n110568;
    output n110582;
    output n110567;
    output n16700;
    input bcd_code_31__N_1519;
    input \lux[27] ;
    output n83413;
    output n110486;
    output n110478;
    input n110930;
    output n23_adj_71;
    output n110482;
    output n14_adj_72;
    output n4;
    output n110475;
    input n110721;
    output bcd_code_31__N_1384;
    output n110701;
    output \lux_data[11] ;
    output n107662;
    output n14_adj_73;
    output n7_adj_74;
    output n110523;
    output n14_adj_75;
    output n110535;
    output n14_adj_76;
    output n14_adj_77;
    output n110524;
    input \lux[9] ;
    input bcd_code_31__N_1769;
    input bcd_code_31__N_1773;
    input n110965;
    output n5621;
    output n110536;
    output n110507;
    output n110508;
    output n14_adj_78;
    input \lux[8] ;
    input bcd_code_31__N_1845;
    input bcd_code_31__N_1849;
    input n110952;
    output n5502;
    output \lux_data[31] ;
    input bcd_code_31__N_1973;
    input \lux[7] ;
    input bcd_code_31__N_1914;
    input bcd_code_31__N_1918;
    input n110936;
    output n5022;
    output n14_adj_79;
    input \lux[6] ;
    input bcd_code_31__N_1974;
    input bcd_code_31__N_1978;
    input n110921;
    output n5660;
    output n110269;
    output n14_adj_80;
    input \bcd_code_31__N_1380[2] ;
    input \lux[5] ;
    input bcd_code_31__N_2025;
    input bcd_code_31__N_2029;
    input n110902;
    output n5260;
    output n7_adj_81;
    input \lux[4] ;
    input bcd_code_31__N_2067;
    input bcd_code_31__N_2071;
    input n110884;
    output n5292;
    output n16584;
    output n83307;
    output n14_adj_82;
    input \lux[3] ;
    input bcd_code_31__N_2100;
    input bcd_code_31__N_2104;
    input n110868;
    output n5181;
    output n14_adj_83;
    output n14_adj_84;
    output n14_adj_85;
    output n16558;
    output n107664;
    output n7_adj_86;
    output n7_adj_87;
    input bcd_code_31__N_795;
    output n14_adj_88;
    input bcd_code_31__N_1257;
    output n7_adj_89;
    output n14_adj_90;
    output n14_adj_91;
    output n110557;
    output n110556;
    output n110558;
    input bcd_code_31__N_1913;
    output n110495;
    output n110494;
    output n7_adj_92;
    output n16471;
    output n16601;
    output n110592;
    output n83295;
    output n14_adj_93;
    output n16738;
    output n110591;
    output bcd_code_31__N_2138;
    output n16428;
    output n83319;
    output \lux_data[7] ;
    output n110493;
    input [3:0]n922;
    output n110578;
    output n110496;
    output n110581;
    output n110817;
    output n14_adj_94;
    output n110580;
    output n14_adj_95;
    output n107668;
    input \lux[2] ;
    input bcd_code_31__N_2124;
    input bcd_code_31__N_2128;
    input n110850;
    output n5141;
    input \lux[1] ;
    output n14_adj_96;
    output n14_adj_97;
    output n14_adj_98;
    output n14_adj_99;
    output n7_adj_100;
    input \lux[20] ;
    input bcd_code_31__N_1030;
    input bcd_code_31__N_1034;
    input n111081;
    output n5916;
    output n107675;
    output n14_adj_101;
    output n7_adj_102;
    output n14_adj_103;
    output n16300;
    output n110504;
    output n110503;
    output \lux_data[3] ;
    output n110505;
    output n110566;
    input \lux[21] ;
    input bcd_code_31__N_988;
    input bcd_code_31__N_992;
    input n111089;
    output n6021;
    output \lux_data[23] ;
    output n110489;
    input bcd_code_31__N_1844;
    output \lux_data[27] ;
    output n83415;
    input \lux[22] ;
    input bcd_code_31__N_952;
    input bcd_code_31__N_956;
    input n111098;
    output n6059;
    input bcd_code_31__N_1768;
    input n6291;
    output n110272;
    input \lux[23] ;
    input bcd_code_31__N_914;
    input bcd_code_31__N_918;
    input n111102;
    output n5329;
    output n14_adj_104;
    output n107610;
    output n7_adj_105;
    output n14_adj_106;
    output n14_adj_107;
    output n7_adj_108;
    output n14_adj_109;
    output n16550;
    output n14_adj_110;
    input bcd_code_31__N_1140;
    input bcd_code_31__N_1690;
    input \lux[24] ;
    input bcd_code_31__N_887;
    input bcd_code_31__N_891;
    input n111108;
    output n5433;
    output n16351;
    input bcd_code_31__N_798;
    input \lux[25] ;
    input bcd_code_31__N_860;
    input bcd_code_31__N_864;
    input n111110;
    output n5548;
    input bcd_code_31__N_2099;
    input bcd_code_31__N_1588;
    input bcd_code_31__N_1394;
    input bcd_code_31__N_1450;
    output \lux_data[19] ;
    input bcd_code_31__N_1246;
    output n110276;
    input bcd_code_31__N_1047;
    input bcd_code_31__N_1366;
    input bcd_code_31__N_1043;
    input bcd_code_31__N_1392;
    output n83303;
    input \lux[10] ;
    input bcd_code_31__N_1691;
    input bcd_code_31__N_1695;
    input n110987;
    output n5701;
    output n110944;
    input \lux[26] ;
    output bcd_code_31__N_842;
    output bcd_code_31__N_846;
    input n111115;
    output n5804;
    input bcd_code_31__N_1306;
    output n83327;
    input \lux[11] ;
    input bcd_code_31__N_1589;
    input bcd_code_31__N_1593;
    input n110994;
    output n5956;
    input \lux[12] ;
    input bcd_code_31__N_1520;
    input bcd_code_31__N_1524;
    input n111006;
    output n5470;
    input \lux[13] ;
    input bcd_code_31__N_1451;
    input bcd_code_31__N_1455;
    input n111016;
    output n5988;
    input bcd_code_31__N_2066;
    input \lux[14] ;
    input bcd_code_31__N_1367;
    input bcd_code_31__N_1371;
    input n111026;
    output n5369;
    output n16541;
    input \lux[15] ;
    input bcd_code_31__N_1307;
    input bcd_code_31__N_1311;
    input n111037;
    output n5883;
    input n110979;
    output n110275;
    input \lux[16] ;
    input bcd_code_31__N_1247;
    input bcd_code_31__N_1251;
    input n111050;
    output n5225;
    input GND_net;
    input \lux[17] ;
    input bcd_code_31__N_1181;
    input bcd_code_31__N_1185;
    input n111059;
    output n5401;
    
    
    wire n110996;
    wire [3:0]n816;
    
    wire n110989, n110981, n110630;
    wire [3:0]n914;
    wire [3:0]n915;
    
    wire n110600;
    wire [3:0]n924;
    
    wire n110622;
    wire [3:0]n890;
    
    wire n110683;
    wire [3:0]n891;
    wire [3:0]n899;
    
    wire n111276, n111277;
    wire [3:0]n835;
    
    wire n110877;
    wire [3:0]n841;
    
    wire n110861, n110852;
    wire [3:0]n848;
    
    wire n110967, n111273, n111274, n110879, n110872, n110862, n110845;
    wire [3:0]n908;
    
    wire n110633;
    wire [3:0]n917;
    
    wire n110843, n110680;
    wire [3:0]n896;
    wire [3:0]n897;
    wire [3:0]n906;
    
    wire n110995, n110863, n4_c, n4_adj_2321;
    wire [3:0]n818;
    
    wire n110990;
    wire [3:0]n819;
    
    wire n110983, n110970;
    wire [3:0]n840;
    
    wire n110880, n110871, n110854, n110657;
    wire [3:0]n839;
    
    wire n110881;
    wire [3:0]n845;
    
    wire n110865, n110855;
    wire [3:0]n852;
    
    wire n110887, n110886;
    wire [3:0]n836;
    
    wire n6094, n110829, n111286, n111285, n111289, n110572, n110562, 
        n110512, n111295, n111294, n111987, n111988;
    wire [3:0]n926;
    wire [3:0]n889;
    
    wire n110692, n110660;
    wire [3:0]n898;
    
    wire n110667, n110550;
    wire [3:0]n927;
    
    wire n110539, n110712, n110693, n110685, n110671;
    wire [3:0]n893;
    wire [3:0]n834;
    
    wire n110888, n110553;
    wire [3:0]n919;
    wire [3:0]n920;
    
    wire n110501;
    wire [3:0]n876;
    
    wire n110705;
    wire [3:0]n884;
    
    wire n110688, n110678;
    wire [3:0]n929;
    
    wire n110518;
    wire [3:0]n892;
    
    wire n110542, n21200;
    wire [2:0]n878;
    wire [2:0]n903;
    
    wire n21133, n110543, n21201, n110696;
    wire [3:0]n883;
    
    wire n110687, n110664;
    wire [3:0]n847;
    
    wire n110698;
    wire [3:0]n905;
    
    wire n110571, n110641;
    wire [3:0]n907;
    wire [3:0]n916;
    
    wire n83379, n110672;
    wire [3:0]n826;
    
    wire n35, n83384, n110483, n110477, n110479, n111004, n110999, 
        n110986;
    wire [3:0]n811;
    
    wire n111008;
    wire [3:0]n815;
    
    wire n111002, n110998, n110991;
    wire [3:0]n814;
    
    wire n111009, n111001, n111010, n111000, n110992;
    wire [3:0]n823;
    
    wire n111267, n111268, n5365, n111017, n111011, n5469, n110988;
    wire [3:0]n810;
    
    wire n111012, n110531, n111007, n110703, n110702;
    wire [3:0]n877;
    
    wire n5324, n110646, n111020, n111014, n111003, n111021, n111013, 
        n110945;
    wire [3:0]n807;
    
    wire n111028, n111019, n111022, n111018, n110614, n111024;
    wire [3:0]n806;
    
    wire n111027, n110584, n5133;
    wire [3:0]n875;
    
    wire n110704, n110706, n110982, n111033, n111032, n110997, n111034, 
        n111030, n111035, n111029;
    wire [3:0]n804;
    
    wire n111046, n111116, n4_adj_2329, n111040, n111041, n111043;
    wire [3:0]n803;
    
    wire n111045, n110561;
    wire [3:0]n801;
    
    wire n12539, n29;
    wire [3:0]n888;
    
    wire n110708, n111052, n111051, n111053, n111048, n110574, n110538, 
        n111054, n111047, n111056, n111055, n111057, n111071, n5952, 
        n110603, n111063, n83388;
    wire [3:0]n800;
    
    wire n111064, n111062, n110975, n111065, n111061;
    wire [3:0]n793;
    
    wire n111068, n20274, n110984, n111069, n110976;
    wire [3:0]n824;
    
    wire n111070, n32, n29_adj_2337, n109677;
    wire [3:0]n870;
    
    wire n110723, n110676;
    wire [3:0]n797;
    
    wire n111079, n111073, n111077, n111072, n110511;
    wire [3:0]n928;
    
    wire n110632, n110694;
    wire [3:0]n885;
    
    wire n110677, n110662, n111078, n110675, n111084, n111083;
    wire [3:0]n795;
    
    wire n111094, n110652, n111087, n111091, n4_adj_2340, n109681, 
        n4_adj_2341, n111093, n110713, n110686;
    wire [3:0]n910;
    
    wire n110565, n110541, n4_adj_2342, n111096, n111095, n111099, 
        n111100, n110891, n110883, n110866, n5361, n111106, n111105, 
        n35_adj_2343, n111103;
    wire [3:0]n851;
    wire [3:0]n820;
    
    wire n111112, n110875;
    wire [3:0]n894;
    
    wire n110607, n110564;
    wire [3:0]n911;
    
    wire n110500, n110499;
    wire [3:0]n886;
    
    wire n110663, n110856, n110892, n110882, n110867, n111291, n111292, 
        n110715, n110714, n83401, n110555, n110644;
    wire [3:0]n900;
    
    wire n110606;
    wire [3:0]n831;
    
    wire n110907, n110860, n29_adj_2344, n110859;
    wire [3:0]n909;
    
    wire n110719;
    wire [3:0]n881;
    wire [3:0]n882;
    
    wire n20271, n11979, n110904, n4_adj_2346, n12231, n6313, n4_adj_2349, 
        n110570;
    wire [3:0]n925;
    wire [3:0]n869;
    
    wire n110722, n83393, n110733, n110725, n110878;
    wire [2:0]n921;
    
    wire n21062, n110728, n110573;
    wire [3:0]n918;
    
    wire n110526, n110575, n110576;
    wire [2:0]n912;
    
    wire n110577, n110749, n110529, n110731, n110730, n110670, n83386, 
        n110488;
    wire [3:0]n868;
    
    wire n110732;
    wire [3:0]n880;
    
    wire n110739, n110740, n110741, n110743, n110742, n110744, n110735, 
        n110726, n110745;
    wire [3:0]n874;
    
    wire n110734, n110746;
    wire [3:0]n873;
    
    wire n5537, n110755, n110762;
    wire [3:0]n862;
    
    wire n110750, n110751, n110767, n110752, n110595;
    wire [3:0]n923;
    
    wire n110587, n110540, n110753;
    wire [3:0]n901;
    
    wire n110598, n83391, n110579;
    wire [3:0]n861;
    
    wire n110756, n83382, n110502, n110594, n110602, n110605, n110527, 
        n110612;
    wire [3:0]n872;
    
    wire n110761, n110621, n110601, n110763, n110766, n110758, n110768, 
        n110757;
    wire [3:0]n855;
    
    wire n110781, n110765, n110774, n110764, n110792, n110775;
    wire [3:0]n860;
    
    wire n110785;
    wire [3:0]n867;
    
    wire n110770, n110759, n110611;
    wire [3:0]n866;
    
    wire n110777, n110769, n110510, n110779, n21022;
    wire [3:0]n854;
    
    wire n110780;
    wire [3:0]n859;
    
    wire n110784, n110786;
    wire [3:0]n865;
    
    wire n110790, n110789, n110791, n110783, n110793, n110782, n110795, 
        n110794;
    wire [3:0]n849;
    
    wire n110809, n110799;
    wire [3:0]n853;
    
    wire n110800, n110813, n110617, n110895, n110870, n110802, n110804, 
        n110808, n110812, n110627;
    wire [3:0]n902;
    
    wire n110609, n110827, n110620, n110608, n110819, n110818, n110820, 
        n110811, n110821, n110810, n21023, n110823, n110822, n110824, 
        n110815, n110803, n110825;
    wire [3:0]n858;
    
    wire n110814, n110828, n110830, n110831, n110832, n110833, n110834, 
        n110841, n110626, n110628;
    wire [3:0]n846;
    
    wire n110837;
    wire [3:0]n842;
    
    wire n110842, n110836, n110844, n110835, n110639, n110847, n110839, 
        n110848, n110838, n110851, n110846, n110857, n110849, n110873, 
        n110874, n110864, n110645, n110637, n110985, n110900, n110890, 
        n110899, n110889, n110901, n110636;
    wire [3:0]n830;
    
    wire n110906, n110908, n110898, n110909, n110897;
    wire [3:0]n833;
    
    wire n110910, n110971;
    wire [3:0]n828;
    
    wire n110649, n110915, n110914;
    wire [3:0]n829;
    
    wire n110916, n110919, n110912, n110920, n110911, n110922, n110923, 
        n110926, n110918, n110927, n110917, n110928, n110978, n5546, 
        n110937, n110946;
    wire [3:0]n825;
    
    wire n110931, n110925, n110932, n110924, n110661, n110933, n110938, 
        n110969, n110941, n110935, n110942, n110934, n110653, n110647, 
        n110949, n110940, n110950, n110939, n110951, n110960, n110948, 
        n110954, n110947, n110955, n110959, n110963, n110957, n110964, 
        n110956, n110968, n110962, n110961, n111283, n111282, n110977;
    
    LUT4 i2930_3_lut_rep_923_4_lut (.A(bcd_code_31__N_965), .B(n110996), 
         .C(n816[1]), .D(n110989), .Z(n110981)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2930_3_lut_rep_923_4_lut.init = 16'hf666;
    LUT4 i4311_2_lut_rep_542_4_lut_4_lut (.A(n110630), .B(n914[3]), .C(n915[1]), 
         .D(n915[2]), .Z(n110600)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4311_2_lut_rep_542_4_lut_4_lut.init = 16'h332c;
    LUT4 i4333_3_lut_4_lut_3_lut_4_lut (.A(n110630), .B(n914[3]), .C(n915[1]), 
         .D(n915[2]), .Z(n924[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4333_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2905_3_lut_rep_564 (.A(n110630), .B(n914[3]), .C(n915[1]), .D(n915[2]), 
         .Z(n110622)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2905_3_lut_rep_564.init = 16'hffe0;
    LUT4 i4319_3_lut_4_lut (.A(n110630), .B(n914[3]), .C(n915[1]), .D(n915[2]), 
         .Z(n924[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4319_3_lut_4_lut.init = 16'h998a;
    LUT4 i6496_3_lut_4_lut_3_lut_4_lut (.A(n890[3]), .B(n110683), .C(n891[1]), 
         .D(n891[2]), .Z(n899[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i6496_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    PFUMX i102164 (.BLUT(n111276), .ALUT(n111277), .C0(n110806), .Z(n5695));
    LUT4 i2504_2_lut_rep_803_3_lut (.A(n835[3]), .B(n110877), .C(n841[3]), 
         .Z(n110861)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2504_2_lut_rep_803_3_lut.init = 16'hf6f6;
    LUT4 i4865_3_lut_4_lut (.A(n835[3]), .B(n110877), .C(n841[3]), .D(n110852), 
         .Z(n848[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4865_3_lut_4_lut.init = 16'h6966;
    LUT4 i4928_2_lut_rep_909_3_lut_3_lut_4_lut (.A(bcd_code_31__N_965), .B(n110996), 
         .C(n816[1]), .D(n110989), .Z(n110967)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4928_2_lut_rep_909_3_lut_3_lut_4_lut.init = 16'h06f0;
    PFUMX i102162 (.BLUT(n111273), .ALUT(n111274), .C0(n110905), .Z(n6295));
    LUT4 i2931_3_lut_rep_804_4_lut (.A(n835[1]), .B(n110879), .C(n841[1]), 
         .D(n110872), .Z(n110862)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2931_3_lut_rep_804_4_lut.init = 16'hf666;
    LUT4 i4956_2_lut_rep_787_3_lut_3_lut_4_lut (.A(n835[1]), .B(n110879), 
         .C(n841[1]), .D(n110872), .Z(n110845)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4956_2_lut_rep_787_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4472_2_lut_4_lut_4_lut (.A(n908[0]), .B(n110633), .C(n908[1]), 
         .D(n908[2]), .Z(n917[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4472_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i4963_3_lut_rep_785_4_lut_3_lut_4_lut (.A(n835[1]), .B(n110879), 
         .C(n841[1]), .D(n110872), .Z(n110843)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4963_3_lut_rep_785_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4753_3_lut_4_lut (.A(n110680), .B(n896[3]), .C(n897[1]), .D(n897[2]), 
         .Z(n906[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4753_3_lut_4_lut.init = 16'h998a;
    LUT4 bcd_code_31__N_923_bdd_4_lut_4_lut (.A(bcd_code_31__N_960), .B(n110995), 
         .C(n111044), .D(n110966), .Z(n110278)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B (C+!(D))+!B (D)))) */ ;
    defparam bcd_code_31__N_923_bdd_4_lut_4_lut.init = 16'h73c6;
    LUT4 i4494_3_lut_4_lut_3_lut_4_lut (.A(n908[0]), .B(n110633), .C(n908[1]), 
         .D(n908[2]), .Z(n917[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4494_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4487_2_lut_3_lut_3_lut_4_lut (.A(n908[0]), .B(n110633), .C(n908[1]), 
         .D(n908[2]), .Z(n917[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4487_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i13836_2_lut_rep_805_4_lut (.A(n835[1]), .B(n110879), .C(n841[1]), 
         .D(n110872), .Z(n110863)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13836_2_lut_rep_805_4_lut.init = 16'hf600;
    LUT4 i1_3_lut_4_lut (.A(n110995), .B(bcd_code_31__N_960), .C(n4_c), 
         .D(n111044), .Z(n4_adj_2321)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(B (D)+!B !(C (D)+!C !(D))))) */ ;
    defparam i1_3_lut_4_lut.init = 16'h6f90;
    LUT4 i6754_2_lut_rep_912_4_lut_4_lut (.A(n818[3]), .B(n110990), .C(n819[1]), 
         .D(n110983), .Z(n110970)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6754_2_lut_rep_912_4_lut_4_lut.init = 16'h554a;
    LUT4 i4767_3_lut_4_lut_3_lut_4_lut (.A(n110680), .B(n896[3]), .C(n897[1]), 
         .D(n897[2]), .Z(n906[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4767_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2995_4_lut (.A(\lux[18] ), .B(bcd_code_31__N_1130), .C(bcd_code_31__N_1134), 
         .D(n111067), .Z(n5740)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2995_4_lut.init = 16'hfcec;
    LUT4 i4480_3_lut_4_lut (.A(n908[0]), .B(n110633), .C(n908[1]), .D(n908[2]), 
         .Z(n917[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4480_3_lut_4_lut.init = 16'h998a;
    LUT4 i4941_2_lut_rep_796_4_lut_4_lut (.A(n840[3]), .B(n110880), .C(n841[1]), 
         .D(n110871), .Z(n110854)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4941_2_lut_rep_796_4_lut_4_lut.init = 16'h554a;
    LUT4 i4745_2_lut_rep_599_4_lut_4_lut (.A(n110680), .B(n896[3]), .C(n897[1]), 
         .D(n897[2]), .Z(n110657)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4745_2_lut_rep_599_4_lut_4_lut.init = 16'h332c;
    LUT4 i3256_2_lut_rep_807_3_lut (.A(n839[3]), .B(n110881), .C(n845[3]), 
         .Z(n110865)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3256_2_lut_rep_807_3_lut.init = 16'hf6f6;
    LUT4 i6538_3_lut_4_lut (.A(n839[3]), .B(n110881), .C(n845[3]), .D(n110855), 
         .Z(n852[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6538_3_lut_4_lut.init = 16'h6966;
    LUT4 i6894_2_lut_rep_771_4_lut_4_lut (.A(n110887), .B(n110886), .C(n836[1]), 
         .D(n6094), .Z(n110829)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i6894_2_lut_rep_771_4_lut_4_lut.init = 16'h936c;
    LUT4 i3014_4_lut_then_4_lut (.A(n6358), .B(n6354), .C(n111044), .D(n110966), 
         .Z(n111286)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A !((C)+!B)) */ ;
    defparam i3014_4_lut_then_4_lut.init = 16'hac0c;
    LUT4 i3014_4_lut_else_4_lut (.A(n6358), .B(n6354), .C(n111044), .D(n110966), 
         .Z(n111285)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(B (C+(D))+!B (C)))) */ ;
    defparam i3014_4_lut_else_4_lut.init = 16'h5c50;
    LUT4 i11567_3_lut_4_lut_then_4_lut (.A(lux_31__N_575), .B(\lux_31__N_511[27] ), 
         .Z(n111289)) /* synthesis lut_function=(!(A+(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11567_3_lut_4_lut_then_4_lut.init = 16'h1111;
    LUT4 i75767_2_lut_rep_454_3_lut_4_lut (.A(n110572), .B(n110562), .C(rst_n_c), 
         .D(n110534), .Z(n110512)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i75767_2_lut_rep_454_3_lut_4_lut.init = 16'h6000;
    LUT4 i5159_3_lut_4_lut_then_4_lut (.A(bcd_code_31__N_841), .B(bcd_code_31__N_855), 
         .C(bcd_code_31__N_851), .D(bcd_code_31__N_859), .Z(n111295)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A (B (C)+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5159_3_lut_4_lut_then_4_lut.init = 16'h3cb4;
    LUT4 i5159_3_lut_4_lut_else_4_lut (.A(bcd_code_31__N_841), .B(bcd_code_31__N_855), 
         .C(bcd_code_31__N_851), .D(bcd_code_31__N_859), .Z(n111294)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5159_3_lut_4_lut_else_4_lut.init = 16'h3c78;
    LUT4 mux_9087_i3_3_lut_rep_691_4_lut_else_3_lut_4_lut (.A(n6264), .B(n5653), 
         .C(bcd_code_31__N_797), .D(n110788), .Z(n111987)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam mux_9087_i3_3_lut_rep_691_4_lut_else_3_lut_4_lut.init = 16'h8880;
    LUT4 mux_9087_i3_3_lut_rep_691_4_lut_then_3_lut (.A(n6295), .B(n6268), 
         .C(bcd_code_31__N_797), .Z(n111988)) /* synthesis lut_function=(A+!(B+(C))) */ ;
    defparam mux_9087_i3_3_lut_rep_691_4_lut_then_3_lut.init = 16'habab;
    LUT4 i75557_2_lut_rep_463_4_lut (.A(n926[0]), .B(n110562), .C(n110572), 
         .D(rst_n_c), .Z(n110521)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i75557_2_lut_rep_463_4_lut.init = 16'ha600;
    LUT4 i3620_3_lut_rep_602_4_lut_3_lut_4_lut (.A(n889[3]), .B(n110692), 
         .C(n890[1]), .D(n890[2]), .Z(n110660)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i3620_3_lut_rep_602_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i3613_2_lut_3_lut_3_lut_4_lut (.A(n889[3]), .B(n110692), .C(n890[1]), 
         .D(n890[2]), .Z(n898[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i3613_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i3598_2_lut_rep_609_4_lut_4_lut (.A(n889[3]), .B(n110692), .C(n890[1]), 
         .D(n890[2]), .Z(n110667)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i3598_2_lut_rep_609_4_lut_4_lut.init = 16'h554a;
    LUT4 i4032_3_lut_rep_448_4_lut_3_lut_4_lut (.A(n110550), .B(n926[3]), 
         .C(n927[1]), .D(n927[2]), .Z(n110506)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4032_3_lut_rep_448_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4010_2_lut_rep_457_4_lut_4_lut (.A(n110550), .B(n926[3]), .C(n927[1]), 
         .D(n927[2]), .Z(n110515)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4010_2_lut_rep_457_4_lut_4_lut.init = 16'h332c;
    LUT4 i3606_3_lut_4_lut (.A(n889[3]), .B(n110692), .C(n890[1]), .D(n890[2]), 
         .Z(n898[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i3606_3_lut_4_lut.init = 16'h998c;
    LUT4 i2894_3_lut_rep_481 (.A(n110550), .B(n926[3]), .C(n927[1]), .D(n927[2]), 
         .Z(n110539)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2894_3_lut_rep_481.init = 16'hffe0;
    LUT4 i4018_3_lut_rep_456_4_lut (.A(n110550), .B(n926[3]), .C(n927[1]), 
         .D(n927[2]), .Z(n110514)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4018_3_lut_rep_456_4_lut.init = 16'h998a;
    LUT4 i5278_3_lut_4_lut (.A(n110712), .B(n110693), .C(n110685), .D(n110671), 
         .Z(n893[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5278_3_lut_4_lut.init = 16'h6966;
    LUT4 i3048_2_lut_rep_814_3_lut (.A(n834[3]), .B(n110888), .C(n840[3]), 
         .Z(n110872)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3048_2_lut_rep_814_3_lut.init = 16'hf6f6;
    LUT4 i4193_3_lut_rep_443_4_lut_3_lut_4_lut (.A(n110553), .B(n919[3]), 
         .C(n920[1]), .D(n920[2]), .Z(n110501)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4193_3_lut_rep_443_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2956_3_lut_rep_620_4_lut (.A(n876[1]), .B(n110705), .C(n884[1]), 
         .D(n110688), .Z(n110678)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2956_3_lut_rep_620_4_lut.init = 16'hf666;
    LUT4 i4186_2_lut_3_lut_3_lut_4_lut (.A(n110553), .B(n919[3]), .C(n920[1]), 
         .D(n920[2]), .Z(n929[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4186_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4171_2_lut_rep_460_4_lut_4_lut (.A(n110553), .B(n919[3]), .C(n920[1]), 
         .D(n920[2]), .Z(n110518)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4171_2_lut_rep_460_4_lut_4_lut.init = 16'h332c;
    LUT4 i5397_2_lut_3_lut_3_lut_4_lut (.A(n876[1]), .B(n110705), .C(n884[1]), 
         .D(n110688), .Z(n892[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5397_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5404_3_lut_4_lut_3_lut_4_lut (.A(n876[1]), .B(n110705), .C(n884[1]), 
         .D(n110688), .Z(n892[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5404_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2900_3_lut_rep_484 (.A(n110553), .B(n919[3]), .C(n920[1]), .D(n920[2]), 
         .Z(n110542)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2900_3_lut_rep_484.init = 16'hffe0;
    LUT4 i4179_3_lut_4_lut (.A(n110553), .B(n919[3]), .C(n920[1]), .D(n920[2]), 
         .Z(n929[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4179_3_lut_4_lut.init = 16'h998a;
    LUT4 i2917_4_lut_rep_485 (.A(n21200), .B(n878[1]), .C(n903[1]), .D(n21133), 
         .Z(n110543)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i2917_4_lut_rep_485.init = 16'hb3ec;
    LUT4 i13832_2_lut_4_lut (.A(n21200), .B(n878[1]), .C(n903[1]), .D(n21133), 
         .Z(n21201)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))) */ ;
    defparam i13832_2_lut_4_lut.init = 16'ha2a8;
    LUT4 i5382_2_lut_rep_606_4_lut_4_lut (.A(n110696), .B(n883[3]), .C(n884[1]), 
         .D(n110687), .Z(n110664)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5382_2_lut_rep_606_4_lut_4_lut.init = 16'h332c;
    LUT4 i75654_4_lut_4_lut_4_lut (.A(n110491), .B(rst_n_c), .C(n110497), 
         .D(n110490), .Z(n16726)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75654_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i4949_3_lut_4_lut (.A(n834[3]), .B(n110888), .C(n840[3]), .D(n110862), 
         .Z(n847[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4949_3_lut_4_lut.init = 16'h6966;
    LUT4 i4788_2_lut_3_lut_3_lut_4_lut (.A(n110698), .B(bcd_code_31__N_2024), 
         .C(n896[1]), .D(n896[2]), .Z(n905[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4788_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i10506_3_lut_rep_472_4_lut (.A(n924[3]), .B(n110571), .C(rst_n_c), 
         .D(n110559), .Z(n110530)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i10506_3_lut_rep_472_4_lut.init = 16'h9060;
    LUT4 i4795_3_lut_4_lut_3_lut_4_lut (.A(n110698), .B(bcd_code_31__N_2024), 
         .C(n896[1]), .D(n896[2]), .Z(n905[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4795_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4515_2_lut_3_lut_3_lut_4_lut (.A(n110641), .B(n906[3]), .C(n907[1]), 
         .D(n907[2]), .Z(n916[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4515_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i75815_2_lut_3_lut (.A(n924[3]), .B(n110571), .C(n110559), .Z(n83379)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i75815_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i75552_2_lut_rep_475_3_lut (.A(n924[3]), .B(n110571), .C(rst_n_c), 
         .Z(n110533)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i75552_2_lut_rep_475_3_lut.init = 16'h6060;
    LUT4 i4773_2_lut_rep_614_4_lut_4_lut (.A(n110698), .B(bcd_code_31__N_2024), 
         .C(n896[1]), .D(n896[2]), .Z(n110672)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4773_2_lut_rep_614_4_lut_4_lut.init = 16'h332c;
    LUT4 i75396_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), 
         .C(n110545), .D(n110547), .Z(n14)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75396_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 mux_29_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110559), 
         .B(rst_n_c), .C(n110545), .D(n110547), .Z(n14_adj_55)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_29_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i1_4_lut_4_lut (.A(bcd_code_31__N_1042), .B(n826[3]), .C(n110980), 
         .D(n110885), .Z(n35)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C))+!A !(B (C+!(D))))) */ ;
    defparam i1_4_lut_4_lut.init = 16'h60e4;
    LUT4 i75433_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), 
         .C(n110547), .D(n110545), .Z(n14_adj_56)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75433_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hffbf;
    LUT4 i4781_3_lut_4_lut (.A(n110698), .B(bcd_code_31__N_2024), .C(n896[1]), 
         .D(n896[2]), .Z(n905[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4781_3_lut_4_lut.init = 16'h998a;
    LUT4 i75808_4_lut_4_lut (.A(n110490), .B(rst_n_c), .C(n83384), .D(n110483), 
         .Z(n83313)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75808_4_lut_4_lut.init = 16'h37bf;
    LUT4 mux_29_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), 
         .C(n110532), .D(n110545), .Z(n7)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(B (C+(D))+!B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_29_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut.init = 16'h7cf0;
    LUT4 mux_19_Mux_1_i14_3_lut_3_lut_4_lut (.A(n110481), .B(rst_n_c), .C(n110477), 
         .D(n110479), .Z(n14_adj_57)) /* synthesis lut_function=(A (B (C)+!B !(D))+!A !(D)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_19_Mux_1_i14_3_lut_3_lut_4_lut.init = 16'h80f7;
    LUT4 i6838_2_lut_rep_928_4_lut_4_lut (.A(bcd_code_31__N_1180), .B(n111004), 
         .C(n818[1]), .D(n110999), .Z(n110986)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6838_2_lut_rep_928_4_lut_4_lut.init = 16'h554a;
    LUT4 i75642_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), 
         .C(n110545), .D(n110547), .Z(n14_adj_58)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75642_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hf7ff;
    LUT4 i2939_3_lut_rep_940_4_lut (.A(n811[1]), .B(n111008), .C(n815[1]), 
         .D(n111002), .Z(n110998)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2939_3_lut_rep_940_4_lut.init = 16'hf666;
    LUT4 i13817_2_lut_rep_933_3_lut_4_lut (.A(n811[1]), .B(n111008), .C(n815[1]), 
         .D(n111002), .Z(n110991)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13817_2_lut_rep_933_3_lut_4_lut.init = 16'hf600;
    LUT4 i5124_2_lut_rep_925_3_lut_3_lut_4_lut (.A(n811[1]), .B(n111008), 
         .C(n815[1]), .D(n111002), .Z(n110983)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5124_2_lut_rep_925_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5131_3_lut_4_lut_3_lut_4_lut (.A(n811[1]), .B(n111008), .C(n815[1]), 
         .D(n111002), .Z(n819[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5131_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5109_2_lut_rep_932_4_lut_4_lut (.A(n814[3]), .B(n111009), .C(n815[1]), 
         .D(n111001), .Z(n110990)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5109_2_lut_rep_932_4_lut_4_lut.init = 16'h554a;
    LUT4 i3086_2_lut_rep_942_3_lut (.A(bcd_code_31__N_1129), .B(n111010), 
         .C(bcd_code_31__N_1180), .Z(n111000)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3086_2_lut_rep_942_3_lut.init = 16'hf6f6;
    LUT4 i6846_3_lut_4_lut (.A(bcd_code_31__N_1129), .B(n111010), .C(bcd_code_31__N_1180), 
         .D(n110992), .Z(n823[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6846_3_lut_4_lut.init = 16'h6966;
    PFUMX i102158 (.BLUT(n111267), .ALUT(n111268), .C0(n878[1]), .Z(n5365));
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), .C(n110547), 
         .D(n110545), .Z(n107666)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 i2953_3_lut_4_lut (.A(n111017), .B(n111011), .C(bcd_code_31__N_965), 
         .D(bcd_code_31__N_961), .Z(n5469)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i2953_3_lut_4_lut.init = 16'hffe0;
    LUT4 i5369_2_lut_rep_930_3_lut_4_lut (.A(n111017), .B(n111011), .C(bcd_code_31__N_965), 
         .D(n5469), .Z(n110988)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam i5369_2_lut_rep_930_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i3092_2_lut_rep_944_3_lut (.A(n810[3]), .B(n111012), .C(n814[3]), 
         .Z(n111002)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3092_2_lut_rep_944_3_lut.init = 16'hf6f6;
    LUT4 i5117_3_lut_4_lut (.A(n810[3]), .B(n111012), .C(n814[3]), .D(n110998), 
         .Z(n819[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5117_3_lut_4_lut.init = 16'h6966;
    LUT4 i75794_2_lut_rep_473_3_lut_4_lut (.A(n110559), .B(rst_n_c), .C(n110571), 
         .D(n924[3]), .Z(n110531)) /* synthesis lut_function=(!(((C (D)+!C !(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75794_2_lut_rep_473_3_lut_4_lut.init = 16'h0880;
    LUT4 i75640_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), .C(n110545), 
         .D(n110547), .Z(n14_adj_59)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75640_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i13780_2_lut_rep_938_3_lut_4_lut (.A(n111031), .B(n23), .C(n5469), 
         .D(n111017), .Z(n110996)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (B (C (D))+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13780_2_lut_rep_938_3_lut_4_lut.init = 16'hf090;
    LUT4 i3099_2_lut_rep_949_3_lut (.A(n111031), .B(n23), .C(n111017), 
         .Z(n111007)) /* synthesis lut_function=(A (B+(C))+!A ((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3099_2_lut_rep_949_3_lut.init = 16'hf9f9;
    LUT4 i5362_3_lut_4_lut (.A(n111031), .B(n23), .C(n111017), .D(n5469), 
         .Z(n816[1])) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5362_3_lut_4_lut.init = 16'h9699;
    LUT4 i75669_3_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), .C(n110547), 
         .D(n110545), .Z(n16565)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75669_3_lut_4_lut_4_lut_4_lut.init = 16'hffb7;
    LUT4 i75641_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110559), .B(rst_n_c), 
         .C(n110545), .D(n110547), .Z(n7_adj_60)) /* synthesis lut_function=(!(A (B)+!A !((C+!(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75641_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7377;
    LUT4 i4997_2_lut_rep_588_4_lut_4_lut (.A(n110703), .B(n110702), .C(n877[1]), 
         .D(n5324), .Z(n110646)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i4997_2_lut_rep_588_4_lut_4_lut.init = 16'h936c;
    LUT4 i13807_2_lut_rep_945_3_lut_4_lut (.A(n810[1]), .B(n111020), .C(n814[1]), 
         .D(n111014), .Z(n111003)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13807_2_lut_rep_945_3_lut_4_lut.init = 16'hf600;
    LUT4 i5180_2_lut_rep_941_3_lut_3_lut_4_lut (.A(n810[1]), .B(n111020), 
         .C(n814[1]), .D(n111014), .Z(n110999)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5180_2_lut_rep_941_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5187_3_lut_4_lut_3_lut_4_lut (.A(n810[1]), .B(n111020), .C(n814[1]), 
         .D(n111014), .Z(n818[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5187_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2942_3_lut_rep_952_4_lut (.A(n810[1]), .B(n111020), .C(n814[1]), 
         .D(n111014), .Z(n111010)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2942_3_lut_rep_952_4_lut.init = 16'hf666;
    LUT4 i5165_2_lut_rep_946_4_lut_4_lut (.A(bcd_code_31__N_1129), .B(n111021), 
         .C(n814[1]), .D(n111013), .Z(n111004)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5165_2_lut_rep_946_4_lut_4_lut.init = 16'h554a;
    LUT4 i8706_2_lut_rep_887_4_lut_4_lut (.A(n110989), .B(n110988), .C(n816[1]), 
         .D(n5948), .Z(n110945)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i8706_2_lut_rep_887_4_lut_4_lut.init = 16'h936c;
    LUT4 i5656_3_lut_4_lut_3_lut_4_lut (.A(n807[1]), .B(n111028), .C(n811[1]), 
         .D(n111019), .Z(n815[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5656_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2966_3_lut_rep_954_4_lut (.A(n807[1]), .B(n111028), .C(n811[1]), 
         .D(n111019), .Z(n111012)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2966_3_lut_rep_954_4_lut.init = 16'hf666;
    LUT4 i5649_2_lut_rep_943_3_lut_3_lut_4_lut (.A(n807[1]), .B(n111028), 
         .C(n811[1]), .D(n111019), .Z(n111001)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5649_2_lut_rep_943_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13134_2_lut_rep_950_3_lut_4_lut (.A(n807[1]), .B(n111028), .C(n811[1]), 
         .D(n111019), .Z(n111008)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13134_2_lut_rep_950_3_lut_4_lut.init = 16'hf600;
    LUT4 i5634_2_lut_rep_951_4_lut_4_lut (.A(n810[3]), .B(n111022), .C(n811[1]), 
         .D(n111018), .Z(n111009)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5634_2_lut_rep_951_4_lut_4_lut.init = 16'h554a;
    LUT4 i4500_2_lut_rep_556_4_lut_4_lut (.A(n110641), .B(n906[3]), .C(n907[1]), 
         .D(n907[2]), .Z(n110614)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4500_2_lut_rep_556_4_lut_4_lut.init = 16'h332c;
    LUT4 i3095_2_lut_rep_956_3_lut (.A(bcd_code_31__N_1078), .B(n111024), 
         .C(bcd_code_31__N_1129), .Z(n111014)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3095_2_lut_rep_956_3_lut.init = 16'hf6f6;
    LUT4 i5173_3_lut_4_lut (.A(bcd_code_31__N_1078), .B(n111024), .C(bcd_code_31__N_1129), 
         .D(n111010), .Z(n818[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5173_3_lut_4_lut.init = 16'h6966;
    LUT4 i3103_2_lut_rep_961_3_lut (.A(n806[3]), .B(n111027), .C(n810[3]), 
         .Z(n111019)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3103_2_lut_rep_961_3_lut.init = 16'hf6f6;
    LUT4 i5642_3_lut_4_lut (.A(n806[3]), .B(n111027), .C(n810[3]), .D(n111012), 
         .Z(n815[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5642_3_lut_4_lut.init = 16'h6966;
    LUT4 i75553_2_lut_rep_474_4_lut (.A(n110584), .B(n110571), .C(n924[3]), 
         .D(rst_n_c), .Z(n110532)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i75553_2_lut_rep_474_4_lut.init = 16'ha600;
    LUT4 i75572_2_lut_rep_418_3_lut (.A(n110501), .B(n5133), .C(rst_n_c), 
         .Z(n110476)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i75572_2_lut_rep_418_3_lut.init = 16'h6060;
    LUT4 i75729_3_lut_4_lut_4_lut (.A(n110584), .B(n110571), .C(n924[3]), 
         .D(n110546), .Z(n14_adj_61)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A !(B+!(C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i75729_3_lut_4_lut_4_lut.init = 16'h65ff;
    LUT4 i5390_3_lut_4_lut (.A(n875[3]), .B(n110704), .C(n883[3]), .D(n110678), 
         .Z(n892[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5390_3_lut_4_lut.init = 16'h6966;
    LUT4 i5395_2_lut_rep_630_3_lut (.A(n875[3]), .B(n110704), .C(n883[3]), 
         .Z(n110688)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5395_2_lut_rep_630_3_lut.init = 16'hf6f6;
    LUT4 i5438_2_lut_rep_625_4_lut_4_lut (.A(n883[0]), .B(n110706), .C(n883[1]), 
         .D(n883[2]), .Z(n110683)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5438_2_lut_rep_625_4_lut_4_lut.init = 16'h332c;
    LUT4 i13838_2_lut_rep_924_4_lut (.A(bcd_code_31__N_965), .B(n110996), 
         .C(n816[1]), .D(n110989), .Z(n110982)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13838_2_lut_rep_924_4_lut.init = 16'hf600;
    LUT4 i3004_4_lut (.A(\lux[19] ), .B(bcd_code_31__N_1079), .C(bcd_code_31__N_1083), 
         .D(n111075), .Z(n5845)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3004_4_lut.init = 16'hfcec;
    LUT4 i5460_3_lut_4_lut_3_lut_4_lut (.A(n883[0]), .B(n110706), .C(n883[1]), 
         .D(n883[2]), .Z(n891[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5460_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5354_2_lut_rep_939_4_lut_4_lut (.A(n111033), .B(n111032), .C(n807[1]), 
         .D(n5469), .Z(n110997)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i5354_2_lut_rep_939_4_lut_4_lut.init = 16'h936c;
    LUT4 i13825_2_lut_rep_962_3_lut_4_lut (.A(n806[1]), .B(n111034), .C(n810[1]), 
         .D(n111030), .Z(n111020)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13825_2_lut_rep_962_3_lut_4_lut.init = 16'hf600;
    LUT4 i2969_3_lut_rep_966_4_lut (.A(n806[1]), .B(n111034), .C(n810[1]), 
         .D(n111030), .Z(n111024)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2969_3_lut_rep_966_4_lut.init = 16'hf666;
    LUT4 i5705_2_lut_rep_955_3_lut_3_lut_4_lut (.A(n806[1]), .B(n111034), 
         .C(n810[1]), .D(n111030), .Z(n111013)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5705_2_lut_rep_955_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5712_3_lut_4_lut_3_lut_4_lut (.A(n806[1]), .B(n111034), .C(n810[1]), 
         .D(n111030), .Z(n814[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5712_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5690_2_lut_rep_963_4_lut_4_lut (.A(bcd_code_31__N_1078), .B(n111035), 
         .C(n810[1]), .D(n111029), .Z(n111021)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5690_2_lut_rep_963_4_lut_4_lut.init = 16'h554a;
    LUT4 i6321_2_lut_rep_960_3_lut_3_lut_4_lut (.A(n804[1]), .B(n111046), 
         .C(n807[1]), .D(n111033), .Z(n111018)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6321_2_lut_rep_960_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13746_2_lut_rep_970_4_lut (.A(n804[1]), .B(n111046), .C(n807[1]), 
         .D(n111033), .Z(n111028)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13746_2_lut_rep_970_4_lut.init = 16'hf600;
    LUT4 i6328_3_lut_rep_959_4_lut_3_lut_4_lut (.A(n804[1]), .B(n111046), 
         .C(n807[1]), .D(n111033), .Z(n111017)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6328_3_lut_rep_959_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5453_2_lut_3_lut_3_lut_4_lut (.A(n883[0]), .B(n110706), .C(n883[1]), 
         .D(n883[2]), .Z(n891[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5453_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i3000_3_lut_rep_969_4_lut (.A(n804[1]), .B(n111046), .C(n807[1]), 
         .D(n111033), .Z(n111027)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3000_3_lut_rep_969_4_lut.init = 16'hf666;
    LUT4 i1_3_lut_4_lut_3_lut_4_lut (.A(n111116), .B(n5465), .Z(n4_adj_2329)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_3_lut_4_lut_3_lut_4_lut.init = 16'heeee;
    LUT4 i6306_2_lut_rep_964_4_lut_4_lut (.A(n111040), .B(n806[3]), .C(n807[1]), 
         .D(n111032), .Z(n111022)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6306_2_lut_rep_964_4_lut_4_lut.init = 16'h332c;
    LUT4 i5446_3_lut_4_lut (.A(n883[0]), .B(n110706), .C(n883[1]), .D(n883[2]), 
         .Z(n891[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5446_3_lut_4_lut.init = 16'h998a;
    LUT4 i2665_2_lut_rep_972_3_lut (.A(bcd_code_31__N_1029), .B(n111041), 
         .C(bcd_code_31__N_1078), .Z(n111030)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2665_2_lut_rep_972_3_lut.init = 16'hf6f6;
    LUT4 i5698_3_lut_4_lut (.A(bcd_code_31__N_1029), .B(n111041), .C(bcd_code_31__N_1078), 
         .D(n111024), .Z(n814[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5698_3_lut_4_lut.init = 16'h6966;
    LUT4 mux_9089_i3_3_lut_rep_937_4_lut (.A(n111043), .B(n111092), .C(n6358), 
         .D(n6354), .Z(n110995)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_9089_i3_3_lut_rep_937_4_lut.init = 16'hf780;
    LUT4 i6314_3_lut_4_lut (.A(n803[3]), .B(n111045), .C(n806[3]), .D(n111027), 
         .Z(n811[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6314_3_lut_4_lut.init = 16'h6966;
    LUT4 i6319_2_lut_rep_975_3_lut (.A(n803[3]), .B(n111045), .C(n806[3]), 
         .Z(n111033)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6319_2_lut_rep_975_3_lut.init = 16'hf6f6;
    LUT4 i75558_3_lut_4_lut_4_lut (.A(n110561), .B(n926[2]), .C(n926[1]), 
         .D(rst_n_c), .Z(\lux_data[15] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75558_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i75559_2_lut_rep_455_4_lut_4_lut (.A(n110561), .B(n926[2]), .C(n926[1]), 
         .D(rst_n_c), .Z(n110513)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75559_2_lut_rep_455_4_lut_4_lut.init = 16'h6c00;
    LUT4 i8527_2_lut_4_lut_4_lut (.A(n801[3]), .B(bcd_code_31__N_895), .C(n111031), 
         .D(n23), .Z(n12539)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B+(D)))) */ ;
    defparam i8527_2_lut_4_lut_4_lut.init = 16'h0091;
    LUT4 i3120_2_lut_rep_985 (.A(bcd_code_31__N_895), .B(n801[3]), .Z(n111043)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3120_2_lut_rep_985.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(bcd_code_31__N_895), .B(n801[3]), 
         .C(n111031), .D(n111092), .Z(n29)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+(D))+!B (C)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'h0b05;
    LUT4 bcd_code_31__N_804_bdd_4_lut_4_lut (.A(bcd_code_31__N_895), .B(n801[3]), 
         .C(n111092), .D(n111031), .Z(n110282)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B (C+!(D))+!B (D)))) */ ;
    defparam bcd_code_31__N_804_bdd_4_lut_4_lut.init = 16'h73c6;
    LUT4 i3648_3_lut_4_lut_3_lut_4_lut (.A(n888[3]), .B(n110708), .C(n889[1]), 
         .D(n889[2]), .Z(n897[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i3648_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i8482_2_lut_rep_953_4_lut_4_lut (.A(n111052), .B(n111051), .C(n804[1]), 
         .D(n23), .Z(n111011)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D)))) */ ;
    defparam i8482_2_lut_rep_953_4_lut_4_lut.init = 16'h6c93;
    LUT4 i13741_2_lut_rep_976_3_lut_4_lut (.A(n803[1]), .B(n111053), .C(n806[1]), 
         .D(n111048), .Z(n111034)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13741_2_lut_rep_976_3_lut_4_lut.init = 16'hf600;
    LUT4 i6356_3_lut_4_lut_3_lut_4_lut (.A(n803[1]), .B(n111053), .C(n806[1]), 
         .D(n111048), .Z(n810[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6356_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i3001_3_lut_rep_983_4_lut (.A(n803[1]), .B(n111053), .C(n806[1]), 
         .D(n111048), .Z(n111041)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3001_3_lut_rep_983_4_lut.init = 16'hf666;
    LUT4 i6349_2_lut_rep_971_3_lut_3_lut_4_lut (.A(n803[1]), .B(n111053), 
         .C(n806[1]), .D(n111048), .Z(n111029)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6349_2_lut_rep_971_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4023_2_lut_rep_480_3_lut (.A(n917[3]), .B(n110574), .C(n926[3]), 
         .Z(n110538)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4023_2_lut_rep_480_3_lut.init = 16'hf6f6;
    LUT4 i3626_2_lut_rep_622_4_lut_4_lut (.A(n888[3]), .B(n110708), .C(n889[1]), 
         .D(n889[2]), .Z(n110680)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i3626_2_lut_rep_622_4_lut_4_lut.init = 16'h554a;
    LUT4 i6334_2_lut_rep_977_4_lut_4_lut (.A(n111054), .B(bcd_code_31__N_1029), 
         .C(n806[1]), .D(n111047), .Z(n111035)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6334_2_lut_rep_977_4_lut_4_lut.init = 16'h332c;
    LUT4 i3641_2_lut_3_lut_3_lut_4_lut (.A(n888[3]), .B(n110708), .C(n889[1]), 
         .D(n889[2]), .Z(n897[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i3641_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i75731_3_lut_4_lut (.A(n110497), .B(rst_n_c), .C(n110490), .D(n110491), 
         .Z(n14_adj_62)) /* synthesis lut_function=(((C (D)+!C !(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75731_3_lut_4_lut.init = 16'hf77f;
    LUT4 i75687_4_lut_4_lut_4_lut (.A(n110480), .B(rst_n_c), .C(n110487), 
         .D(n110481), .Z(n16456)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75687_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i6440_3_lut_rep_973_4_lut_3_lut_4_lut (.A(bcd_code_31__N_900), .B(n111056), 
         .C(n804[1]), .D(n111052), .Z(n111031)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6440_3_lut_rep_973_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i75442_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), 
         .C(n110491), .D(n110490), .Z(n14_adj_63)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75442_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 i13731_2_lut_rep_988_4_lut (.A(bcd_code_31__N_900), .B(n111056), 
         .C(n804[1]), .D(n111052), .Z(n111046)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13731_2_lut_rep_988_4_lut.init = 16'hf600;
    LUT4 i3005_3_lut_rep_987_4_lut (.A(bcd_code_31__N_900), .B(n111056), 
         .C(n804[1]), .D(n111052), .Z(n111045)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3005_3_lut_rep_987_4_lut.init = 16'hf666;
    LUT4 i3634_3_lut_4_lut (.A(n888[3]), .B(n110708), .C(n889[1]), .D(n889[2]), 
         .Z(n897[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i3634_3_lut_4_lut.init = 16'h998c;
    LUT4 i6433_2_lut_rep_974_3_lut_3_lut_4_lut (.A(bcd_code_31__N_900), .B(n111056), 
         .C(n804[1]), .D(n111052), .Z(n111032)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6433_2_lut_rep_974_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i75663_4_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), .C(n110491), 
         .D(n110490), .Z(n14_adj_64)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75663_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i6418_2_lut_rep_982_4_lut_4_lut (.A(n111055), .B(n803[3]), .C(n804[1]), 
         .D(n111051), .Z(n111040)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6418_2_lut_rep_982_4_lut_4_lut.init = 16'h332c;
    LUT4 mux_21_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110497), 
         .B(rst_n_c), .C(n110491), .D(n110490), .Z(n7_adj_65)) /* synthesis lut_function=(!(A ((C (D)+!C !(D))+!B)+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_21_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h4cc0;
    LUT4 i6342_3_lut_4_lut (.A(bcd_code_31__N_987), .B(n111057), .C(bcd_code_31__N_1029), 
         .D(n111041), .Z(n810[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6342_3_lut_4_lut.init = 16'h6966;
    LUT4 i6347_2_lut_rep_990_3_lut (.A(bcd_code_31__N_987), .B(n111057), 
         .C(bcd_code_31__N_1029), .Z(n111048)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6347_2_lut_rep_990_3_lut.init = 16'hf6f6;
    LUT4 i6431_2_lut_rep_994_3_lut (.A(n111071), .B(n5952), .C(n803[3]), 
         .Z(n111052)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6431_2_lut_rep_994_3_lut.init = 16'hf6f6;
    LUT4 i4522_3_lut_rep_545_4_lut_3_lut_4_lut (.A(n110641), .B(n906[3]), 
         .C(n907[1]), .D(n907[2]), .Z(n110603)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4522_3_lut_rep_545_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i6426_3_lut_4_lut (.A(n111071), .B(n5952), .C(n803[3]), .D(n111045), 
         .Z(n807[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6426_3_lut_4_lut.init = 16'h6966;
    LUT4 i75476_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), 
         .C(n110491), .D(n110490), .Z(n14_adj_66)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75476_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 i6636_3_lut_4_lut (.A(n5952), .B(n111063), .C(bcd_code_31__N_900), 
         .D(bcd_code_31__N_896), .Z(bcd_code_31__N_895)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6636_3_lut_4_lut.init = 16'h7f80;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_193 (.A(n110497), .B(rst_n_c), 
         .C(n110491), .D(n110490), .Z(n107670)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_193.init = 16'hffbf;
    LUT4 i75798_2_lut_3_lut (.A(n110501), .B(n5133), .C(n110487), .Z(n83388)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i75798_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i6608_3_lut_4_lut_3_lut_4_lut (.A(n800[1]), .B(n111064), .C(n803[1]), 
         .D(n111062), .Z(n806[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6608_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i3012_3_lut_rep_999_4_lut (.A(n800[1]), .B(n111064), .C(n803[1]), 
         .D(n111062), .Z(n111057)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3012_3_lut_rep_999_4_lut.init = 16'hf666;
    LUT4 i4913_2_lut_rep_917_4_lut_4_lut (.A(n815[3]), .B(n110997), .C(n816[1]), 
         .D(n110988), .Z(n110975)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4913_2_lut_rep_917_4_lut_4_lut.init = 16'h554a;
    LUT4 i6601_2_lut_rep_989_3_lut_3_lut_4_lut (.A(n800[1]), .B(n111064), 
         .C(n803[1]), .D(n111062), .Z(n111047)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6601_2_lut_rep_989_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13843_2_lut_rep_995_3_lut_4_lut (.A(n800[1]), .B(n111064), .C(n803[1]), 
         .D(n111062), .Z(n111053)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13843_2_lut_rep_995_3_lut_4_lut.init = 16'hf600;
    LUT4 i75665_3_lut_4_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), .C(n110491), 
         .D(n110490), .Z(n16625)) /* synthesis lut_function=(A ((C+(D))+!B)+!A ((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75665_3_lut_4_lut_4_lut_4_lut.init = 16'hfbf7;
    LUT4 i6586_2_lut_rep_996_4_lut_4_lut (.A(bcd_code_31__N_987), .B(n111065), 
         .C(n803[1]), .D(n111061), .Z(n111054)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6586_2_lut_rep_996_4_lut_4_lut.init = 16'h554a;
    LUT4 i13151_2_lut_3_lut_4_lut (.A(n793[3]), .B(n111068), .C(bcd_code_31__N_895), 
         .D(n111113), .Z(n20274)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A (C+(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13151_2_lut_3_lut_4_lut.init = 16'hf7f8;
    LUT4 i3084_2_lut_rep_926_3_lut (.A(n814[3]), .B(n110998), .C(n818[3]), 
         .Z(n110984)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3084_2_lut_rep_926_3_lut.init = 16'hf6f6;
    LUT4 i3015_3_lut_4_lut (.A(n111071), .B(n111069), .C(bcd_code_31__N_900), 
         .D(bcd_code_31__N_896), .Z(n5952)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i3015_3_lut_4_lut.init = 16'hffe0;
    LUT4 i6629_2_lut_rep_993_3_lut_4_lut (.A(n111071), .B(n111069), .C(bcd_code_31__N_900), 
         .D(n5952), .Z(n111051)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam i6629_2_lut_rep_993_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i6762_3_lut_4_lut (.A(n814[3]), .B(n110998), .C(n818[3]), .D(n110976), 
         .Z(n824[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6762_3_lut_4_lut.init = 16'h6966;
    LUT4 i75664_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), 
         .C(n110490), .D(n110491), .Z(n14_adj_67)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75664_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hff7f;
    LUT4 i3124_2_lut_rep_1004_3_lut (.A(bcd_code_31__N_951), .B(n111070), 
         .C(bcd_code_31__N_987), .Z(n111062)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3124_2_lut_rep_1004_3_lut.init = 16'hf6f6;
    LUT4 mux_21_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110497), 
         .B(rst_n_c), .C(n110491), .D(n110490), .Z(n14_adj_68)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_21_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i6594_3_lut_4_lut (.A(bcd_code_31__N_951), .B(n111070), .C(bcd_code_31__N_987), 
         .D(n111057), .Z(n806[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6594_3_lut_4_lut.init = 16'h6966;
    LUT4 i1_4_lut (.A(n32), .B(n111113), .C(n29_adj_2337), .D(n109677), 
         .Z(n23_adj_69)) /* synthesis lut_function=(A+!(B+!(C+!(D)))) */ ;
    defparam i1_4_lut.init = 16'hbabb;
    LUT4 i75429_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110497), .B(rst_n_c), 
         .C(n110490), .D(n110491), .Z(n7_adj_70)) /* synthesis lut_function=(!(A (B)+!A !(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75429_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7737;
    LUT4 i13228_3_lut_rep_1010 (.A(n23_adj_69), .B(bcd_code_31__N_850), 
         .C(n111082), .Z(n111068)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13228_3_lut_rep_1010.init = 16'h5454;
    LUT4 i13839_2_lut_rep_998_3_lut_4_lut (.A(n111082), .B(n23_adj_69), 
         .C(n5952), .D(n111071), .Z(n111056)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (B (C (D))+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13839_2_lut_rep_998_3_lut_4_lut.init = 16'hf090;
    LUT4 i2707_2_lut_rep_1005_3_lut (.A(n111082), .B(n23_adj_69), .C(n111071), 
         .Z(n111063)) /* synthesis lut_function=(A (B+(C))+!A ((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2707_2_lut_rep_1005_3_lut.init = 16'hf9f9;
    LUT4 i75556_2_lut_rep_464_3_lut (.A(n110572), .B(n110562), .C(rst_n_c), 
         .Z(n110522)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i75556_2_lut_rep_464_3_lut.init = 16'h6060;
    LUT4 i6622_3_lut_4_lut (.A(n111082), .B(n23_adj_69), .C(n111071), 
         .D(n5952), .Z(n804[1])) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6622_3_lut_4_lut.init = 16'h9699;
    LUT4 i6482_3_lut_4_lut (.A(n890[3]), .B(n110683), .C(n891[1]), .D(n891[2]), 
         .Z(n899[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i6482_3_lut_4_lut.init = 16'h998c;
    LUT4 i2985_3_lut_rep_635_4_lut (.A(n870[1]), .B(n110723), .C(n877[1]), 
         .D(n110703), .Z(n110693)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2985_3_lut_rep_635_4_lut.init = 16'hf666;
    LUT4 i6041_2_lut_rep_618_3_lut_3_lut_4_lut (.A(n870[1]), .B(n110723), 
         .C(n877[1]), .D(n110703), .Z(n110676)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i6041_2_lut_rep_618_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13834_2_lut_rep_1006_3_lut_4_lut (.A(n797[1]), .B(n111079), .C(n800[1]), 
         .D(n111073), .Z(n111064)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13834_2_lut_rep_1006_3_lut_4_lut.init = 16'hf600;
    LUT4 i6657_2_lut_rep_1003_3_lut_3_lut_4_lut (.A(n797[1]), .B(n111079), 
         .C(n800[1]), .D(n111073), .Z(n111061)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6657_2_lut_rep_1003_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i3016_3_lut_rep_1012_4_lut (.A(n797[1]), .B(n111079), .C(n800[1]), 
         .D(n111073), .Z(n111070)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3016_3_lut_rep_1012_4_lut.init = 16'hf666;
    LUT4 i6664_3_lut_4_lut_3_lut_4_lut (.A(n797[1]), .B(n111079), .C(n800[1]), 
         .D(n111073), .Z(n803[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6664_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6642_2_lut_rep_1007_4_lut_4_lut (.A(bcd_code_31__N_951), .B(n111077), 
         .C(n800[1]), .D(n111072), .Z(n111065)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6642_2_lut_rep_1007_4_lut_4_lut.init = 16'h554a;
    LUT4 i75569_2_lut_rep_427_4_lut (.A(n110518), .B(n110511), .C(n928[3]), 
         .D(rst_n_c), .Z(n110485)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i75569_2_lut_rep_427_4_lut.init = 16'ha600;
    LUT4 i2913_3_lut_rep_574 (.A(n110641), .B(n906[3]), .C(n907[1]), .D(n907[2]), 
         .Z(n110632)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2913_3_lut_rep_574.init = 16'hffe0;
    LUT4 i9443_3_lut_rep_462_4_lut (.A(n110572), .B(n110562), .C(rst_n_c), 
         .D(n110534), .Z(n110520)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i9443_3_lut_rep_462_4_lut.init = 16'h9060;
    LUT4 i13796_2_lut_rep_604_3_lut_4_lut (.A(n877[1]), .B(n110694), .C(n885[1]), 
         .D(n110677), .Z(n110662)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i13796_2_lut_rep_604_3_lut_4_lut.init = 16'hf600;
    LUT4 i3126_2_lut_rep_1015_3_lut (.A(bcd_code_31__N_913), .B(n111078), 
         .C(bcd_code_31__N_951), .Z(n111073)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3126_2_lut_rep_1015_3_lut.init = 16'hf6f6;
    LUT4 i6048_3_lut_rep_617_4_lut_3_lut_4_lut (.A(n870[1]), .B(n110723), 
         .C(n877[1]), .D(n110703), .Z(n110675)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i6048_3_lut_rep_617_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6650_3_lut_4_lut (.A(bcd_code_31__N_913), .B(n111078), .C(bcd_code_31__N_951), 
         .D(n111070), .Z(n803[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6650_3_lut_4_lut.init = 16'h6966;
    LUT4 i2946_3_lut_rep_613_4_lut (.A(n877[1]), .B(n110694), .C(n885[1]), 
         .D(n110677), .Z(n110671)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2946_3_lut_rep_613_4_lut.init = 16'hf666;
    LUT4 i6614_2_lut_rep_997_4_lut_4_lut (.A(n111084), .B(n111083), .C(n797[1]), 
         .D(n5952), .Z(n111055)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i6614_2_lut_rep_997_4_lut_4_lut.init = 16'h936c;
    LUT4 i13790_2_lut_rep_636_4_lut (.A(n870[1]), .B(n110723), .C(n877[1]), 
         .D(n110703), .Z(n110694)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i13790_2_lut_rep_636_4_lut.init = 16'hf600;
    LUT4 i13814_2_lut_rep_1021_4_lut (.A(n795[1]), .B(n111094), .C(n797[1]), 
         .D(n111084), .Z(n111079)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13814_2_lut_rep_1021_4_lut.init = 16'hf600;
    LUT4 i6797_2_lut_rep_1014_3_lut_3_lut_4_lut (.A(n795[1]), .B(n111094), 
         .C(n797[1]), .D(n111084), .Z(n111072)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6797_2_lut_rep_1014_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5285_2_lut_rep_594_3_lut_3_lut_4_lut (.A(n877[1]), .B(n110694), 
         .C(n885[1]), .D(n110677), .Z(n110652)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5285_2_lut_rep_594_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i3025_3_lut_rep_1020_4_lut (.A(n795[1]), .B(n111094), .C(n797[1]), 
         .D(n111084), .Z(n111078)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3025_3_lut_rep_1020_4_lut.init = 16'hf666;
    LUT4 i6804_3_lut_rep_1013_4_lut_3_lut_4_lut (.A(n795[1]), .B(n111094), 
         .C(n797[1]), .D(n111084), .Z(n111071)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6804_3_lut_rep_1013_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i75568_2_lut_rep_426_3_lut (.A(n928[3]), .B(n110511), .C(rst_n_c), 
         .Z(n110484)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i75568_2_lut_rep_426_3_lut.init = 16'h6060;
    LUT4 i6782_2_lut_rep_1019_4_lut_4_lut (.A(bcd_code_31__N_913), .B(n111087), 
         .C(n797[1]), .D(n111083), .Z(n111077)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6782_2_lut_rep_1019_4_lut_4_lut.init = 16'h554a;
    LUT4 i3404_2_lut_rep_986_4_lut (.A(n111091), .B(n111113), .C(n801[3]), 
         .D(bcd_code_31__N_895), .Z(n111044)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i3404_2_lut_rep_986_4_lut.init = 16'h8880;
    LUT4 i5292_3_lut_4_lut_3_lut_4_lut (.A(n877[1]), .B(n110694), .C(n885[1]), 
         .D(n110677), .Z(n893[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5292_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 bcd_code_31__N_804_bdd_3_lut_4_lut_3_lut_4_lut (.A(n111091), .B(n111113), 
         .C(n801[3]), .D(bcd_code_31__N_895), .Z(n110281)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (C)) */ ;
    defparam bcd_code_31__N_804_bdd_3_lut_4_lut_3_lut_4_lut.init = 16'hf070;
    LUT4 mux_9091_i3_4_lut_4_lut (.A(n111091), .B(n111113), .C(n4_adj_2340), 
         .D(n109681), .Z(n801[3])) /* synthesis lut_function=(!(A (B (C)+!B !(D))+!A !(D))) */ ;
    defparam mux_9091_i3_4_lut_4_lut.init = 16'h7f08;
    LUT4 i8504_3_lut_4_lut (.A(n111091), .B(n111113), .C(n4_adj_2341), 
         .D(n801[3]), .Z(n6354)) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i8504_3_lut_4_lut.init = 16'h7888;
    LUT4 i3137_2_lut_rep_1026_3_lut (.A(bcd_code_31__N_886), .B(n111093), 
         .C(bcd_code_31__N_913), .Z(n111084)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3137_2_lut_rep_1026_3_lut.init = 16'hf6f6;
    LUT4 i6790_3_lut_4_lut (.A(bcd_code_31__N_886), .B(n111093), .C(bcd_code_31__N_913), 
         .D(n111078), .Z(n800[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6790_3_lut_4_lut.init = 16'h6966;
    LUT4 i6026_2_lut_rep_628_4_lut_4_lut (.A(n110713), .B(n110712), .C(n877[1]), 
         .D(n110702), .Z(n110686)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i6026_2_lut_rep_628_4_lut_4_lut.init = 16'h332c;
    LUT4 i4184_2_lut_rep_483_3_lut (.A(n910[3]), .B(n110565), .C(n919[3]), 
         .Z(n110541)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4184_2_lut_rep_483_3_lut.init = 16'hf6f6;
    LUT4 i1_3_lut_4_lut_adj_194 (.A(n793[3]), .B(bcd_code_31__N_850), .C(n4_adj_2342), 
         .D(n111113), .Z(n4_adj_2340)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(B (D)+!B !(C (D)+!C !(D))))) */ ;
    defparam i1_3_lut_4_lut_adj_194.init = 16'h6f90;
    LUT4 i3877_2_lut_rep_1033 (.A(n793[3]), .B(bcd_code_31__N_850), .Z(n111091)) /* synthesis lut_function=(A+(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3877_2_lut_rep_1033.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_4_lut_adj_195 (.A(n793[3]), .B(bcd_code_31__N_850), 
         .C(n111082), .D(n111113), .Z(n29_adj_2337)) /* synthesis lut_function=(!(A (B (C+!(D))+!B (C+(D)))+!A (B (C+!(D))+!B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i1_2_lut_3_lut_4_lut_4_lut_adj_195.init = 16'h0d03;
    LUT4 bcd_code_31__N_807_bdd_4_lut_4_lut (.A(n793[3]), .B(bcd_code_31__N_850), 
         .C(n111113), .D(n111082), .Z(n110285)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B ((D)+!C)+!B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam bcd_code_31__N_807_bdd_4_lut_4_lut.init = 16'h75a6;
    LUT4 i8930_2_lut_rep_1011_4_lut_4_lut (.A(n111096), .B(n111095), .C(n795[1]), 
         .D(n23_adj_69), .Z(n111069)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D)))) */ ;
    defparam i8930_2_lut_rep_1011_4_lut_4_lut.init = 16'h6c93;
    LUT4 i3029_3_lut_rep_1035_4_lut (.A(bcd_code_31__N_855), .B(n111099), 
         .C(n795[1]), .D(n111096), .Z(n111093)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3029_3_lut_rep_1035_4_lut.init = 16'hf666;
    LUT4 i13785_2_lut_rep_1036_4_lut (.A(bcd_code_31__N_855), .B(n111099), 
         .C(n795[1]), .D(n111096), .Z(n111094)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13785_2_lut_rep_1036_4_lut.init = 16'hf600;
    LUT4 i6888_3_lut_rep_1024_4_lut_3_lut_4_lut (.A(bcd_code_31__N_855), .B(n111099), 
         .C(n795[1]), .D(n111096), .Z(n111082)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6888_3_lut_rep_1024_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6881_2_lut_rep_1025_3_lut_3_lut_4_lut (.A(bcd_code_31__N_855), .B(n111099), 
         .C(n795[1]), .D(n111096), .Z(n111083)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6881_2_lut_rep_1025_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6866_2_lut_rep_1029_4_lut_4_lut (.A(n111100), .B(bcd_code_31__N_886), 
         .C(n795[1]), .D(n111095), .Z(n111087)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6866_2_lut_rep_1029_4_lut_4_lut.init = 16'h332c;
    LUT4 i13826_2_lut_rep_808_3_lut_4_lut (.A(n839[1]), .B(n110891), .C(n845[1]), 
         .D(n110883), .Z(n110866)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13826_2_lut_rep_808_3_lut_4_lut.init = 16'hf600;
    LUT4 i5137_2_lut_rep_1042 (.A(bcd_code_31__N_859), .B(n5361), .Z(n111100)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5137_2_lut_rep_1042.init = 16'h6666;
    LUT4 i6874_3_lut_4_lut (.A(bcd_code_31__N_859), .B(n5361), .C(bcd_code_31__N_886), 
         .D(n111093), .Z(n797[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6874_3_lut_4_lut.init = 16'h6966;
    LUT4 i6879_2_lut_rep_1038_3_lut (.A(bcd_code_31__N_859), .B(n5361), 
         .C(bcd_code_31__N_886), .Z(n111096)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6879_2_lut_rep_1038_3_lut.init = 16'hf6f6;
    LUT4 i2941_3_lut_4_lut (.A(bcd_code_31__N_859), .B(n111106), .C(bcd_code_31__N_855), 
         .D(bcd_code_31__N_851), .Z(n5361)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i2941_3_lut_4_lut.init = 16'hffe0;
    LUT4 i5152_2_lut_rep_1037_3_lut_4_lut (.A(bcd_code_31__N_859), .B(n111106), 
         .C(bcd_code_31__N_855), .D(n5361), .Z(n111095)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam i5152_2_lut_rep_1037_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i13186_3_lut_rep_1047 (.A(n5465), .B(bcd_code_31__N_841), .Z(n111105)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13186_3_lut_rep_1047.init = 16'h8888;
    LUT4 i1_4_lut_adj_196 (.A(n111092), .B(n35_adj_2343), .C(n29), .D(n109681), 
         .Z(n23)) /* synthesis lut_function=(A (B)+!A (B+(C+!(D)))) */ ;
    defparam i1_4_lut_adj_196.init = 16'hdcdd;
    LUT4 i5376_3_lut_4_lut (.A(n5469), .B(n111007), .C(bcd_code_31__N_965), 
         .D(bcd_code_31__N_961), .Z(bcd_code_31__N_960)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5376_3_lut_4_lut.init = 16'h7f80;
    LUT4 i7771_2_lut_rep_1045_4_lut (.A(n5465), .B(bcd_code_31__N_841), 
         .C(n111116), .Z(n111103)) /* synthesis lut_function=(A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i7771_2_lut_rep_1045_4_lut.init = 16'h8080;
    LUT4 i6692_3_lut_4_lut_3_lut_4_lut (.A(n839[1]), .B(n110891), .C(n845[1]), 
         .D(n110883), .Z(n851[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6692_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i7754_2_lut_rep_1048 (.A(bcd_code_31__N_841), .B(n5465), .Z(n111106)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i7754_2_lut_rep_1048.init = 16'h6666;
    LUT4 i13813_2_lut_rep_1041_3_lut_4_lut (.A(bcd_code_31__N_841), .B(n5465), 
         .C(n5361), .D(bcd_code_31__N_859), .Z(n111099)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (B (C)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13813_2_lut_rep_1041_3_lut_4_lut.init = 16'hf060;
    LUT4 i5145_3_lut_4_lut (.A(bcd_code_31__N_841), .B(n5465), .C(bcd_code_31__N_859), 
         .D(n5361), .Z(n795[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5145_3_lut_4_lut.init = 16'h6966;
    LUT4 i2638_2_lut_rep_931_3_lut (.A(n111017), .B(n5469), .C(n815[3]), 
         .Z(n110989)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2638_2_lut_rep_931_3_lut.init = 16'hf6f6;
    LUT4 i4921_3_lut_4_lut (.A(n111017), .B(n5469), .C(n815[3]), .D(n110981), 
         .Z(n820[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4921_3_lut_4_lut.init = 16'h6966;
    LUT4 i101754_2_lut_3_lut_4_lut (.A(n111112), .B(\lux[29] ), .C(n111068), 
         .D(n793[3]), .Z(n109681)) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i101754_2_lut_3_lut_4_lut.init = 16'h7888;
    LUT4 i13229_3_lut (.A(n23_adj_69), .B(bcd_code_31__N_850), .C(n111082), 
         .Z(n4_adj_2342)) /* synthesis lut_function=(!(A+!((C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13229_3_lut.init = 16'h5151;
    LUT4 i101161_4_lut_4_lut (.A(n111112), .B(\lux[29] ), .C(n4_adj_2329), 
         .D(n111103), .Z(n793[3])) /* synthesis lut_function=(!(A (B (C)+!B !(D))+!A (B (D)+!B !(D)))) */ ;
    defparam i101161_4_lut_4_lut.init = 16'h3b4c;
    LUT4 i3407_2_lut_rep_1034_4_lut (.A(n111112), .B(\lux[29] ), .C(bcd_code_31__N_850), 
         .D(n793[3]), .Z(n111092)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i3407_2_lut_rep_1034_4_lut.init = 16'h8880;
    LUT4 bcd_code_31__N_807_bdd_3_lut_102107_4_lut_3_lut_4_lut (.A(n111112), 
         .B(\lux[29] ), .C(bcd_code_31__N_850), .D(n793[3]), .Z(n110284)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (D)) */ ;
    defparam bcd_code_31__N_807_bdd_3_lut_102107_4_lut_3_lut_4_lut.init = 16'hf700;
    LUT4 i3017_3_lut_rep_817_4_lut (.A(n839[1]), .B(n110891), .C(n845[1]), 
         .D(n110883), .Z(n110875)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3017_3_lut_rep_817_4_lut.init = 16'hf666;
    LUT4 i4508_3_lut_4_lut (.A(n110641), .B(n906[3]), .C(n907[1]), .D(n907[2]), 
         .Z(n916[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4508_3_lut_4_lut.init = 16'h998a;
    LUT4 bcd_code_31__N_810_bdd_4_lut_4_lut (.A(n111116), .B(\lux[29] ), 
         .C(bcd_code_31__N_841), .Z(n110289)) /* synthesis lut_function=(A (B+!(C))+!A (C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam bcd_code_31__N_810_bdd_4_lut_4_lut.init = 16'hdada;
    LUT4 i2945_4_lut_4_lut_then_4_lut (.A(n110720), .B(n110806), .C(n894[3]), 
         .D(n110607), .Z(n111268)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (C+(D))) */ ;
    defparam i2945_4_lut_4_lut_then_4_lut.init = 16'hff78;
    LUT4 i4367_2_lut_rep_441_4_lut_4_lut (.A(n110564), .B(n911[2]), .C(n911[1]), 
         .D(n110500), .Z(n110499)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i4367_2_lut_rep_441_4_lut_4_lut.init = 16'h936c;
    LUT4 i2945_4_lut_4_lut_else_4_lut (.A(n110720), .B(n110806), .C(n894[3]), 
         .D(n886[3]), .Z(n111267)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i2945_4_lut_4_lut_else_4_lut.init = 16'h0008;
    LUT4 i5270_2_lut_rep_605_4_lut_4_lut (.A(n110686), .B(n110685), .C(n885[1]), 
         .D(n110676), .Z(n110663)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5270_2_lut_rep_605_4_lut_4_lut.init = 16'h332c;
    LUT4 i75775_2_lut_rep_425_3_lut_4_lut (.A(n928[3]), .B(n110511), .C(rst_n_c), 
         .D(n110497), .Z(n110483)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i75775_2_lut_rep_425_3_lut_4_lut.init = 16'h6000;
    LUT4 i6685_2_lut_rep_798_3_lut_3_lut_4_lut (.A(n839[1]), .B(n110891), 
         .C(n845[1]), .D(n110883), .Z(n110856)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6685_2_lut_rep_798_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i75662_4_lut_4_lut_4_lut (.A(n110568), .B(rst_n_c), .C(n110582), 
         .D(n110567), .Z(n16700)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75662_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i3434_2_lut_rep_1055_4_lut_4_lut_1_lut (.A(\lux[29] ), .Z(n111113)) /* synthesis lut_function=(A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i3434_2_lut_rep_1055_4_lut_4_lut_1_lut.init = 16'haaaa;
    LUT4 i6670_2_lut_rep_809_4_lut_4_lut (.A(n110892), .B(bcd_code_31__N_1519), 
         .C(n845[1]), .D(n110882), .Z(n110867)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6670_2_lut_rep_809_4_lut_4_lut.init = 16'h332c;
    LUT4 i101750_2_lut_3_lut_4_lut_4_lut_2_lut (.A(\lux[29] ), .B(n111105), 
         .Z(n109677)) /* synthesis lut_function=(!((B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i101750_2_lut_3_lut_4_lut_4_lut_2_lut.init = 16'h2222;
    LUT4 i101175_3_lut_rep_1058_4_lut_4_lut_3_lut_1_lut (.A(\lux[29] ), .Z(n111116)) /* synthesis lut_function=(A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i101175_3_lut_rep_1058_4_lut_4_lut_3_lut_1_lut.init = 16'haaaa;
    LUT4 i11568_3_lut_4_lut_4_lut_else_4_lut_2_lut (.A(\lux[27] ), .B(\lux[29] ), 
         .Z(n111291)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11568_3_lut_4_lut_4_lut_else_4_lut_2_lut.init = 16'h8888;
    LUT4 i11568_3_lut_4_lut_4_lut_then_4_lut_2_lut (.A(\lux[27] ), .B(\lux[29] ), 
         .Z(n111292)) /* synthesis lut_function=(!(A+(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i11568_3_lut_4_lut_4_lut_then_4_lut_2_lut.init = 16'h1111;
    LUT4 i75806_2_lut_3_lut (.A(n928[3]), .B(n110511), .C(n110497), .Z(n83384)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i75806_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i5283_2_lut_rep_619_4_lut_4_lut (.A(n110715), .B(n110714), .C(n876[1]), 
         .D(n110686), .Z(n110677)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i5283_2_lut_rep_619_4_lut_4_lut.init = 16'hff6c;
    LUT4 i8532_4_lut (.A(n20274), .B(n12539), .C(n111043), .D(n111092), 
         .Z(n6358)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A (B (C+!(D))+!B !(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i8532_4_lut.init = 16'hc366;
    LUT4 i13212_3_lut (.A(n23), .B(bcd_code_31__N_895), .C(n111031), .Z(n4_adj_2341)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13212_3_lut.init = 16'h5454;
    LUT4 i75871_4_lut_4_lut (.A(n110567), .B(rst_n_c), .C(n83401), .D(n110555), 
         .Z(n83413)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75871_4_lut_4_lut.init = 16'h37bf;
    LUT4 i4683_3_lut_rep_548_4_lut_3_lut_4_lut (.A(n110644), .B(n899[3]), 
         .C(n900[1]), .D(n900[2]), .Z(n110606)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4683_3_lut_rep_548_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i10512_3_lut_rep_428_4_lut (.A(n928[3]), .B(n110511), .C(rst_n_c), 
         .D(n110497), .Z(n110486)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i10512_3_lut_rep_428_4_lut.init = 16'h9060;
    LUT4 i10502_3_lut_rep_420_4_lut (.A(n110501), .B(n5133), .C(rst_n_c), 
         .D(n110487), .Z(n110478)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i10502_3_lut_rep_420_4_lut.init = 16'h9060;
    LUT4 i5733_2_lut_rep_802_3_lut_3_lut_4_lut (.A(n831[1]), .B(n110907), 
         .C(n836[1]), .D(n110887), .Z(n110860)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5733_2_lut_rep_802_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i1_4_lut_adj_197 (.A(n110980), .B(n35), .C(n29_adj_2344), .D(n110930), 
         .Z(n23_adj_71)) /* synthesis lut_function=(A (B)+!A (B+(C+!(D)))) */ ;
    defparam i1_4_lut_adj_197.init = 16'hdcdd;
    LUT4 i5740_3_lut_rep_801_4_lut_3_lut_4_lut (.A(n831[1]), .B(n110907), 
         .C(n836[1]), .D(n110887), .Z(n110859)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5740_3_lut_rep_801_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4676_2_lut_3_lut_3_lut_4_lut (.A(n110644), .B(n899[3]), .C(n900[1]), 
         .D(n900[2]), .Z(n909[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4676_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i13221_3_lut (.A(n5948), .B(bcd_code_31__N_960), .C(n110966), 
         .Z(n4_c)) /* synthesis lut_function=(A ((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13221_3_lut.init = 16'ha2a2;
    LUT4 i5565_2_lut_3_lut_3_lut_4_lut (.A(n110719), .B(n881[3]), .C(n882[1]), 
         .D(n882[2]), .Z(n890[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5565_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2970_3_lut_rep_819_4_lut (.A(n831[1]), .B(n110907), .C(n836[1]), 
         .D(n110887), .Z(n110877)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2970_3_lut_rep_819_4_lut.init = 16'hf666;
    LUT4 i5572_3_lut_4_lut_3_lut_4_lut (.A(n110719), .B(n881[3]), .C(n882[1]), 
         .D(n882[2]), .Z(n890[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5572_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i7972_4_lut (.A(n20271), .B(n11979), .C(n110904), .D(n110980), 
         .Z(n6268)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A (B (C+!(D))+!B !(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i7972_4_lut.init = 16'hc366;
    LUT4 i13192_3_lut (.A(n23_adj_71), .B(bcd_code_31__N_1042), .C(n110885), 
         .Z(n4_adj_2346)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13192_3_lut.init = 16'h5454;
    LUT4 i5550_2_lut_rep_634_4_lut_4_lut (.A(n110719), .B(n881[3]), .C(n882[1]), 
         .D(n882[2]), .Z(n110692)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5550_2_lut_rep_634_4_lut_4_lut.init = 16'h332c;
    LUT4 i5558_3_lut_4_lut (.A(n110719), .B(n881[3]), .C(n882[1]), .D(n882[2]), 
         .Z(n890[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5558_3_lut_4_lut.init = 16'h998a;
    LUT4 i6978_3_lut_3_lut_4_lut (.A(n110720), .B(n110806), .C(n894[3]), 
         .D(n886[3]), .Z(n878[0])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C))+!A !(C))) */ ;
    defparam i6978_3_lut_3_lut_4_lut.init = 16'h7870;
    LUT4 i75727_3_lut_4_lut_4_lut (.A(n110499), .B(n5133), .C(n110501), 
         .D(n110482), .Z(n14_adj_72)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A !(B+!(C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i75727_3_lut_4_lut_4_lut.init = 16'h65ff;
    LUT4 i13198_3_lut (.A(n5653), .B(bcd_code_31__N_797), .C(n110788), 
         .Z(n4)) /* synthesis lut_function=(A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i13198_3_lut.init = 16'ha8a8;
    LUT4 mux_9088_i3_4_lut_4_lut (.A(n110720), .B(n110806), .C(n12231), 
         .D(n6313), .Z(n886[3])) /* synthesis lut_function=(A (B (D)+!B (C))+!A !(B (C)+!B !(C))) */ ;
    defparam mux_9088_i3_4_lut_4_lut.init = 16'hbc34;
    LUT4 i75573_2_lut_rep_417_4_lut (.A(n110499), .B(n5133), .C(n110501), 
         .D(rst_n_c), .Z(n110475)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i75573_2_lut_rep_417_4_lut.init = 16'ha600;
    LUT4 i7007_4_lut (.A(n886[3]), .B(n6313), .C(n894[3]), .D(n110721), 
         .Z(n878[1])) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i7007_4_lut.init = 16'ha6aa;
    LUT4 i5257_3_lut (.A(n878[0]), .B(n5365), .C(n110607), .Z(n903[1])) /* synthesis lut_function=(A ((C)+!B)+!A !((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i5257_3_lut.init = 16'ha6a6;
    LUT4 i13203_3_lut (.A(n5695), .B(bcd_code_31__N_1384), .C(n110701), 
         .Z(n4_adj_2349)) /* synthesis lut_function=(A ((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i13203_3_lut.init = 16'ha2a2;
    LUT4 i1_4_lut_4_lut_adj_198 (.A(bcd_code_31__N_895), .B(n801[3]), .C(n111092), 
         .D(n111031), .Z(n35_adj_2343)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C))+!A !(B (C+!(D))))) */ ;
    defparam i1_4_lut_4_lut_adj_198.init = 16'h60e4;
    LUT4 i75554_3_lut_4_lut_4_lut (.A(n110570), .B(n925[2]), .C(n925[1]), 
         .D(rst_n_c), .Z(\lux_data[11] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75554_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i75781_2_lut_rep_421_3_lut_4_lut (.A(n110487), .B(rst_n_c), .C(n5133), 
         .D(n110501), .Z(n110479)) /* synthesis lut_function=(!(((C (D)+!C !(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75781_2_lut_rep_421_3_lut_4_lut.init = 16'h0880;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_199 (.A(n110487), .B(rst_n_c), 
         .C(n110481), .D(n110480), .Z(n107662)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_199.init = 16'hfbff;
    LUT4 i2_2_lut_rep_419_3_lut_4_lut (.A(n110487), .B(rst_n_c), .C(n5133), 
         .D(n110501), .Z(n110477)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_2_lut_rep_419_3_lut_4_lut.init = 16'h8008;
    LUT4 i75377_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), 
         .C(n110481), .D(n110480), .Z(n14_adj_73)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75377_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3fbf;
    LUT4 mux_19_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110487), 
         .B(rst_n_c), .C(n110481), .D(n110480), .Z(n7_adj_74)) /* synthesis lut_function=(!(A ((C (D)+!C !(D))+!B)+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_19_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h4cc0;
    LUT4 i1_2_lut_rep_465_4_lut_4_lut (.A(n110570), .B(n925[2]), .C(n925[1]), 
         .D(rst_n_c), .Z(n110523)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i1_2_lut_rep_465_4_lut_4_lut.init = 16'h6c00;
    LUT4 i6034_3_lut_4_lut (.A(n869[3]), .B(n110722), .C(n110712), .D(n110693), 
         .Z(n885[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i6034_3_lut_4_lut.init = 16'h6966;
    LUT4 i75680_4_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), .C(n110480), 
         .D(n110481), .Z(n14_adj_75)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75680_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i75789_2_lut_4_lut_4_lut (.A(n110570), .B(n925[2]), .C(n925[1]), 
         .D(n110535), .Z(n83393)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i75789_2_lut_4_lut_4_lut.init = 16'hff6c;
    LUT4 i75678_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), 
         .C(n110480), .D(n110481), .Z(n14_adj_76)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75678_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hf7ff;
    LUT4 i2986_3_lut_rep_646_4_lut (.A(n869[1]), .B(n110733), .C(n876[1]), 
         .D(n110715), .Z(n110704)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2986_3_lut_rep_646_4_lut.init = 16'hf666;
    LUT4 i6069_2_lut_rep_629_3_lut_3_lut_4_lut (.A(n869[1]), .B(n110733), 
         .C(n876[1]), .D(n110715), .Z(n110687)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6069_2_lut_rep_629_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i75677_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), 
         .C(n110481), .D(n110480), .Z(n14_adj_77)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75677_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hffbf;
    LUT4 i4060_3_lut_rep_466_4_lut_3_lut_4_lut (.A(n926[0]), .B(n110572), 
         .C(n926[1]), .D(n926[2]), .Z(n110524)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4060_3_lut_rep_466_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i6076_3_lut_rep_627_4_lut_3_lut_4_lut (.A(n869[1]), .B(n110733), 
         .C(n876[1]), .D(n110715), .Z(n110685)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6076_3_lut_rep_627_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i13789_2_lut_rep_647_4_lut (.A(n869[1]), .B(n110733), .C(n876[1]), 
         .D(n110715), .Z(n110705)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13789_2_lut_rep_647_4_lut.init = 16'hf600;
    LUT4 i4038_2_lut_rep_477_4_lut_4_lut (.A(n926[0]), .B(n110572), .C(n926[1]), 
         .D(n926[2]), .Z(n110535)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4038_2_lut_rep_477_4_lut_4_lut.init = 16'h332c;
    LUT4 i6054_2_lut_rep_638_4_lut_4_lut (.A(n110725), .B(n875[3]), .C(n876[1]), 
         .D(n110714), .Z(n110696)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6054_2_lut_rep_638_4_lut_4_lut.init = 16'h332c;
    LUT4 i13823_2_lut_rep_820_4_lut (.A(n831[1]), .B(n110907), .C(n836[1]), 
         .D(n110887), .Z(n110878)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13823_2_lut_rep_820_4_lut.init = 16'hf600;
    LUT4 i2895_3_lut_rep_504 (.A(n926[0]), .B(n110572), .C(n926[1]), .D(n926[2]), 
         .Z(n110562)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2895_3_lut_rep_504.init = 16'hffe0;
    LUT4 i2975_4_lut (.A(\lux[9] ), .B(bcd_code_31__N_1769), .C(bcd_code_31__N_1773), 
         .D(n110965), .Z(n5621)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2975_4_lut.init = 16'hfcec;
    LUT4 i4046_3_lut_rep_478_4_lut (.A(n926[0]), .B(n110572), .C(n926[1]), 
         .D(n926[2]), .Z(n110536)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4046_3_lut_rep_478_4_lut.init = 16'h998a;
    LUT4 i75676_4_lut_4_lut_4_lut (.A(n110506), .B(rst_n_c), .C(n110507), 
         .D(n110508), .Z(n14_adj_78)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75676_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i2955_4_lut (.A(\lux[8] ), .B(bcd_code_31__N_1845), .C(bcd_code_31__N_1849), 
         .D(n110952), .Z(n5502)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2955_4_lut.init = 16'hfcec;
    LUT4 i75574_4_lut (.A(n921[1]), .B(rst_n_c), .C(n5133), .D(n21062), 
         .Z(\lux_data[31] )) /* synthesis lut_function=(!(A ((C (D))+!B)+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75574_4_lut.init = 16'h4888;
    LUT4 i4816_2_lut_3_lut_3_lut_4_lut (.A(n110728), .B(bcd_code_31__N_1973), 
         .C(n888[1]), .D(n888[2]), .Z(n896[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4816_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i3995_2_lut_rep_468_4_lut_4_lut (.A(n110573), .B(n918[2]), .C(n918[1]), 
         .D(n928[0]), .Z(n110526)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i3995_2_lut_rep_468_4_lut_4_lut.init = 16'hff6c;
    LUT4 i4199_2_lut_4_lut_4_lut (.A(n919[0]), .B(n110575), .C(n919[1]), 
         .D(n919[2]), .Z(n928[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4199_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i4801_2_lut_rep_640_4_lut_4_lut (.A(n110728), .B(bcd_code_31__N_1973), 
         .C(n888[1]), .D(n888[2]), .Z(n110698)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4801_2_lut_rep_640_4_lut_4_lut.init = 16'h332c;
    LUT4 i4823_3_lut_4_lut_3_lut_4_lut (.A(n110728), .B(bcd_code_31__N_1973), 
         .C(n888[1]), .D(n888[2]), .Z(n896[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4823_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4221_3_lut_4_lut_3_lut_4_lut (.A(n919[0]), .B(n110575), .C(n919[1]), 
         .D(n919[2]), .Z(n928[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4221_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i3036_4_lut (.A(\lux[7] ), .B(bcd_code_31__N_1914), .C(bcd_code_31__N_1918), 
         .D(n110936), .Z(n5022)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3036_4_lut.init = 16'hfcec;
    LUT4 i4214_2_lut_3_lut_3_lut_4_lut (.A(n919[0]), .B(n110575), .C(n919[1]), 
         .D(n919[2]), .Z(n928[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4214_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4207_3_lut_4_lut (.A(n919[0]), .B(n110575), .C(n919[1]), .D(n919[2]), 
         .Z(n928[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4207_3_lut_4_lut.init = 16'h998a;
    LUT4 i4592_3_lut_4_lut (.A(n110607), .B(n5365), .C(n110576), .D(n110543), 
         .Z(n912[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4592_3_lut_4_lut.init = 16'h6966;
    LUT4 i1_4_lut_4_lut_adj_200 (.A(n793[3]), .B(bcd_code_31__N_850), .C(n111113), 
         .D(n111082), .Z(n32)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+!(D)))+!A !(B (C)))) */ ;
    defparam i1_4_lut_4_lut_adj_200.init = 16'h60e2;
    LUT4 i4809_3_lut_4_lut (.A(n110728), .B(bcd_code_31__N_1973), .C(n888[1]), 
         .D(n888[2]), .Z(n896[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4809_3_lut_4_lut.init = 16'h998a;
    LUT4 i4597_2_lut_3_lut (.A(n110607), .B(n5365), .C(n110576), .Z(n21200)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4597_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i4388_2_lut_rep_495_4_lut_4_lut (.A(n110577), .B(n910[3]), .C(n911[1]), 
         .D(n911[2]), .Z(n110553)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4388_2_lut_rep_495_4_lut_4_lut.init = 16'h332c;
    LUT4 i75737_3_lut_4_lut (.A(n110506), .B(rst_n_c), .C(n110508), .D(n110507), 
         .Z(n14_adj_79)) /* synthesis lut_function=(((C (D)+!C !(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75737_3_lut_4_lut.init = 16'hf77f;
    LUT4 i4403_2_lut_3_lut_3_lut_4_lut (.A(n110577), .B(n910[3]), .C(n911[1]), 
         .D(n911[2]), .Z(n920[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4403_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2980_4_lut (.A(\lux[6] ), .B(bcd_code_31__N_1974), .C(bcd_code_31__N_1978), 
         .D(n110921), .Z(n5660)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2980_4_lut.init = 16'hfcec;
    LUT4 bcd_code_31__N_1381_bdd_4_lut_4_lut (.A(bcd_code_31__N_1384), .B(n110749), 
         .C(n110806), .D(n110701), .Z(n110269)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B (C+!(D))+!B (D)))) */ ;
    defparam bcd_code_31__N_1381_bdd_4_lut_4_lut.init = 16'h73c6;
    LUT4 mux_23_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110508), 
         .B(rst_n_c), .C(n110507), .D(n110506), .Z(n14_adj_80)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_23_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3f77;
    LUT4 i4410_3_lut_rep_471_4_lut_3_lut_4_lut (.A(n110577), .B(n910[3]), 
         .C(n911[1]), .D(n911[2]), .Z(n110529)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4410_3_lut_rep_471_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i8252_3_lut_4_lut (.A(n110749), .B(bcd_code_31__N_1384), .C(n4_adj_2349), 
         .D(\bcd_code_31__N_1380[2] ), .Z(n6313)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(B (D)+!B !(C (D)+!C !(D))))) */ ;
    defparam i8252_3_lut_4_lut.init = 16'h6f90;
    LUT4 i2909_3_lut_rep_507 (.A(n110577), .B(n910[3]), .C(n911[1]), .D(n911[2]), 
         .Z(n110565)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2909_3_lut_rep_507.init = 16'hffe0;
    LUT4 i4396_3_lut_4_lut (.A(n110577), .B(n910[3]), .C(n911[1]), .D(n911[2]), 
         .Z(n920[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4396_3_lut_4_lut.init = 16'h998a;
    LUT4 i2933_4_lut (.A(\lux[5] ), .B(bcd_code_31__N_2025), .C(bcd_code_31__N_2029), 
         .D(n110902), .Z(n5260)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2933_4_lut.init = 16'hfcec;
    LUT4 i75679_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), 
         .C(n110480), .D(n110481), .Z(n7_adj_81)) /* synthesis lut_function=(!(A (B)+!A !((C+!(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75679_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7377;
    LUT4 i2934_4_lut (.A(\lux[4] ), .B(bcd_code_31__N_2067), .C(bcd_code_31__N_2071), 
         .D(n110884), .Z(n5292)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2934_4_lut.init = 16'hfcec;
    LUT4 i8202_2_lut_rep_612_4_lut_4_lut (.A(n110731), .B(n110730), .C(n870[1]), 
         .D(n5695), .Z(n110670)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i8202_2_lut_rep_612_4_lut_4_lut.init = 16'h936c;
    LUT4 i75667_3_lut_4_lut_4_lut_4_lut (.A(n110487), .B(rst_n_c), .C(n110481), 
         .D(n110480), .Z(n16584)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75667_3_lut_4_lut_4_lut_4_lut.init = 16'hffb7;
    LUT4 i75803_4_lut_4_lut (.A(n110508), .B(rst_n_c), .C(n83386), .D(n110488), 
         .Z(n83307)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75803_4_lut_4_lut.init = 16'h37bf;
    LUT4 i75388_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110508), .B(rst_n_c), 
         .C(n110507), .D(n110506), .Z(n14_adj_82)) /* synthesis lut_function=(!(A (B (C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75388_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h7f77;
    LUT4 i6062_3_lut_4_lut (.A(n868[3]), .B(n110732), .C(n875[3]), .D(n110704), 
         .Z(n884[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6062_3_lut_4_lut.init = 16'h6966;
    LUT4 i6067_2_lut_rep_657_3_lut (.A(n868[3]), .B(n110732), .C(n875[3]), 
         .Z(n110715)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6067_2_lut_rep_657_3_lut.init = 16'hf6f6;
    LUT4 i2916_4_lut (.A(\lux[3] ), .B(bcd_code_31__N_2100), .C(bcd_code_31__N_2104), 
         .D(n110868), .Z(n5181)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2916_4_lut.init = 16'hfcec;
    LUT4 i75733_3_lut_4_lut (.A(n110582), .B(rst_n_c), .C(n110567), .D(n110568), 
         .Z(n14_adj_83)) /* synthesis lut_function=(((C (D)+!C !(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75733_3_lut_4_lut.init = 16'hf77f;
    LUT4 i75430_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), 
         .C(n110568), .D(n110567), .Z(n14_adj_84)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75430_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 i75708_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), 
         .C(n110568), .D(n110567), .Z(n14_adj_85)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75708_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 i75670_3_lut_4_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), .C(n110568), 
         .D(n110567), .Z(n16558)) /* synthesis lut_function=(A ((C+(D))+!B)+!A ((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75670_3_lut_4_lut_4_lut_4_lut.init = 16'hfbf7;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_201 (.A(n110582), .B(rst_n_c), 
         .C(n110568), .D(n110567), .Z(n107664)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_201.init = 16'hffbf;
    LUT4 i75675_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), 
         .C(n110506), .D(n110508), .Z(n7_adj_86)) /* synthesis lut_function=(!(A (B (C))+!A (B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75675_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'h3b3f;
    LUT4 i75481_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), 
         .C(n110567), .D(n110568), .Z(n7_adj_87)) /* synthesis lut_function=(!(A (B)+!A !(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75481_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7737;
    LUT4 i5796_3_lut_4_lut_3_lut_4_lut (.A(n880[3]), .B(n110739), .C(n881[1]), 
         .D(n881[2]), .Z(n889[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i5796_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5774_2_lut_rep_650_4_lut_4_lut (.A(n880[3]), .B(n110739), .C(n881[1]), 
         .D(n881[2]), .Z(n110708)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5774_2_lut_rep_650_4_lut_4_lut.init = 16'h554a;
    LUT4 i5789_2_lut_3_lut_3_lut_4_lut (.A(n880[3]), .B(n110739), .C(n881[1]), 
         .D(n881[2]), .Z(n889[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i5789_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i5782_3_lut_4_lut (.A(n880[3]), .B(n110739), .C(n881[1]), .D(n881[2]), 
         .Z(n889[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i5782_3_lut_4_lut.init = 16'h998c;
    LUT4 i2891_3_lut_rep_664_4_lut (.A(bcd_code_31__N_795), .B(n110740), 
         .C(n870[1]), .D(n110731), .Z(n110722)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2891_3_lut_rep_664_4_lut.init = 16'hf666;
    LUT4 i3727_2_lut_rep_644_3_lut_3_lut_4_lut (.A(bcd_code_31__N_795), .B(n110740), 
         .C(n870[1]), .D(n110731), .Z(n110702)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3727_2_lut_rep_644_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i3734_3_lut_rep_643_4_lut_3_lut_4_lut (.A(bcd_code_31__N_795), .B(n110740), 
         .C(n870[1]), .D(n110731), .Z(n110701)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3734_3_lut_rep_643_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i13815_2_lut_rep_665_4_lut (.A(bcd_code_31__N_795), .B(n110740), 
         .C(n870[1]), .D(n110731), .Z(n110723)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i13815_2_lut_rep_665_4_lut.init = 16'hf600;
    LUT4 i3712_2_lut_rep_655_4_lut_4_lut (.A(n110741), .B(n869[3]), .C(n870[1]), 
         .D(n110730), .Z(n110713)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3712_2_lut_rep_655_4_lut_4_lut.init = 16'h332c;
    LUT4 i6039_2_lut_rep_645_4_lut_4_lut (.A(n110743), .B(n110742), .C(n869[1]), 
         .D(n110713), .Z(n110703)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i6039_2_lut_rep_645_4_lut_4_lut.init = 16'hff6c;
    LUT4 i6153_2_lut_3_lut_3_lut_4_lut (.A(n868[1]), .B(n110744), .C(n875[1]), 
         .D(n110735), .Z(n883[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6153_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2990_3_lut_rep_668_4_lut (.A(n868[1]), .B(n110744), .C(n875[1]), 
         .D(n110735), .Z(n110726)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2990_3_lut_rep_668_4_lut.init = 16'hf666;
    LUT4 i6160_3_lut_4_lut_3_lut_4_lut (.A(n868[1]), .B(n110744), .C(n875[1]), 
         .D(n110735), .Z(n883[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6160_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6138_2_lut_4_lut_4_lut (.A(n110745), .B(n874[3]), .C(n875[1]), 
         .D(n110734), .Z(n883[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6138_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i6181_2_lut_3_lut_3_lut_4_lut (.A(n110746), .B(n873[3]), .C(n874[1]), 
         .D(n874[2]), .Z(n882[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6181_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i6188_3_lut_rep_648_4_lut_3_lut_4_lut (.A(n110746), .B(n873[3]), 
         .C(n874[1]), .D(n874[2]), .Z(n110706)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6188_3_lut_rep_648_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i6166_2_lut_rep_661_4_lut_4_lut (.A(n110746), .B(n873[3]), .C(n874[1]), 
         .D(n874[2]), .Z(n110719)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6166_2_lut_rep_661_4_lut_4_lut.init = 16'h332c;
    LUT4 i6174_3_lut_4_lut (.A(n110746), .B(n873[3]), .C(n874[1]), .D(n874[2]), 
         .Z(n882[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6174_3_lut_4_lut.init = 16'h998a;
    LUT4 i75478_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), 
         .C(n110567), .D(n110568), .Z(n14_adj_88)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75478_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hff7f;
    LUT4 i5488_3_lut_4_lut (.A(n5537), .B(n110755), .C(bcd_code_31__N_795), 
         .D(bcd_code_31__N_1257), .Z(bcd_code_31__N_1384)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5488_3_lut_4_lut.init = 16'h7f80;
    LUT4 i3720_3_lut_4_lut (.A(n110762), .B(n5537), .C(n869[3]), .D(n110722), 
         .Z(n877[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3720_3_lut_4_lut.init = 16'h6966;
    LUT4 i3725_2_lut_rep_673_3_lut (.A(n110762), .B(n5537), .C(n869[3]), 
         .Z(n110731)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3725_2_lut_rep_673_3_lut.init = 16'hf6f6;
    LUT4 i2926_3_lut_rep_674_4_lut (.A(n862[1]), .B(n110750), .C(n869[1]), 
         .D(n110743), .Z(n110732)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2926_3_lut_rep_674_4_lut.init = 16'hf666;
    LUT4 i4844_2_lut_rep_656_3_lut_3_lut_4_lut (.A(n862[1]), .B(n110750), 
         .C(n869[1]), .D(n110743), .Z(n110714)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4844_2_lut_rep_656_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4851_3_lut_rep_654_4_lut_3_lut_4_lut (.A(n862[1]), .B(n110750), 
         .C(n869[1]), .D(n110743), .Z(n110712)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4851_3_lut_rep_654_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i13727_2_lut_rep_675_4_lut (.A(n862[1]), .B(n110750), .C(n869[1]), 
         .D(n110743), .Z(n110733)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13727_2_lut_rep_675_4_lut.init = 16'hf600;
    LUT4 i4829_2_lut_rep_667_4_lut_4_lut (.A(n110751), .B(n868[3]), .C(n869[1]), 
         .D(n110742), .Z(n110725)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4829_2_lut_rep_667_4_lut_4_lut.init = 16'h332c;
    LUT4 mux_31_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110582), 
         .B(rst_n_c), .C(n110568), .D(n110567), .Z(n7_adj_89)) /* synthesis lut_function=(!(A ((C (D)+!C !(D))+!B)+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_31_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h4cc0;
    LUT4 i6146_3_lut_4_lut (.A(n110767), .B(n110752), .C(n874[3]), .D(n110726), 
         .Z(n883[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6146_3_lut_4_lut.init = 16'h6966;
    LUT4 i6151_2_lut_rep_677_3_lut (.A(n110767), .B(n110752), .C(n874[3]), 
         .Z(n110735)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6151_2_lut_rep_677_3_lut.init = 16'hf6f6;
    LUT4 i2_4_lut_then_4_lut (.A(bcd_code_31__N_797), .B(n6268), .C(n110788), 
         .D(n5653), .Z(n111274)) /* synthesis lut_function=(A (B (C (D)))+!A !(B+(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2_4_lut_then_4_lut.init = 16'h8011;
    LUT4 i75482_4_lut_4_lut_4_lut (.A(n110582), .B(rst_n_c), .C(n110568), 
         .D(n110567), .Z(n14_adj_90)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75482_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 mux_31_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110582), 
         .B(rst_n_c), .C(n110568), .D(n110567), .Z(n14_adj_91)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_31_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i75549_2_lut_rep_499_4_lut (.A(n110600), .B(n110595), .C(n923[3]), 
         .D(rst_n_c), .Z(n110557)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i75549_2_lut_rep_499_4_lut.init = 16'ha600;
    LUT4 i75548_2_lut_rep_498_3_lut (.A(n923[3]), .B(n110595), .C(rst_n_c), 
         .Z(n110556)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i75548_2_lut_rep_498_3_lut.init = 16'h6060;
    LUT4 i10508_3_lut_rep_500_4_lut (.A(n923[3]), .B(n110595), .C(rst_n_c), 
         .D(n110582), .Z(n110558)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i10508_3_lut_rep_500_4_lut.init = 16'h9060;
    LUT4 i75773_2_lut_3_lut (.A(n923[3]), .B(n110595), .C(n110582), .Z(n83401)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i75773_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i75771_2_lut_rep_497_3_lut_4_lut (.A(n923[3]), .B(n110595), .C(rst_n_c), 
         .D(n110582), .Z(n110555)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i75771_2_lut_rep_497_3_lut_4_lut.init = 16'h6000;
    LUT4 i4088_3_lut_rep_476_4_lut_3_lut_4_lut (.A(n110584), .B(n924[3]), 
         .C(n925[1]), .D(n925[2]), .Z(n110534)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4088_3_lut_rep_476_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4066_2_lut_rep_487_4_lut_4_lut (.A(n110584), .B(n924[3]), .C(n925[1]), 
         .D(n925[2]), .Z(n110545)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4066_2_lut_rep_487_4_lut_4_lut.init = 16'h332c;
    LUT4 i2896_3_lut_rep_513 (.A(n110584), .B(n924[3]), .C(n925[1]), .D(n925[2]), 
         .Z(n110571)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2896_3_lut_rep_513.init = 16'hffe0;
    LUT4 i4074_3_lut_rep_489_4_lut (.A(n110584), .B(n924[3]), .C(n925[1]), 
         .D(n925[2]), .Z(n110547)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4074_3_lut_rep_489_4_lut.init = 16'h998a;
    LUT4 i4249_3_lut_rep_482_4_lut_3_lut_4_lut (.A(n110587), .B(n917[3]), 
         .C(n918[1]), .D(n918[2]), .Z(n110540)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4249_3_lut_rep_482_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4242_2_lut_3_lut_3_lut_4_lut (.A(n110587), .B(n917[3]), .C(n918[1]), 
         .D(n918[2]), .Z(n927[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4242_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4227_2_lut_rep_492_4_lut_4_lut (.A(n110587), .B(n917[3]), .C(n918[1]), 
         .D(n918[2]), .Z(n110550)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4227_2_lut_rep_492_4_lut_4_lut.init = 16'h332c;
    LUT4 i5929_2_lut_3_lut_3_lut_4_lut (.A(bcd_code_31__N_1913), .B(n110753), 
         .C(n880[1]), .D(n880[2]), .Z(n888[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i5929_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 mux_23_Mux_6_i7_3_lut_3_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), 
         .C(n110495), .D(n110494), .Z(n7_adj_92)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_23_Mux_6_i7_3_lut_3_lut_4_lut_4_lut.init = 16'h58f8;
    LUT4 i75684_4_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), .C(n110506), 
         .D(n110508), .Z(n16471)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75684_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i2902_3_lut_rep_516 (.A(n110587), .B(n917[3]), .C(n918[1]), .D(n918[2]), 
         .Z(n110574)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2902_3_lut_rep_516.init = 16'hffe0;
    LUT4 i4235_3_lut_4_lut (.A(n110587), .B(n917[3]), .C(n918[1]), .D(n918[2]), 
         .Z(n927[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4235_3_lut_4_lut.init = 16'h998a;
    LUT4 i5914_2_lut_rep_670_4_lut_4_lut (.A(bcd_code_31__N_1913), .B(n110753), 
         .C(n880[1]), .D(n880[2]), .Z(n110728)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5914_2_lut_rep_670_4_lut_4_lut.init = 16'h554a;
    LUT4 i5936_3_lut_4_lut_3_lut_4_lut (.A(bcd_code_31__N_1913), .B(n110753), 
         .C(n880[1]), .D(n880[2]), .Z(n888[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i5936_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2_4_lut_else_4_lut (.A(bcd_code_31__N_797), .B(n6264), .C(n110788), 
         .D(n5653), .Z(n111273)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B+(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2_4_lut_else_4_lut.init = 16'h7fee;
    LUT4 i5922_3_lut_4_lut (.A(bcd_code_31__N_1913), .B(n110753), .C(n880[1]), 
         .D(n880[2]), .Z(n888[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i5922_3_lut_4_lut.init = 16'h998c;
    LUT4 i4401_2_lut_rep_506_3_lut (.A(n901[3]), .B(n110598), .C(n910[3]), 
         .Z(n110564)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4401_2_lut_rep_506_3_lut.init = 16'hf6f6;
    LUT4 i75666_3_lut_4_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), .C(n110506), 
         .D(n110508), .Z(n16601)) /* synthesis lut_function=(A+((C (D)+!C !(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75666_3_lut_4_lut_4_lut_4_lut.init = 16'hfbbf;
    LUT4 i75793_4_lut_4_lut (.A(n110592), .B(rst_n_c), .C(n83391), .D(n110579), 
         .Z(n83295)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75793_4_lut_4_lut.init = 16'h37bf;
    LUT4 i75639_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), 
         .C(n110506), .D(n110508), .Z(n14_adj_93)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75639_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 i75651_4_lut_4_lut_4_lut (.A(n110515), .B(rst_n_c), .C(n110524), 
         .D(n110514), .Z(n16738)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75651_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i4837_3_lut_4_lut (.A(n861[3]), .B(n110756), .C(n868[3]), .D(n110732), 
         .Z(n876[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4837_3_lut_4_lut.init = 16'h6966;
    LUT4 i4842_2_lut_rep_685_3_lut (.A(n861[3]), .B(n110756), .C(n868[3]), 
         .Z(n110743)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4842_2_lut_rep_685_3_lut.init = 16'hf6f6;
    LUT4 i75696_4_lut_4_lut_4_lut (.A(n110591), .B(rst_n_c), .C(bcd_code_31__N_2138), 
         .D(n110592), .Z(n16428)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75696_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i75813_4_lut_4_lut (.A(n110514), .B(rst_n_c), .C(n83382), .D(n110502), 
         .Z(n83319)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75813_4_lut_4_lut.init = 16'h37bf;
    LUT4 i75550_3_lut_4_lut_4_lut (.A(n110594), .B(n924[2]), .C(n924[1]), 
         .D(rst_n_c), .Z(\lux_data[7] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75550_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i75551_2_lut_rep_488_4_lut_4_lut (.A(n110594), .B(n924[2]), .C(n924[1]), 
         .D(rst_n_c), .Z(n110546)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75551_2_lut_rep_488_4_lut_4_lut.init = 16'h6c00;
    LUT4 i4079_2_lut_rep_512_3_lut (.A(n915[3]), .B(n110602), .C(n924[3]), 
         .Z(n110570)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4079_2_lut_rep_512_3_lut.init = 16'hf6f6;
    LUT4 i4240_2_lut_rep_515_3_lut (.A(n908[3]), .B(n110605), .C(n917[3]), 
         .Z(n110573)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4240_2_lut_rep_515_3_lut.init = 16'hf6f6;
    LUT4 i10504_3_lut_rep_435_4_lut (.A(n110540), .B(n110527), .C(rst_n_c), 
         .D(n110506), .Z(n110493)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i10504_3_lut_rep_435_4_lut.init = 16'h9060;
    LUT4 i10500_3_lut_rep_520_4_lut (.A(n922[3]), .B(n110612), .C(rst_n_c), 
         .D(bcd_code_31__N_2138), .Z(n110578)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i10500_3_lut_rep_520_4_lut.init = 16'h9060;
    LUT4 i75785_2_lut_rep_430_3_lut_4_lut (.A(n110540), .B(n110527), .C(rst_n_c), 
         .D(n110506), .Z(n110488)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i75785_2_lut_rep_430_3_lut_4_lut.init = 16'h6000;
    LUT4 i75564_2_lut_rep_438_3_lut (.A(n110540), .B(n110527), .C(rst_n_c), 
         .Z(n110496)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i75564_2_lut_rep_438_3_lut.init = 16'h6060;
    LUT4 i75791_2_lut_3_lut (.A(n922[3]), .B(n110612), .C(bcd_code_31__N_2138), 
         .Z(n83391)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i75791_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i75544_2_lut_rep_523_3_lut (.A(n922[3]), .B(n110612), .C(rst_n_c), 
         .Z(n110581)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i75544_2_lut_rep_523_3_lut.init = 16'h6060;
    LUT4 i6517_2_lut_3_lut_3_lut_4_lut (.A(n872[3]), .B(n110761), .C(n873[1]), 
         .D(n873[2]), .Z(n881[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i6517_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i75565_2_lut_rep_437_4_lut (.A(n928[0]), .B(n110527), .C(n110540), 
         .D(rst_n_c), .Z(n110495)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i75565_2_lut_rep_437_4_lut.init = 16'ha600;
    LUT4 i75735_3_lut_4_lut_4_lut (.A(n110621), .B(n110612), .C(n922[3]), 
         .D(n110817), .Z(n14_adj_94)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A !(B+!(C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i75735_3_lut_4_lut_4_lut.init = 16'h65ff;
    LUT4 i75545_2_lut_rep_522_4_lut (.A(n110621), .B(n110612), .C(n922[3]), 
         .D(rst_n_c), .Z(n110580)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i75545_2_lut_rep_522_4_lut.init = 16'ha600;
    LUT4 i75674_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110507), .B(rst_n_c), 
         .C(n110506), .D(n110508), .Z(n14_adj_95)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75674_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hbfff;
    LUT4 i4116_3_lut_rep_501_4_lut_3_lut_4_lut (.A(n110600), .B(n923[3]), 
         .C(n924[1]), .D(n924[2]), .Z(n110559)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4116_3_lut_rep_501_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i3976_3_lut_rep_429_4_lut_3_lut_4_lut (.A(n110518), .B(n928[3]), 
         .C(n929[1]), .D(n929[2]), .Z(n110487)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3976_3_lut_rep_429_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4094_2_lut_rep_510_4_lut_4_lut (.A(n110600), .B(n923[3]), .C(n924[1]), 
         .D(n924[2]), .Z(n110568)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4094_2_lut_rep_510_4_lut_4_lut.init = 16'h332c;
    LUT4 i2897_3_lut_rep_537 (.A(n110600), .B(n923[3]), .C(n924[1]), .D(n924[2]), 
         .Z(n110595)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2897_3_lut_rep_537.init = 16'hffe0;
    LUT4 i4102_3_lut_rep_509_4_lut (.A(n110600), .B(n923[3]), .C(n924[1]), 
         .D(n924[2]), .Z(n110567)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4102_3_lut_rep_509_4_lut.init = 16'h998a;
    LUT4 i3954_2_lut_rep_433_4_lut_4_lut (.A(n110518), .B(n928[3]), .C(n929[1]), 
         .D(n929[2]), .Z(n110491)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3954_2_lut_rep_433_4_lut_4_lut.init = 16'h332c;
    LUT4 i2892_3_lut_rep_453 (.A(n110518), .B(n928[3]), .C(n929[1]), .D(n929[2]), 
         .Z(n110511)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2892_3_lut_rep_453.init = 16'hffe0;
    LUT4 i3962_3_lut_rep_432_4_lut (.A(n110518), .B(n928[3]), .C(n929[1]), 
         .D(n929[2]), .Z(n110490)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3962_3_lut_rep_432_4_lut.init = 16'h998a;
    LUT4 i4051_2_lut_rep_503_4_lut_4_lut (.A(n110601), .B(n916[2]), .C(n916[1]), 
         .D(n926[0]), .Z(n110561)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i4051_2_lut_rep_503_4_lut_4_lut.init = 16'hff6c;
    LUT4 i6502_2_lut_rep_681_4_lut_4_lut (.A(n872[3]), .B(n110761), .C(n873[1]), 
         .D(n873[2]), .Z(n110739)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6502_2_lut_rep_681_4_lut_4_lut.init = 16'h554a;
    LUT4 i4255_2_lut_4_lut_4_lut (.A(n917[0]), .B(n110603), .C(n917[1]), 
         .D(n917[2]), .Z(n926[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4255_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i6524_3_lut_4_lut_3_lut_4_lut (.A(n872[3]), .B(n110761), .C(n873[1]), 
         .D(n873[2]), .Z(n881[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i6524_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i6510_3_lut_4_lut (.A(n872[3]), .B(n110761), .C(n873[1]), .D(n873[2]), 
         .Z(n881[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i6510_3_lut_4_lut.init = 16'h998c;
    LUT4 i2959_3_lut_4_lut (.A(n110763), .B(n110762), .C(bcd_code_31__N_795), 
         .D(bcd_code_31__N_1257), .Z(n5537)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2959_3_lut_4_lut.init = 16'hffe0;
    LUT4 i5481_2_lut_rep_672_3_lut_4_lut (.A(n110763), .B(n110762), .C(bcd_code_31__N_795), 
         .D(n5537), .Z(n110730)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5481_2_lut_rep_672_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i13833_2_lut_rep_686_3_lut_4_lut (.A(n861[1]), .B(n110766), .C(n868[1]), 
         .D(n110758), .Z(n110744)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13833_2_lut_rep_686_3_lut_4_lut.init = 16'hf600;
    LUT4 i2932_3_lut_rep_694_4_lut (.A(n861[1]), .B(n110766), .C(n868[1]), 
         .D(n110758), .Z(n110752)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2932_3_lut_rep_694_4_lut.init = 16'hf666;
    LUT4 i4984_2_lut_rep_676_3_lut_3_lut_4_lut (.A(n861[1]), .B(n110766), 
         .C(n868[1]), .D(n110758), .Z(n110734)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4984_2_lut_rep_676_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4991_3_lut_4_lut_3_lut_4_lut (.A(n861[1]), .B(n110766), .C(n868[1]), 
         .D(n110758), .Z(n875[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4991_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4969_2_lut_rep_687_4_lut_4_lut (.A(n110767), .B(n110768), .C(n868[1]), 
         .D(n110757), .Z(n110745)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4969_2_lut_rep_687_4_lut_4_lut.init = 16'h554a;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_202 (.A(n110507), .B(rst_n_c), 
         .C(n110506), .D(n110508), .Z(n107668)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_202.init = 16'hfff7;
    LUT4 i4270_2_lut_3_lut_3_lut_4_lut (.A(n917[0]), .B(n110603), .C(n917[1]), 
         .D(n917[2]), .Z(n926[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4270_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2907_4_lut (.A(\lux[2] ), .B(bcd_code_31__N_2124), .C(bcd_code_31__N_2128), 
         .D(n110850), .Z(n5141)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2907_4_lut.init = 16'hfcec;
    LUT4 i4277_3_lut_4_lut_3_lut_4_lut (.A(n917[0]), .B(n110603), .C(n917[1]), 
         .D(n917[2]), .Z(n926[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4277_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4263_3_lut_4_lut (.A(n917[0]), .B(n110603), .C(n917[1]), .D(n917[2]), 
         .Z(n926[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4263_3_lut_4_lut.init = 16'h998a;
    LUT4 i4416_2_lut_4_lut_4_lut (.A(n910[0]), .B(n110606), .C(n910[1]), 
         .D(n910[2]), .Z(n919[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4416_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i15_4_lut (.A(n922[2]), .B(n922[1]), .C(n922[0]), .D(\lux[1] ), 
         .Z(bcd_code_31__N_2138)) /* synthesis lut_function=(!(A (B (C+(D)))+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(39[4] 40[49])
    defparam i15_4_lut.init = 16'h666a;
    LUT4 i4438_3_lut_4_lut_3_lut_4_lut (.A(n910[0]), .B(n110606), .C(n910[1]), 
         .D(n910[2]), .Z(n919[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4438_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5474_3_lut_4_lut (.A(n110788), .B(n5653), .C(n110762), .D(n5537), 
         .Z(n870[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5474_3_lut_4_lut.init = 16'h6966;
    LUT4 i75657_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), 
         .C(n110514), .D(n110515), .Z(n14_adj_96)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75657_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hff7f;
    LUT4 i13753_2_lut_rep_682_3_lut_4_lut (.A(n110788), .B(n5653), .C(n5537), 
         .D(n110762), .Z(n110740)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (B (C)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i13753_2_lut_rep_682_3_lut_4_lut.init = 16'hf060;
    LUT4 i4431_2_lut_3_lut_3_lut_4_lut (.A(n910[0]), .B(n110606), .C(n910[1]), 
         .D(n910[2]), .Z(n919[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4431_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4424_3_lut_4_lut (.A(n910[0]), .B(n110606), .C(n910[1]), .D(n910[2]), 
         .Z(n919[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4424_3_lut_4_lut.init = 16'h998a;
    LUT4 i13797_2_lut_3_lut (.A(n878[0]), .B(n110607), .C(n5365), .Z(n21133)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i13797_2_lut_3_lut.init = 16'he0e0;
    LUT4 i75655_4_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), .C(n110515), 
         .D(n110514), .Z(n14_adj_97)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75655_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i13749_2_lut_rep_692_3_lut_4_lut (.A(n855[1]), .B(n110781), .C(n862[1]), 
         .D(n110765), .Z(n110750)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13749_2_lut_rep_692_3_lut_4_lut.init = 16'hf600;
    LUT4 i2960_3_lut_rep_698_4_lut (.A(n855[1]), .B(n110781), .C(n862[1]), 
         .D(n110765), .Z(n110756)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2960_3_lut_rep_698_4_lut.init = 16'hf666;
    LUT4 i75477_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), 
         .C(n110515), .D(n110514), .Z(n14_adj_98)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75477_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 i5509_2_lut_rep_684_3_lut_3_lut_4_lut (.A(n855[1]), .B(n110781), 
         .C(n862[1]), .D(n110765), .Z(n110742)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5509_2_lut_rep_684_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5516_3_lut_4_lut_3_lut_4_lut (.A(n855[1]), .B(n110781), .C(n862[1]), 
         .D(n110765), .Z(n869[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5516_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i75739_3_lut_4_lut (.A(n110524), .B(rst_n_c), .C(n110514), .D(n110515), 
         .Z(n14_adj_99)) /* synthesis lut_function=(((C (D)+!C !(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75739_3_lut_4_lut.init = 16'hf77f;
    LUT4 i5494_2_lut_rep_693_4_lut_4_lut (.A(n110774), .B(n861[3]), .C(n862[1]), 
         .D(n110764), .Z(n110751)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5494_2_lut_rep_693_4_lut_4_lut.init = 16'h332c;
    LUT4 mux_25_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110524), 
         .B(rst_n_c), .C(n110515), .D(n110514), .Z(n7_adj_100)) /* synthesis lut_function=(!(A ((C (D)+!C !(D))+!B)+!A !(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_25_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h4cc0;
    LUT4 i3013_4_lut (.A(\lux[20] ), .B(bcd_code_31__N_1030), .C(bcd_code_31__N_1034), 
         .D(n111081), .Z(n5916)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3013_4_lut.init = 16'hfcec;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_203 (.A(n110524), .B(rst_n_c), 
         .C(n110515), .D(n110514), .Z(n107675)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_203.init = 16'hffbf;
    LUT4 i75445_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), 
         .C(n110515), .D(n110514), .Z(n14_adj_101)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75445_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 i75656_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), 
         .C(n110514), .D(n110515), .Z(n7_adj_102)) /* synthesis lut_function=(!(A (B)+!A !(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75656_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7737;
    LUT4 mux_25_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110524), 
         .B(rst_n_c), .C(n110515), .D(n110514), .Z(n14_adj_103)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_25_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i75485_3_lut_4_lut_4_lut_4_lut (.A(n110524), .B(rst_n_c), .C(n110515), 
         .D(n110514), .Z(n16300)) /* synthesis lut_function=(A ((C+(D))+!B)+!A ((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75485_3_lut_4_lut_4_lut_4_lut.init = 16'hfbf7;
    LUT4 i75561_2_lut_rep_446_4_lut (.A(n110550), .B(n110539), .C(n926[3]), 
         .D(rst_n_c), .Z(n110504)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i75561_2_lut_rep_446_4_lut.init = 16'ha600;
    LUT4 i4977_3_lut_4_lut (.A(n110792), .B(n110775), .C(n110767), .D(n110752), 
         .Z(n875[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4977_3_lut_4_lut.init = 16'h6966;
    LUT4 i75560_2_lut_rep_445_3_lut (.A(n926[3]), .B(n110539), .C(rst_n_c), 
         .Z(n110503)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i75560_2_lut_rep_445_3_lut.init = 16'h6060;
    LUT4 i2936_3_lut_rep_701_4_lut (.A(n860[1]), .B(n110785), .C(n867[1]), 
         .D(n110770), .Z(n110759)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2936_3_lut_rep_701_4_lut.init = 16'hf666;
    LUT4 i75765_2_lut_rep_444_3_lut_4_lut (.A(n926[3]), .B(n110539), .C(rst_n_c), 
         .D(n110524), .Z(n110502)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i75765_2_lut_rep_444_3_lut_4_lut.init = 16'h6000;
    LUT4 i75546_3_lut_4_lut_4_lut (.A(n110611), .B(n923[2]), .C(n923[1]), 
         .D(rst_n_c), .Z(\lux_data[3] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75546_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i10510_3_lut_rep_447_4_lut (.A(n926[3]), .B(n110539), .C(rst_n_c), 
         .D(n110524), .Z(n110505)) /* synthesis lut_function=(A (B (C (D))+!B !((D)+!C))+!A !(B ((D)+!C)+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i10510_3_lut_rep_447_4_lut.init = 16'h9060;
    LUT4 i75547_2_lut_rep_508_4_lut_4_lut (.A(n110611), .B(n923[2]), .C(n923[1]), 
         .D(rst_n_c), .Z(n110566)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75547_2_lut_rep_508_4_lut_4_lut.init = 16'h6c00;
    LUT4 i5040_2_lut_3_lut_3_lut_4_lut (.A(n860[1]), .B(n110785), .C(n867[1]), 
         .D(n110770), .Z(n874[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5040_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5047_3_lut_4_lut_3_lut_4_lut (.A(n860[1]), .B(n110785), .C(n867[1]), 
         .D(n110770), .Z(n874[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5047_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5025_2_lut_rep_688_4_lut_4_lut (.A(n866[3]), .B(n110777), .C(n867[1]), 
         .D(n110769), .Z(n110746)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5025_2_lut_rep_688_4_lut_4_lut.init = 16'h554a;
    LUT4 i75809_2_lut_3_lut (.A(n926[3]), .B(n110539), .C(n110524), .Z(n83382)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i75809_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i3022_4_lut (.A(\lux[21] ), .B(bcd_code_31__N_988), .C(bcd_code_31__N_992), 
         .D(n111089), .Z(n6021)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3022_4_lut.init = 16'hfcec;
    LUT4 i75566_3_lut_4_lut_4_lut (.A(n110526), .B(n928[2]), .C(n928[1]), 
         .D(rst_n_c), .Z(\lux_data[23] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75566_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i75567_2_lut_rep_431_4_lut_4_lut (.A(n110526), .B(n928[2]), .C(n928[1]), 
         .D(rst_n_c), .Z(n110489)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75567_2_lut_rep_431_4_lut_4_lut.init = 16'h6c00;
    LUT4 i4107_2_lut_rep_536_3_lut (.A(n914[3]), .B(n110622), .C(n923[3]), 
         .Z(n110594)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4107_2_lut_rep_536_3_lut.init = 16'hf6f6;
    LUT4 i3967_2_lut_rep_452_3_lut (.A(n919[3]), .B(n110542), .C(n928[3]), 
         .Z(n110510)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3967_2_lut_rep_452_3_lut.init = 16'hf6f6;
    LUT4 i6720_3_lut_4_lut_3_lut_4_lut (.A(bcd_code_31__N_1844), .B(n110779), 
         .C(n872[1]), .D(n872[2]), .Z(n880[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i6720_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4380_2_lut_3_lut (.A(n110576), .B(n110543), .C(n110529), .Z(n21022)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4380_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i4375_3_lut_4_lut (.A(n110576), .B(n110543), .C(n110529), .D(n110500), 
         .Z(n921[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4375_3_lut_4_lut.init = 16'h6966;
    LUT4 i6698_2_lut_rep_695_4_lut_4_lut (.A(bcd_code_31__N_1844), .B(n110779), 
         .C(n872[1]), .D(n872[2]), .Z(n110753)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6698_2_lut_rep_695_4_lut_4_lut.init = 16'h554a;
    LUT4 i6713_2_lut_3_lut_3_lut_4_lut (.A(bcd_code_31__N_1844), .B(n110779), 
         .C(n872[1]), .D(n872[2]), .Z(n880[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i6713_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i6706_3_lut_4_lut (.A(bcd_code_31__N_1844), .B(n110779), .C(n872[1]), 
         .D(n872[2]), .Z(n880[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i6706_3_lut_4_lut.init = 16'h998c;
    LUT4 i5502_3_lut_4_lut (.A(n854[3]), .B(n110780), .C(n861[3]), .D(n110756), 
         .Z(n869[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5502_3_lut_4_lut.init = 16'h6966;
    LUT4 i5507_2_lut_rep_707_3_lut (.A(n854[3]), .B(n110780), .C(n861[3]), 
         .Z(n110765)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5507_2_lut_rep_707_3_lut.init = 16'hf6f6;
    LUT4 i3244_2_lut_rep_712_3_lut (.A(n859[3]), .B(n110784), .C(n866[3]), 
         .Z(n110770)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3244_2_lut_rep_712_3_lut.init = 16'hf6f6;
    LUT4 i5033_3_lut_4_lut (.A(n859[3]), .B(n110784), .C(n866[3]), .D(n110759), 
         .Z(n874[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5033_3_lut_4_lut.init = 16'h6966;
    LUT4 i5236_2_lut_3_lut_3_lut_4_lut (.A(n110786), .B(n865[3]), .C(n866[1]), 
         .D(n866[2]), .Z(n873[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5236_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i5243_3_lut_4_lut_3_lut_4_lut (.A(n110786), .B(n865[3]), .C(n866[1]), 
         .D(n866[2]), .Z(n873[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5243_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5221_2_lut_rep_703_4_lut_4_lut (.A(n110786), .B(n865[3]), .C(n866[1]), 
         .D(n866[2]), .Z(n110761)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5221_2_lut_rep_703_4_lut_4_lut.init = 16'h332c;
    LUT4 i2984_4_lut_then_4_lut (.A(n110749), .B(n6295), .C(n110701), 
         .D(bcd_code_31__N_1384), .Z(n111277)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A !(B ((D)+!C)+!B (D))) */ ;
    defparam i2984_4_lut_then_4_lut.init = 16'ha073;
    LUT4 i5229_3_lut_4_lut (.A(n110786), .B(n865[3]), .C(n866[1]), .D(n866[2]), 
         .Z(n873[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5229_3_lut_4_lut.init = 16'h998a;
    LUT4 i5479_2_lut_rep_697_4_lut_4_lut (.A(n110790), .B(n110789), .C(n855[1]), 
         .D(n110763), .Z(n110755)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i5479_2_lut_rep_697_4_lut_4_lut.init = 16'hff6c;
    LUT4 i5466_2_lut_rep_683_4_lut_4_lut (.A(n110790), .B(n110789), .C(n855[1]), 
         .D(n5537), .Z(n110741)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i5466_2_lut_rep_683_4_lut_4_lut.init = 16'h936c;
    LUT4 i13729_2_lut_rep_708_3_lut_4_lut (.A(n854[1]), .B(n110791), .C(n861[1]), 
         .D(n110783), .Z(n110766)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13729_2_lut_rep_708_3_lut_4_lut.init = 16'hf600;
    LUT4 i5600_3_lut_4_lut_3_lut_4_lut (.A(n854[1]), .B(n110791), .C(n861[1]), 
         .D(n110783), .Z(n868[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5600_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2963_3_lut_rep_717_4_lut (.A(n854[1]), .B(n110791), .C(n861[1]), 
         .D(n110783), .Z(n110775)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2963_3_lut_rep_717_4_lut.init = 16'hf666;
    LUT4 i5593_2_lut_rep_699_3_lut_3_lut_4_lut (.A(n854[1]), .B(n110791), 
         .C(n861[1]), .D(n110783), .Z(n110757)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5593_2_lut_rep_699_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5578_2_lut_rep_710_4_lut_4_lut (.A(n110793), .B(n110792), .C(n861[1]), 
         .D(n110782), .Z(n110768)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5578_2_lut_rep_710_4_lut_4_lut.init = 16'h332c;
    LUT4 i3242_2_lut_rep_700_4_lut_4_lut (.A(n110795), .B(n110794), .C(n860[1]), 
         .D(n110768), .Z(n110758)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i3242_2_lut_rep_700_4_lut_4_lut.init = 16'hff6c;
    LUT4 i13808_2_lut_rep_723_4_lut (.A(n849[1]), .B(n110809), .C(n855[1]), 
         .D(n110790), .Z(n110781)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13808_2_lut_rep_723_4_lut.init = 16'hf600;
    LUT4 i5873_2_lut_rep_706_3_lut_3_lut_4_lut (.A(n849[1]), .B(n110809), 
         .C(n855[1]), .D(n110790), .Z(n110764)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5873_2_lut_rep_706_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5880_3_lut_rep_704_4_lut_3_lut_4_lut (.A(n849[1]), .B(n110809), 
         .C(n855[1]), .D(n110790), .Z(n110762)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5880_3_lut_rep_704_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2977_3_lut_rep_722_4_lut (.A(n849[1]), .B(n110809), .C(n855[1]), 
         .D(n110790), .Z(n110780)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2977_3_lut_rep_722_4_lut.init = 16'hf666;
    LUT4 i5858_2_lut_rep_716_4_lut_4_lut (.A(n110799), .B(n854[3]), .C(n855[1]), 
         .D(n110789), .Z(n110774)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5858_2_lut_rep_716_4_lut_4_lut.init = 16'h332c;
    LUT4 i75570_3_lut_4_lut_4_lut (.A(n110510), .B(n929[2]), .C(n929[1]), 
         .D(rst_n_c), .Z(\lux_data[27] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75570_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i5586_3_lut_4_lut (.A(n853[3]), .B(n110800), .C(n110792), .D(n110775), 
         .Z(n868[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5586_3_lut_4_lut.init = 16'h6966;
    LUT4 i2971_3_lut_rep_726_4_lut (.A(n853[1]), .B(n110813), .C(n860[1]), 
         .D(n110795), .Z(n110784)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2971_3_lut_rep_726_4_lut.init = 16'hf666;
    LUT4 i5761_2_lut_rep_711_3_lut_3_lut_4_lut (.A(n853[1]), .B(n110813), 
         .C(n860[1]), .D(n110795), .Z(n110769)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5761_2_lut_rep_711_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4305_3_lut_rep_514_4_lut_3_lut_4_lut (.A(n110614), .B(n915[3]), 
         .C(n916[1]), .D(n916[2]), .Z(n110572)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4305_3_lut_rep_514_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i75872_4_lut_4_lut (.A(n110536), .B(rst_n_c), .C(n83393), .D(n110512), 
         .Z(n83415)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75872_4_lut_4_lut.init = 16'h37bf;
    LUT4 i4661_2_lut_rep_559_4_lut_4_lut (.A(n110644), .B(n899[3]), .C(n900[1]), 
         .D(n900[2]), .Z(n110617)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4661_2_lut_rep_559_4_lut_4_lut.init = 16'h332c;
    LUT4 i3026_4_lut (.A(\lux[22] ), .B(bcd_code_31__N_952), .C(bcd_code_31__N_956), 
         .D(n111098), .Z(n6059)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3026_4_lut.init = 16'hfcec;
    LUT4 i5768_3_lut_rep_709_4_lut_3_lut_4_lut (.A(n853[1]), .B(n110813), 
         .C(n860[1]), .D(n110795), .Z(n110767)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5768_3_lut_rep_709_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4283_2_lut_rep_526_4_lut_4_lut (.A(n110614), .B(n915[3]), .C(n916[1]), 
         .D(n916[2]), .Z(n110584)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4283_2_lut_rep_526_4_lut_4_lut.init = 16'h332c;
    LUT4 i75571_2_lut_rep_424_4_lut_4_lut (.A(n110510), .B(n929[2]), .C(n929[1]), 
         .D(rst_n_c), .Z(n110482)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75571_2_lut_rep_424_4_lut_4_lut.init = 16'h6c00;
    LUT4 i4158_3_lut_rep_423_4_lut (.A(n110529), .B(n110500), .C(n110501), 
         .D(n5133), .Z(n110481)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4158_3_lut_rep_423_4_lut.init = 16'h6966;
    LUT4 i4163_2_lut_3_lut (.A(n110529), .B(n110500), .C(n110501), .Z(n21062)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(56[24:48])
    defparam i4163_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i13820_2_lut_rep_727_4_lut (.A(n853[1]), .B(n110813), .C(n860[1]), 
         .D(n110795), .Z(n110785)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13820_2_lut_rep_727_4_lut.init = 16'hf600;
    LUT4 i4298_2_lut_3_lut_3_lut_4_lut (.A(n110614), .B(n915[3]), .C(n916[1]), 
         .D(n916[2]), .Z(n925[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4298_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i5718_2_lut_rep_812_4_lut_4_lut (.A(n835[3]), .B(n110895), .C(n836[1]), 
         .D(n110886), .Z(n110870)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5718_2_lut_rep_812_4_lut_4_lut.init = 16'h554a;
    LUT4 i2904_3_lut_rep_544 (.A(n110614), .B(n915[3]), .C(n916[1]), .D(n916[2]), 
         .Z(n110602)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2904_3_lut_rep_544.init = 16'hffe0;
    LUT4 i5746_2_lut_rep_719_4_lut_4_lut (.A(n110802), .B(n859[3]), .C(n860[1]), 
         .D(n110794), .Z(n110777)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5746_2_lut_rep_719_4_lut_4_lut.init = 16'h332c;
    LUT4 i5313_2_lut_3_lut_3_lut_4_lut (.A(n110804), .B(bcd_code_31__N_1768), 
         .C(n865[1]), .D(n865[2]), .Z(n872[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5313_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i5298_2_lut_rep_721_4_lut_4_lut (.A(n110804), .B(bcd_code_31__N_1768), 
         .C(n865[1]), .D(n865[2]), .Z(n110779)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5298_2_lut_rep_721_4_lut_4_lut.init = 16'h332c;
    LUT4 i5320_3_lut_4_lut_3_lut_4_lut (.A(n110804), .B(bcd_code_31__N_1768), 
         .C(n865[1]), .D(n865[2]), .Z(n872[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5320_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2984_4_lut_else_4_lut (.A(n6291), .B(n110701), .C(bcd_code_31__N_1384), 
         .Z(n111276)) /* synthesis lut_function=(A (B+(C))) */ ;
    defparam i2984_4_lut_else_4_lut.init = 16'ha8a8;
    LUT4 i5306_3_lut_4_lut (.A(n110804), .B(bcd_code_31__N_1768), .C(n865[1]), 
         .D(n865[2]), .Z(n872[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5306_3_lut_4_lut.init = 16'h998a;
    LUT4 i5871_2_lut_rep_732_3_lut (.A(n848[3]), .B(n110808), .C(n854[3]), 
         .Z(n110790)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5871_2_lut_rep_732_3_lut.init = 16'hf6f6;
    LUT4 i5866_3_lut_4_lut (.A(n848[3]), .B(n110808), .C(n854[3]), .D(n110780), 
         .Z(n862[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i5866_3_lut_4_lut.init = 16'h6966;
    LUT4 i5754_3_lut_4_lut (.A(n852[3]), .B(n110812), .C(n859[3]), .D(n110784), 
         .Z(n867[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5754_3_lut_4_lut.init = 16'h6966;
    LUT4 i5759_2_lut_rep_737_3_lut (.A(n852[3]), .B(n110812), .C(n859[3]), 
         .Z(n110795)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5759_2_lut_rep_737_3_lut.init = 16'hf6f6;
    LUT4 i4291_3_lut_4_lut (.A(n110614), .B(n915[3]), .C(n916[1]), .D(n916[2]), 
         .Z(n925[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4291_3_lut_4_lut.init = 16'h998a;
    LUT4 i4466_3_lut_rep_517_4_lut_3_lut_4_lut (.A(n110617), .B(n908[3]), 
         .C(n909[1]), .D(n909[2]), .Z(n110575)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4466_3_lut_rep_517_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4459_2_lut_3_lut_3_lut_4_lut (.A(n110617), .B(n908[3]), .C(n909[1]), 
         .D(n909[2]), .Z(n918[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4459_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4444_2_lut_rep_529_4_lut_4_lut (.A(n110617), .B(n908[3]), .C(n909[1]), 
         .D(n909[2]), .Z(n110587)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4444_2_lut_rep_529_4_lut_4_lut.init = 16'h332c;
    LUT4 i2911_3_lut_rep_547 (.A(n110617), .B(n908[3]), .C(n909[1]), .D(n909[2]), 
         .Z(n110605)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2911_3_lut_rep_547.init = 16'hffe0;
    LUT4 i4452_3_lut_4_lut (.A(n110617), .B(n908[3]), .C(n909[1]), .D(n909[2]), 
         .Z(n918[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4452_3_lut_4_lut.init = 16'h998a;
    LUT4 i2908_4_lut_rep_442 (.A(n21022), .B(n903[1]), .C(n912[1]), .D(n21201), 
         .Z(n110500)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i2908_4_lut_rep_442.init = 16'hb3ec;
    LUT4 i2918_3_lut_rep_540_4_lut (.A(n894[1]), .B(n110627), .C(n902[1]), 
         .D(n110609), .Z(n110598)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2918_3_lut_rep_540_4_lut.init = 16'hf666;
    LUT4 bcd_code_31__N_1190_bdd_4_lut_4_lut (.A(bcd_code_31__N_797), .B(n110827), 
         .C(n110905), .D(n110788), .Z(n110272)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B (C+!(D))+!B (D)))) */ ;
    defparam bcd_code_31__N_1190_bdd_4_lut_4_lut.init = 16'h73c6;
    LUT4 i4620_2_lut_3_lut_3_lut_4_lut (.A(n894[1]), .B(n110627), .C(n902[1]), 
         .D(n110609), .Z(n911[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4620_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4627_3_lut_rep_518_4_lut_3_lut_4_lut (.A(n894[1]), .B(n110627), 
         .C(n902[1]), .D(n110609), .Z(n110576)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4627_3_lut_rep_518_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4605_2_lut_rep_519_4_lut_4_lut (.A(n110620), .B(n901[3]), .C(n902[1]), 
         .D(n110608), .Z(n110577)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4605_2_lut_rep_519_4_lut_4_lut.init = 16'h332c;
    LUT4 i4144_3_lut_rep_524_4_lut_3_lut_4_lut (.A(n110621), .B(n922[3]), 
         .C(n923[1]), .D(n923[2]), .Z(n110582)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4144_3_lut_rep_524_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i8090_2_lut_rep_705_4_lut_4_lut (.A(n110819), .B(n110818), .C(n849[1]), 
         .D(n5653), .Z(n110763)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i8090_2_lut_rep_705_4_lut_4_lut.init = 16'h936c;
    LUT4 i13806_2_lut_rep_733_3_lut_4_lut (.A(n848[1]), .B(n110820), .C(n854[1]), 
         .D(n110811), .Z(n110791)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13806_2_lut_rep_733_3_lut_4_lut.init = 16'hf600;
    LUT4 i5908_3_lut_4_lut_3_lut_4_lut (.A(n848[1]), .B(n110820), .C(n854[1]), 
         .D(n110811), .Z(n861[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5908_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2978_3_lut_rep_742_4_lut (.A(n848[1]), .B(n110820), .C(n854[1]), 
         .D(n110811), .Z(n110800)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2978_3_lut_rep_742_4_lut.init = 16'hf666;
    LUT4 i5901_2_lut_rep_724_3_lut_3_lut_4_lut (.A(n848[1]), .B(n110820), 
         .C(n854[1]), .D(n110811), .Z(n110782)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5901_2_lut_rep_724_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4122_2_lut_rep_533_4_lut_4_lut (.A(n110621), .B(n922[3]), .C(n923[1]), 
         .D(n923[2]), .Z(n110591)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4122_2_lut_rep_533_4_lut_4_lut.init = 16'h332c;
    LUT4 i5886_2_lut_rep_735_4_lut_4_lut (.A(n110821), .B(n853[3]), .C(n854[1]), 
         .D(n110810), .Z(n110793)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5886_2_lut_rep_735_4_lut_4_lut.init = 16'h332c;
    LUT4 i13737_2_lut_4_lut (.A(n21022), .B(n903[1]), .C(n912[1]), .D(n21201), 
         .Z(n21023)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))) */ ;
    defparam i13737_2_lut_4_lut.init = 16'ha2a8;
    LUT4 i2940_4_lut (.A(\lux[23] ), .B(bcd_code_31__N_914), .C(bcd_code_31__N_918), 
         .D(n111102), .Z(n5329)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2940_4_lut.init = 16'hfcec;
    LUT4 i5591_2_lut_rep_725_4_lut_4_lut (.A(n110823), .B(n110822), .C(n853[1]), 
         .D(n110793), .Z(n110783)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i5591_2_lut_rep_725_4_lut_4_lut.init = 16'hff6c;
    LUT4 i2973_3_lut_rep_745_4_lut (.A(n852[1]), .B(n110824), .C(n859[1]), 
         .D(n110815), .Z(n110803)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2973_3_lut_rep_745_4_lut.init = 16'hf666;
    LUT4 i5817_2_lut_3_lut_3_lut_4_lut (.A(n852[1]), .B(n110824), .C(n859[1]), 
         .D(n110815), .Z(n866[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5817_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5824_3_lut_4_lut_3_lut_4_lut (.A(n852[1]), .B(n110824), .C(n859[1]), 
         .D(n110815), .Z(n866[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5824_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5802_2_lut_rep_728_4_lut_4_lut (.A(n110825), .B(n858[3]), .C(n859[1]), 
         .D(n110814), .Z(n110786)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5802_2_lut_rep_728_4_lut_4_lut.init = 16'h332c;
    LUT4 i75415_2_lut_rep_759 (.A(bcd_code_31__N_2138), .B(rst_n_c), .Z(n110817)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75415_2_lut_rep_759.init = 16'h8888;
    LUT4 i75688_2_lut_3_lut_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), 
         .C(n110592), .D(n110591), .Z(n14_adj_104)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75688_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hffbf;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_204 (.A(bcd_code_31__N_2138), 
         .B(rst_n_c), .C(n110592), .D(n110591), .Z(n107610)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut_adj_204.init = 16'hfbff;
    LUT4 i75692_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), 
         .B(rst_n_c), .C(n110591), .D(n110592), .Z(n7_adj_105)) /* synthesis lut_function=(!(A (B)+!A !((C+!(D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75692_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h7377;
    LUT4 i75763_2_lut_rep_521_3_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), 
         .C(n110612), .D(n922[3]), .Z(n110579)) /* synthesis lut_function=(!(((C (D)+!C !(D))+!B)+!A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75763_2_lut_rep_521_3_lut_4_lut.init = 16'h0880;
    LUT4 i75382_2_lut_2_lut_3_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), 
         .C(n110591), .D(n110592), .Z(n14_adj_106)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75382_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 i75691_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), 
         .B(rst_n_c), .C(n110591), .D(n110592), .Z(n14_adj_107)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75691_2_lut_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'hf7ff;
    LUT4 mux_33_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), 
         .B(rst_n_c), .C(n110580), .D(n110591), .Z(n7_adj_108)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(B (C+(D))+!B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_33_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut.init = 16'h7cf0;
    LUT4 i2898_3_lut_rep_554 (.A(n110621), .B(n922[3]), .C(n923[1]), .D(n923[2]), 
         .Z(n110612)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2898_3_lut_rep_554.init = 16'hffe0;
    LUT4 i75695_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), 
         .C(n110591), .D(n110592), .Z(n14_adj_109)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75695_4_lut_4_lut_4_lut.init = 16'hfff7;
    LUT4 i75400_3_lut_4_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), 
         .C(n110592), .D(n110591), .Z(n16550)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75400_3_lut_4_lut_4_lut_4_lut.init = 16'hffb7;
    LUT4 mux_33_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(bcd_code_31__N_2138), 
         .B(rst_n_c), .C(n110591), .D(n110592), .Z(n14_adj_110)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam mux_33_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i2988_3_lut_rep_750_4_lut (.A(bcd_code_31__N_1140), .B(n110828), 
         .C(n849[1]), .D(n110819), .Z(n110808)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i2988_3_lut_rep_750_4_lut.init = 16'hf666;
    LUT4 i6104_3_lut_rep_730_4_lut_3_lut_4_lut (.A(bcd_code_31__N_1140), .B(n110828), 
         .C(n849[1]), .D(n110819), .Z(n110788)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6104_3_lut_rep_730_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6097_2_lut_rep_731_3_lut_3_lut_4_lut (.A(bcd_code_31__N_1140), .B(n110828), 
         .C(n849[1]), .D(n110819), .Z(n110789)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6097_2_lut_rep_731_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13782_2_lut_rep_751_4_lut (.A(bcd_code_31__N_1140), .B(n110828), 
         .C(n849[1]), .D(n110819), .Z(n110809)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13782_2_lut_rep_751_4_lut.init = 16'hf600;
    LUT4 i6082_2_lut_rep_741_4_lut_4_lut (.A(n110829), .B(n848[3]), .C(n849[1]), 
         .D(n110818), .Z(n110799)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6082_2_lut_rep_741_4_lut_4_lut.init = 16'h332c;
    LUT4 i5894_3_lut_4_lut (.A(n110843), .B(n110830), .C(n853[3]), .D(n110800), 
         .Z(n861[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5894_3_lut_4_lut.init = 16'h6966;
    LUT4 i5899_2_lut_rep_753_3_lut (.A(n110843), .B(n110830), .C(n853[3]), 
         .Z(n110811)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5899_2_lut_rep_753_3_lut.init = 16'hf6f6;
    LUT4 i2981_3_lut_rep_754_4_lut (.A(n847[1]), .B(n110831), .C(n853[1]), 
         .D(n110823), .Z(n110812)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2981_3_lut_rep_754_4_lut.init = 16'hf666;
    LUT4 i5957_2_lut_rep_736_3_lut_3_lut_4_lut (.A(n847[1]), .B(n110831), 
         .C(n853[1]), .D(n110823), .Z(n110794)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5957_2_lut_rep_736_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5964_3_lut_rep_734_4_lut_3_lut_4_lut (.A(n847[1]), .B(n110831), 
         .C(n853[1]), .D(n110823), .Z(n110792)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5964_3_lut_rep_734_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i13801_2_lut_rep_755_4_lut (.A(n847[1]), .B(n110831), .C(n853[1]), 
         .D(n110823), .Z(n110813)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13801_2_lut_rep_755_4_lut.init = 16'hf600;
    LUT4 i4130_3_lut_rep_534_4_lut (.A(n110621), .B(n922[3]), .C(n923[1]), 
         .D(n923[2]), .Z(n110592)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4130_3_lut_rep_534_4_lut.init = 16'h998a;
    LUT4 i5942_2_lut_rep_744_4_lut_4_lut (.A(n110832), .B(n852[3]), .C(n853[1]), 
         .D(n110822), .Z(n110802)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5942_2_lut_rep_744_4_lut_4_lut.init = 16'h332c;
    LUT4 i2899_4_lut (.A(n21062), .B(n912[1]), .C(n921[1]), .D(n21023), 
         .Z(n5133)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i2899_4_lut.init = 16'hb3ec;
    LUT4 i4296_2_lut_rep_543_3_lut (.A(n906[3]), .B(n110632), .C(n915[3]), 
         .Z(n110601)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4296_2_lut_rep_543_3_lut.init = 16'hf6f6;
    LUT4 i5810_3_lut_4_lut (.A(n851[3]), .B(n110833), .C(n858[3]), .D(n110803), 
         .Z(n866[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5810_3_lut_4_lut.init = 16'h6966;
    LUT4 i5815_2_lut_rep_757_3_lut (.A(n851[3]), .B(n110833), .C(n858[3]), 
         .Z(n110815)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5815_2_lut_rep_757_3_lut.init = 16'hf6f6;
    LUT4 i5830_2_lut_rep_746_4_lut_4_lut (.A(n110834), .B(bcd_code_31__N_1690), 
         .C(n858[1]), .D(n858[2]), .Z(n110804)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5830_2_lut_rep_746_4_lut_4_lut.init = 16'h332c;
    LUT4 i5845_2_lut_3_lut_3_lut_4_lut (.A(n110834), .B(bcd_code_31__N_1690), 
         .C(n858[1]), .D(n858[2]), .Z(n865[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5845_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2951_4_lut (.A(\lux[24] ), .B(bcd_code_31__N_887), .C(bcd_code_31__N_891), 
         .D(n111108), .Z(n5433)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2951_4_lut.init = 16'hfcec;
    LUT4 i5852_3_lut_4_lut_3_lut_4_lut (.A(n110834), .B(bcd_code_31__N_1690), 
         .C(n858[1]), .D(n858[2]), .Z(n865[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5852_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5838_3_lut_4_lut (.A(n110834), .B(bcd_code_31__N_1690), .C(n858[1]), 
         .D(n858[2]), .Z(n865[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5838_3_lut_4_lut.init = 16'h998a;
    LUT4 i75709_4_lut_4_lut_4_lut (.A(n110535), .B(rst_n_c), .C(n110534), 
         .D(n110536), .Z(n16351)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75709_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i6916_3_lut_4_lut (.A(n6094), .B(n110841), .C(bcd_code_31__N_1140), 
         .D(bcd_code_31__N_798), .Z(bcd_code_31__N_797)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6916_3_lut_4_lut.init = 16'h7f80;
    LUT4 i4613_3_lut_4_lut (.A(n893[3]), .B(n110626), .C(n901[3]), .D(n110598), 
         .Z(n911[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4613_3_lut_4_lut.init = 16'h6966;
    LUT4 i6090_3_lut_4_lut (.A(n110859), .B(n6094), .C(n848[3]), .D(n110808), 
         .Z(n855[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6090_3_lut_4_lut.init = 16'h6966;
    LUT4 i4618_2_lut_rep_551_3_lut (.A(n893[3]), .B(n110626), .C(n901[3]), 
         .Z(n110609)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i4618_2_lut_rep_551_3_lut.init = 16'hf6f6;
    LUT4 i4633_2_lut_4_lut_4_lut (.A(n901[0]), .B(n110628), .C(n901[1]), 
         .D(n901[2]), .Z(n910[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4633_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i6095_2_lut_rep_761_3_lut (.A(n110859), .B(n6094), .C(n848[3]), 
         .Z(n110819)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6095_2_lut_rep_761_3_lut.init = 16'hf6f6;
    LUT4 i4648_2_lut_3_lut_3_lut_4_lut (.A(n901[0]), .B(n110628), .C(n901[1]), 
         .D(n901[2]), .Z(n910[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4648_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4655_3_lut_4_lut_3_lut_4_lut (.A(n901[0]), .B(n110628), .C(n901[1]), 
         .D(n901[2]), .Z(n910[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4655_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i5950_3_lut_4_lut (.A(n846[3]), .B(n110837), .C(n852[3]), .D(n110812), 
         .Z(n860[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5950_3_lut_4_lut.init = 16'h6966;
    LUT4 i5955_2_lut_rep_765_3_lut (.A(n846[3]), .B(n110837), .C(n852[3]), 
         .Z(n110823)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i5955_2_lut_rep_765_3_lut.init = 16'hf6f6;
    LUT4 i4641_3_lut_4_lut (.A(n901[0]), .B(n110628), .C(n901[1]), .D(n901[2]), 
         .Z(n910[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4641_3_lut_4_lut.init = 16'h998a;
    LUT4 i13781_2_lut_rep_762_3_lut_4_lut (.A(n842[1]), .B(n110842), .C(n848[1]), 
         .D(n110836), .Z(n110820)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13781_2_lut_rep_762_3_lut_4_lut.init = 16'hf600;
    LUT4 i6132_3_lut_4_lut_3_lut_4_lut (.A(n842[1]), .B(n110842), .C(n848[1]), 
         .D(n110836), .Z(n854[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6132_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2989_3_lut_rep_772_4_lut (.A(n842[1]), .B(n110842), .C(n848[1]), 
         .D(n110836), .Z(n110830)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2989_3_lut_rep_772_4_lut.init = 16'hf666;
    LUT4 i6125_2_lut_rep_752_3_lut_3_lut_4_lut (.A(n842[1]), .B(n110842), 
         .C(n848[1]), .D(n110836), .Z(n110810)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6125_2_lut_rep_752_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2967_4_lut (.A(\lux[25] ), .B(bcd_code_31__N_860), .C(bcd_code_31__N_864), 
         .D(n111110), .Z(n5548)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2967_4_lut.init = 16'hfcec;
    LUT4 i6110_2_lut_rep_763_4_lut_4_lut (.A(n110844), .B(n110843), .C(n848[1]), 
         .D(n110835), .Z(n110821)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6110_2_lut_rep_763_4_lut_4_lut.init = 16'h332c;
    LUT4 i4135_2_lut_rep_553_3_lut (.A(bcd_code_31__N_2099), .B(n110639), 
         .C(n922[3]), .Z(n110611)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4135_2_lut_rep_553_3_lut.init = 16'hf6f6;
    LUT4 i13792_2_lut_rep_766_3_lut_4_lut (.A(n846[1]), .B(n110847), .C(n852[1]), 
         .D(n110839), .Z(n110824)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13792_2_lut_rep_766_3_lut_4_lut.init = 16'hf600;
    LUT4 i5992_3_lut_4_lut_3_lut_4_lut (.A(n846[1]), .B(n110847), .C(n852[1]), 
         .D(n110839), .Z(n859[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5992_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2982_3_lut_rep_775_4_lut (.A(n846[1]), .B(n110847), .C(n852[1]), 
         .D(n110839), .Z(n110833)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2982_3_lut_rep_775_4_lut.init = 16'hf666;
    LUT4 i5985_2_lut_rep_756_3_lut_3_lut_4_lut (.A(n846[1]), .B(n110847), 
         .C(n852[1]), .D(n110839), .Z(n110814)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5985_2_lut_rep_756_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5970_2_lut_rep_767_4_lut_4_lut (.A(n110848), .B(n851[3]), .C(n852[1]), 
         .D(n110838), .Z(n110825)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5970_2_lut_rep_767_4_lut_4_lut.init = 16'h332c;
    LUT4 i3030_3_lut_4_lut (.A(n110851), .B(n110859), .C(bcd_code_31__N_1140), 
         .D(bcd_code_31__N_798), .Z(n6094)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i3030_3_lut_4_lut.init = 16'hffe0;
    LUT4 i6909_2_lut_rep_760_3_lut_4_lut (.A(n110851), .B(n110859), .C(bcd_code_31__N_1140), 
         .D(n6094), .Z(n110818)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6909_2_lut_rep_760_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i6118_3_lut_4_lut (.A(n841[3]), .B(n110852), .C(n110843), .D(n110830), 
         .Z(n854[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6118_3_lut_4_lut.init = 16'h6966;
    LUT4 i13728_2_lut_rep_773_3_lut_4_lut (.A(n841[1]), .B(n110863), .C(n847[1]), 
         .D(n110846), .Z(n110831)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13728_2_lut_rep_773_3_lut_4_lut.init = 16'hf600;
    LUT4 i3006_3_lut_rep_779_4_lut (.A(n841[1]), .B(n110863), .C(n847[1]), 
         .D(n110846), .Z(n110837)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3006_3_lut_rep_779_4_lut.init = 16'hf666;
    LUT4 i4326_2_lut_3_lut_3_lut_4_lut (.A(n110630), .B(n914[3]), .C(n915[1]), 
         .D(n915[2]), .Z(n924[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4326_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i6461_2_lut_rep_764_3_lut_3_lut_4_lut (.A(n841[1]), .B(n110863), 
         .C(n847[1]), .D(n110846), .Z(n110822)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6461_2_lut_rep_764_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6468_3_lut_4_lut_3_lut_4_lut (.A(n841[1]), .B(n110863), .C(n847[1]), 
         .D(n110846), .Z(n853[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6468_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6446_2_lut_rep_774_4_lut_4_lut (.A(n110854), .B(n846[3]), .C(n847[1]), 
         .D(n110845), .Z(n110832)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6446_2_lut_rep_774_4_lut_4_lut.init = 16'h332c;
    LUT4 i5978_3_lut_4_lut (.A(n845[3]), .B(n110855), .C(n851[3]), .D(n110833), 
         .Z(n859[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5978_3_lut_4_lut.init = 16'h6966;
    LUT4 i5983_2_lut_rep_781_3_lut (.A(n845[3]), .B(n110855), .C(n851[3]), 
         .Z(n110839)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5983_2_lut_rep_781_3_lut.init = 16'hf6f6;
    LUT4 i6907_2_lut_rep_783_3_lut (.A(n110885), .B(n23_adj_71), .C(n110859), 
         .Z(n110841)) /* synthesis lut_function=(A (B+(C))+!A ((C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6907_2_lut_rep_783_3_lut.init = 16'hf9f9;
    LUT4 i13767_2_lut_rep_770_3_lut_4_lut (.A(n110885), .B(n23_adj_71), 
         .C(n6094), .D(n110859), .Z(n110828)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (B (C (D))+!B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i13767_2_lut_rep_770_3_lut_4_lut.init = 16'hf090;
    LUT4 i6902_3_lut_4_lut (.A(n110885), .B(n23_adj_71), .C(n110859), 
         .D(n6094), .Z(n849[1])) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6902_3_lut_4_lut.init = 16'h9699;
    LUT4 i6454_3_lut_4_lut (.A(n840[3]), .B(n110862), .C(n846[3]), .D(n110837), 
         .Z(n853[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6454_3_lut_4_lut.init = 16'h6966;
    LUT4 i6459_2_lut_rep_788_3_lut (.A(n840[3]), .B(n110862), .C(n846[3]), 
         .Z(n110846)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6459_2_lut_rep_788_3_lut.init = 16'hf6f6;
    LUT4 i6013_2_lut_3_lut_3_lut_4_lut (.A(n845[1]), .B(n110866), .C(n851[1]), 
         .D(n110857), .Z(n858[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6013_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2983_3_lut_rep_791_4_lut (.A(n845[1]), .B(n110866), .C(n851[1]), 
         .D(n110857), .Z(n110849)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2983_3_lut_rep_791_4_lut.init = 16'hf666;
    LUT4 i6020_3_lut_4_lut_3_lut_4_lut (.A(n845[1]), .B(n110866), .C(n851[1]), 
         .D(n110857), .Z(n858[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6020_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5998_2_lut_rep_776_4_lut_4_lut (.A(bcd_code_31__N_1588), .B(n110867), 
         .C(n851[1]), .D(n110856), .Z(n110834)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5998_2_lut_rep_776_4_lut_4_lut.init = 16'h554a;
    LUT4 i13842_2_lut_rep_784_3_lut_4_lut (.A(n836[1]), .B(n110878), .C(n842[1]), 
         .D(n110861), .Z(n110842)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13842_2_lut_rep_784_3_lut_4_lut.init = 16'hf600;
    LUT4 i2927_3_lut_rep_794_4_lut (.A(n836[1]), .B(n110878), .C(n842[1]), 
         .D(n110861), .Z(n110852)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2927_3_lut_rep_794_4_lut.init = 16'hf666;
    LUT4 i4872_2_lut_rep_777_3_lut_3_lut_4_lut (.A(n836[1]), .B(n110878), 
         .C(n842[1]), .D(n110861), .Z(n110835)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4872_2_lut_rep_777_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4879_3_lut_4_lut_3_lut_4_lut (.A(n836[1]), .B(n110878), .C(n842[1]), 
         .D(n110861), .Z(n848[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4879_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4857_2_lut_rep_786_4_lut_4_lut (.A(n841[3]), .B(n110870), .C(n842[1]), 
         .D(n110860), .Z(n110844)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4857_2_lut_rep_786_4_lut_4_lut.init = 16'h554a;
    LUT4 i6123_2_lut_rep_778_4_lut_4_lut (.A(n110872), .B(n110871), .C(n841[1]), 
         .D(n110844), .Z(n110836)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i6123_2_lut_rep_778_4_lut_4_lut.init = 16'hff6c;
    LUT4 i13846_2_lut_rep_789_3_lut_4_lut (.A(n840[1]), .B(n110873), .C(n846[1]), 
         .D(n110865), .Z(n110847)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13846_2_lut_rep_789_3_lut_4_lut.init = 16'hf600;
    LUT4 i3009_3_lut_rep_797_4_lut (.A(n840[1]), .B(n110873), .C(n846[1]), 
         .D(n110865), .Z(n110855)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3009_3_lut_rep_797_4_lut.init = 16'hf666;
    LUT4 i6545_2_lut_rep_780_3_lut_3_lut_4_lut (.A(n840[1]), .B(n110873), 
         .C(n846[1]), .D(n110865), .Z(n110838)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6545_2_lut_rep_780_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6552_3_lut_4_lut_3_lut_4_lut (.A(n840[1]), .B(n110873), .C(n846[1]), 
         .D(n110865), .Z(n852[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6552_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6530_2_lut_rep_790_4_lut_4_lut (.A(n845[3]), .B(n110874), .C(n846[1]), 
         .D(n110864), .Z(n110848)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6530_2_lut_rep_790_4_lut_4_lut.init = 16'h554a;
    LUT4 i4669_3_lut_4_lut (.A(n110644), .B(n899[3]), .C(n900[1]), .D(n900[2]), 
         .Z(n909[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i4669_3_lut_4_lut.init = 16'h998a;
    LUT4 i6006_3_lut_4_lut (.A(bcd_code_31__N_1519), .B(n110875), .C(bcd_code_31__N_1588), 
         .D(n110849), .Z(n858[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6006_3_lut_4_lut.init = 16'h6966;
    LUT4 i2957_3_lut_rep_568_4_lut (.A(bcd_code_31__N_1394), .B(n110645), 
         .C(n894[1]), .D(n110637), .Z(n110626)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i2957_3_lut_rep_568_4_lut.init = 16'hf666;
    LUT4 i5425_2_lut_rep_550_3_lut_3_lut_4_lut (.A(bcd_code_31__N_1394), .B(n110645), 
         .C(n894[1]), .D(n110637), .Z(n110608)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i5425_2_lut_rep_550_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13795_2_lut_rep_927_3_lut_4_lut (.A(n814[1]), .B(n111003), .C(n818[1]), 
         .D(n111000), .Z(n110985)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13795_2_lut_rep_927_3_lut_4_lut.init = 16'hf600;
    LUT4 i13824_2_lut_rep_815_3_lut_4_lut (.A(n834[1]), .B(n110900), .C(n840[1]), 
         .D(n110890), .Z(n110873)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13824_2_lut_rep_815_3_lut_4_lut.init = 16'hf600;
    LUT4 i2937_3_lut_rep_823_4_lut (.A(n834[1]), .B(n110900), .C(n840[1]), 
         .D(n110890), .Z(n110881)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2937_3_lut_rep_823_4_lut.init = 16'hf666;
    LUT4 i3035_2_lut_rep_799_3_lut (.A(bcd_code_31__N_1519), .B(n110875), 
         .C(bcd_code_31__N_1588), .Z(n110857)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3035_2_lut_rep_799_3_lut.init = 16'hf6f6;
    LUT4 i5068_2_lut_rep_806_3_lut_3_lut_4_lut (.A(n834[1]), .B(n110900), 
         .C(n840[1]), .D(n110890), .Z(n110864)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5068_2_lut_rep_806_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5075_3_lut_4_lut_3_lut_4_lut (.A(n834[1]), .B(n110900), .C(n840[1]), 
         .D(n110890), .Z(n846[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5075_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5053_2_lut_rep_816_4_lut_4_lut (.A(n839[3]), .B(n110899), .C(n840[1]), 
         .D(n110889), .Z(n110874)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5053_2_lut_rep_816_4_lut_4_lut.init = 16'h554a;
    LUT4 i5432_3_lut_rep_549_4_lut_3_lut_4_lut (.A(bcd_code_31__N_1394), .B(n110645), 
         .C(n894[1]), .D(n110637), .Z(n110607)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i5432_3_lut_rep_549_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6678_3_lut_4_lut (.A(bcd_code_31__N_1450), .B(n110901), .C(bcd_code_31__N_1519), 
         .D(n110875), .Z(n851[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6678_3_lut_4_lut.init = 16'h6966;
    LUT4 i6683_2_lut_rep_825_3_lut (.A(bcd_code_31__N_1450), .B(n110901), 
         .C(bcd_code_31__N_1519), .Z(n110883)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6683_2_lut_rep_825_3_lut.init = 16'hf6f6;
    LUT4 i75562_3_lut_4_lut_4_lut (.A(n110538), .B(n927[2]), .C(n927[1]), 
         .D(rst_n_c), .Z(\lux_data[19] )) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(C (D)))) */ ;
    defparam i75562_3_lut_4_lut_4_lut.init = 16'h5800;
    LUT4 i13762_2_lut_rep_569_4_lut (.A(bcd_code_31__N_1394), .B(n110645), 
         .C(n894[1]), .D(n110637), .Z(n110627)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i13762_2_lut_rep_569_4_lut.init = 16'hf600;
    LUT4 mux_9086_i3_3_lut_rep_769_4_lut (.A(n110904), .B(n110980), .C(n6268), 
         .D(n6264), .Z(n110827)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_9086_i3_3_lut_rep_769_4_lut.init = 16'hf780;
    LUT4 i5410_2_lut_rep_562_4_lut_4_lut (.A(n893[3]), .B(n110646), .C(n894[1]), 
         .D(n110636), .Z(n110620)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5410_2_lut_rep_562_4_lut_4_lut.init = 16'h554a;
    LUT4 i75563_2_lut_rep_436_4_lut_4_lut (.A(n110538), .B(n927[2]), .C(n927[1]), 
         .D(rst_n_c), .Z(n110494)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C (D)))+!A !(B (D)))) */ ;
    defparam i75563_2_lut_rep_436_4_lut_4_lut.init = 16'h6c00;
    LUT4 i3053_2_lut_rep_829_3_lut (.A(n830[3]), .B(n110906), .C(n835[3]), 
         .Z(n110887)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i3053_2_lut_rep_829_3_lut.init = 16'hf6f6;
    LUT4 i5726_3_lut_4_lut (.A(n830[3]), .B(n110906), .C(n835[3]), .D(n110877), 
         .Z(n842[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5726_3_lut_4_lut.init = 16'h6966;
    LUT4 i13760_2_lut_rep_821_3_lut_4_lut (.A(n830[1]), .B(n110908), .C(n835[1]), 
         .D(n110898), .Z(n110879)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13760_2_lut_rep_821_3_lut_4_lut.init = 16'hf600;
    LUT4 i2993_3_lut_rep_830_4_lut (.A(n830[1]), .B(n110908), .C(n835[1]), 
         .D(n110898), .Z(n110888)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2993_3_lut_rep_830_4_lut.init = 16'hf666;
    LUT4 i6244_3_lut_4_lut_3_lut_4_lut (.A(n830[1]), .B(n110908), .C(n835[1]), 
         .D(n110898), .Z(n841[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6244_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6237_2_lut_rep_813_3_lut_3_lut_4_lut (.A(n830[1]), .B(n110908), 
         .C(n835[1]), .D(n110898), .Z(n110871)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6237_2_lut_rep_813_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6222_2_lut_rep_822_4_lut_4_lut (.A(n834[3]), .B(n110909), .C(n835[1]), 
         .D(n110897), .Z(n110880)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6222_2_lut_rep_822_4_lut_4_lut.init = 16'h554a;
    LUT4 i2522_2_lut_rep_832_3_lut (.A(n833[3]), .B(n110910), .C(n839[3]), 
         .Z(n110890)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2522_2_lut_rep_832_3_lut.init = 16'hf6f6;
    LUT4 i5061_3_lut_4_lut (.A(n833[3]), .B(n110910), .C(n839[3]), .D(n110881), 
         .Z(n846[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5061_3_lut_4_lut.init = 16'h6966;
    LUT4 i6398_3_lut_4_lut (.A(bcd_code_31__N_1180), .B(n110992), .C(bcd_code_31__N_1246), 
         .D(n110971), .Z(n828[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6398_3_lut_4_lut.init = 16'h6966;
    LUT4 i7967_2_lut_4_lut_4_lut (.A(n826[3]), .B(bcd_code_31__N_1042), 
         .C(n110885), .D(n23_adj_71), .Z(n11979)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B+(D)))) */ ;
    defparam i7967_2_lut_4_lut_4_lut.init = 16'h0091;
    LUT4 i2561_2_lut_rep_846 (.A(bcd_code_31__N_1042), .B(n826[3]), .Z(n110904)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2561_2_lut_rep_846.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_4_lut_adj_205 (.A(bcd_code_31__N_1042), .B(n826[3]), 
         .C(n110885), .D(n110980), .Z(n29_adj_2344)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+(D))+!B (C)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_4_lut_adj_205.init = 16'h0b05;
    LUT4 bcd_code_31__N_1039_bdd_4_lut_4_lut (.A(bcd_code_31__N_1042), .B(n826[3]), 
         .C(n110980), .D(n110885), .Z(n110276)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !((D)+!C))+!A !(B (C+!(D))+!B (D)))) */ ;
    defparam bcd_code_31__N_1039_bdd_4_lut_4_lut.init = 16'h73c6;
    LUT4 i75801_2_lut_4_lut_4_lut (.A(n110538), .B(n927[2]), .C(n927[1]), 
         .D(n110507), .Z(n83386)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C+(D)))+!A (B+(D))) */ ;
    defparam i75801_2_lut_4_lut_4_lut.init = 16'hff6c;
    LUT4 i4361_3_lut_4_lut_3_lut_4_lut (.A(n110649), .B(bcd_code_31__N_2099), 
         .C(n914[1]), .D(n914[2]), .Z(n923[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4361_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i7922_2_lut_rep_793_4_lut_4_lut (.A(n110915), .B(n110914), .C(n831[1]), 
         .D(n23_adj_71), .Z(n110851)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D)))) */ ;
    defparam i7922_2_lut_rep_793_4_lut_4_lut.init = 16'h6c93;
    LUT4 i3057_2_lut_rep_840_3_lut (.A(n829[3]), .B(n110916), .C(n834[3]), 
         .Z(n110898)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3057_2_lut_rep_840_3_lut.init = 16'hf6f6;
    LUT4 i6230_3_lut_4_lut (.A(n829[3]), .B(n110916), .C(n834[3]), .D(n110888), 
         .Z(n841[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6230_3_lut_4_lut.init = 16'h6966;
    LUT4 i13788_2_lut_rep_833_3_lut_4_lut (.A(n833[1]), .B(n110919), .C(n839[1]), 
         .D(n110912), .Z(n110891)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13788_2_lut_rep_833_3_lut_4_lut.init = 16'hf600;
    LUT4 i2948_3_lut_rep_843_4_lut (.A(n833[1]), .B(n110919), .C(n839[1]), 
         .D(n110912), .Z(n110901)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2948_3_lut_rep_843_4_lut.init = 16'hf666;
    LUT4 i5341_2_lut_rep_824_3_lut_3_lut_4_lut (.A(n833[1]), .B(n110919), 
         .C(n839[1]), .D(n110912), .Z(n110882)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5341_2_lut_rep_824_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5348_3_lut_4_lut_3_lut_4_lut (.A(n833[1]), .B(n110919), .C(n839[1]), 
         .D(n110912), .Z(n845[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5348_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5326_2_lut_rep_834_4_lut_4_lut (.A(bcd_code_31__N_1450), .B(n110920), 
         .C(n839[1]), .D(n110911), .Z(n110892)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5326_2_lut_rep_834_4_lut_4_lut.init = 16'h554a;
    LUT4 i3027_3_lut_rep_848_4_lut (.A(bcd_code_31__N_1047), .B(n110922), 
         .C(n831[1]), .D(n110915), .Z(n110906)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i3027_3_lut_rep_848_4_lut.init = 16'hf666;
    LUT4 i6832_3_lut_rep_827_4_lut_3_lut_4_lut (.A(bcd_code_31__N_1047), .B(n110922), 
         .C(n831[1]), .D(n110915), .Z(n110885)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6832_3_lut_rep_827_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6825_2_lut_rep_828_3_lut_3_lut_4_lut (.A(bcd_code_31__N_1047), .B(n110922), 
         .C(n831[1]), .D(n110915), .Z(n110886)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6825_2_lut_rep_828_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i13799_2_lut_rep_849_4_lut (.A(bcd_code_31__N_1047), .B(n110922), 
         .C(n831[1]), .D(n110915), .Z(n110907)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13799_2_lut_rep_849_4_lut.init = 16'hf600;
    LUT4 i6810_2_lut_rep_837_4_lut_4_lut (.A(n830[3]), .B(n110923), .C(n831[1]), 
         .D(n110914), .Z(n110895)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6810_2_lut_rep_837_4_lut_4_lut.init = 16'h554a;
    LUT4 i4339_2_lut_rep_563_4_lut_4_lut (.A(n110649), .B(bcd_code_31__N_2099), 
         .C(n914[1]), .D(n914[2]), .Z(n110621)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4339_2_lut_rep_563_4_lut_4_lut.init = 16'h332c;
    LUT4 i4354_2_lut_3_lut_3_lut_4_lut (.A(n110649), .B(bcd_code_31__N_2099), 
         .C(n914[1]), .D(n914[2]), .Z(n923[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4354_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2906_3_lut_rep_581 (.A(n110649), .B(bcd_code_31__N_2099), .C(n914[1]), 
         .D(n914[2]), .Z(n110639)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2906_3_lut_rep_581.init = 16'hffe0;
    LUT4 i4347_3_lut_4_lut (.A(n110649), .B(bcd_code_31__N_2099), .C(n914[1]), 
         .D(n914[2]), .Z(n923[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i4347_3_lut_4_lut.init = 16'h998a;
    LUT4 i4004_3_lut_rep_439_4_lut_3_lut_4_lut (.A(n928[0]), .B(n110540), 
         .C(n928[1]), .D(n928[2]), .Z(n110497)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i4004_3_lut_rep_439_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i3002_3_lut_rep_852_4_lut (.A(n829[1]), .B(n110926), .C(n834[1]), 
         .D(n110918), .Z(n110910)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3002_3_lut_rep_852_4_lut.init = 16'hf666;
    LUT4 i13734_2_lut_rep_842_3_lut_4_lut (.A(n829[1]), .B(n110926), .C(n834[1]), 
         .D(n110918), .Z(n110900)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13734_2_lut_rep_842_3_lut_4_lut.init = 16'hf600;
    LUT4 i6377_2_lut_rep_831_3_lut_3_lut_4_lut (.A(n829[1]), .B(n110926), 
         .C(n834[1]), .D(n110918), .Z(n110889)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6377_2_lut_rep_831_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6384_3_lut_4_lut_3_lut_4_lut (.A(n829[1]), .B(n110926), .C(n834[1]), 
         .D(n110918), .Z(n840[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6384_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6362_2_lut_rep_841_4_lut_4_lut (.A(n110927), .B(n833[3]), .C(n834[1]), 
         .D(n110917), .Z(n110899)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6362_2_lut_rep_841_4_lut_4_lut.init = 16'h332c;
    LUT4 i3051_2_lut_rep_854_3_lut (.A(bcd_code_31__N_1366), .B(n110928), 
         .C(bcd_code_31__N_1450), .Z(n110912)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3051_2_lut_rep_854_3_lut.init = 16'hf6f6;
    LUT4 i6403_2_lut_rep_920_3_lut (.A(bcd_code_31__N_1180), .B(n110992), 
         .C(bcd_code_31__N_1246), .Z(n110978)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6403_2_lut_rep_920_3_lut.init = 16'hf6f6;
    LUT4 i5334_3_lut_4_lut (.A(bcd_code_31__N_1366), .B(n110928), .C(bcd_code_31__N_1450), 
         .D(n110901), .Z(n845[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5334_3_lut_4_lut.init = 16'h6966;
    LUT4 i5628_3_lut_4_lut (.A(n5546), .B(n110937), .C(bcd_code_31__N_1047), 
         .D(bcd_code_31__N_1043), .Z(bcd_code_31__N_1042)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5628_3_lut_4_lut.init = 16'h7f80;
    LUT4 i2570_2_lut_rep_857_3_lut (.A(n110946), .B(n5546), .C(n830[3]), 
         .Z(n110915)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2570_2_lut_rep_857_3_lut.init = 16'hf6f6;
    LUT4 i3982_2_lut_rep_449_4_lut_4_lut (.A(n928[0]), .B(n110540), .C(n928[1]), 
         .D(n928[2]), .Z(n110507)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3982_2_lut_rep_449_4_lut_4_lut.init = 16'h332c;
    LUT4 i6818_3_lut_4_lut (.A(n110946), .B(n5546), .C(n830[3]), .D(n110906), 
         .Z(n836[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i6818_3_lut_4_lut.init = 16'h6966;
    LUT4 i13840_2_lut_rep_850_3_lut_4_lut (.A(n825[1]), .B(n110931), .C(n830[1]), 
         .D(n110925), .Z(n110908)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13840_2_lut_rep_850_3_lut_4_lut.init = 16'hf600;
    LUT4 i2928_3_lut_rep_858_4_lut (.A(n825[1]), .B(n110931), .C(n830[1]), 
         .D(n110925), .Z(n110916)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2928_3_lut_rep_858_4_lut.init = 16'hf666;
    LUT4 i4900_2_lut_rep_839_3_lut_3_lut_4_lut (.A(n825[1]), .B(n110931), 
         .C(n830[1]), .D(n110925), .Z(n110897)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4900_2_lut_rep_839_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i4907_3_lut_4_lut_3_lut_4_lut (.A(n825[1]), .B(n110931), .C(n830[1]), 
         .D(n110925), .Z(n835[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4907_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i4885_2_lut_rep_851_4_lut_4_lut (.A(n829[3]), .B(n110932), .C(n830[1]), 
         .D(n110924), .Z(n110909)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4885_2_lut_rep_851_4_lut_4_lut.init = 16'h554a;
    LUT4 i5019_3_lut_4_lut (.A(n5324), .B(n110661), .C(bcd_code_31__N_1394), 
         .D(bcd_code_31__N_1392), .Z(n894[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i5019_3_lut_4_lut.init = 16'h7f80;
    LUT4 i75800_4_lut_4_lut (.A(n110481), .B(rst_n_c), .C(n83388), .D(n110479), 
         .Z(n83303)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75800_4_lut_4_lut.init = 16'h37bf;
    LUT4 i6370_3_lut_4_lut (.A(n828[3]), .B(n110933), .C(n833[3]), .D(n110910), 
         .Z(n840[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6370_3_lut_4_lut.init = 16'h6966;
    LUT4 i6375_2_lut_rep_860_3_lut (.A(n828[3]), .B(n110933), .C(n833[3]), 
         .Z(n110918)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6375_2_lut_rep_860_3_lut.init = 16'hf6f6;
    LUT4 i2893_3_lut_rep_469 (.A(n928[0]), .B(n110540), .C(n928[1]), .D(n928[2]), 
         .Z(n110527)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2893_3_lut_rep_469.init = 16'hffe0;
    LUT4 i3045_2_lut_rep_579_3_lut (.A(n110675), .B(n5324), .C(n893[3]), 
         .Z(n110637)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3045_2_lut_rep_579_3_lut.init = 16'hf6f6;
    LUT4 i5418_3_lut_4_lut (.A(n110675), .B(n5324), .C(n893[3]), .D(n110626), 
         .Z(n902[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i5418_3_lut_4_lut.init = 16'h6966;
    LUT4 i3990_3_lut_rep_450_4_lut (.A(n928[0]), .B(n110540), .C(n928[1]), 
         .D(n928[2]), .Z(n110508)) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i3990_3_lut_rep_450_4_lut.init = 16'h998a;
    LUT4 i2987_4_lut (.A(\lux[10] ), .B(bcd_code_31__N_1691), .C(bcd_code_31__N_1695), 
         .D(n110987), .Z(n5701)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2987_4_lut.init = 16'hfcec;
    LUT4 i4760_2_lut_3_lut_3_lut_4_lut (.A(n110680), .B(n896[3]), .C(n897[1]), 
         .D(n897[2]), .Z(n906[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i4760_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i3063_2_lut_rep_867_3_lut (.A(n824[3]), .B(n110938), .C(n829[3]), 
         .Z(n110925)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3063_2_lut_rep_867_3_lut.init = 16'hf6f6;
    LUT4 i4893_3_lut_4_lut (.A(n824[3]), .B(n110938), .C(n829[3]), .D(n110916), 
         .Z(n835[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4893_3_lut_4_lut.init = 16'h6966;
    LUT4 i13816_2_lut_rep_911_3_lut_4_lut (.A(n815[1]), .B(n110991), .C(n819[1]), 
         .D(n110984), .Z(n110969)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13816_2_lut_rep_911_3_lut_4_lut.init = 16'hf600;
    LUT4 i13845_2_lut_rep_861_3_lut_4_lut (.A(n828[1]), .B(n110941), .C(n833[1]), 
         .D(n110935), .Z(n110919)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13845_2_lut_rep_861_3_lut_4_lut.init = 16'hf600;
    LUT4 i3010_3_lut_rep_870_4_lut (.A(n828[1]), .B(n110941), .C(n833[1]), 
         .D(n110935), .Z(n110928)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3010_3_lut_rep_870_4_lut.init = 16'hf666;
    LUT4 i6573_2_lut_rep_853_3_lut_3_lut_4_lut (.A(n828[1]), .B(n110941), 
         .C(n833[1]), .D(n110935), .Z(n110911)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6573_2_lut_rep_853_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6580_3_lut_4_lut_3_lut_4_lut (.A(n828[1]), .B(n110941), .C(n833[1]), 
         .D(n110935), .Z(n839[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6580_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6558_2_lut_rep_862_4_lut_4_lut (.A(bcd_code_31__N_1366), .B(n110942), 
         .C(n833[1]), .D(n110934), .Z(n110920)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6558_2_lut_rep_862_4_lut_4_lut.init = 16'h554a;
    LUT4 i13148_2_lut_3_lut_4_lut (.A(n110995), .B(n110944), .C(bcd_code_31__N_1042), 
         .D(n111044), .Z(n20271)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A (C+(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13148_2_lut_3_lut_4_lut.init = 16'hf7f8;
    LUT4 i4543_2_lut_3_lut_3_lut_4_lut (.A(n905[3]), .B(n110657), .C(n906[1]), 
         .D(n906[2]), .Z(n915[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i4543_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4550_3_lut_4_lut_3_lut_4_lut (.A(n905[3]), .B(n110657), .C(n906[1]), 
         .D(n906[2]), .Z(n915[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i4550_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2965_3_lut_4_lut (.A(n110946), .B(n110945), .C(bcd_code_31__N_1047), 
         .D(bcd_code_31__N_1043), .Z(n5546)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i2965_3_lut_4_lut.init = 16'hffe0;
    LUT4 i4528_2_lut_rep_572_4_lut_4_lut (.A(n905[3]), .B(n110657), .C(n906[1]), 
         .D(n906[2]), .Z(n110630)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4528_2_lut_rep_572_4_lut_4_lut.init = 16'h554a;
    LUT4 i5621_2_lut_rep_856_3_lut_4_lut (.A(n110946), .B(n110945), .C(bcd_code_31__N_1047), 
         .D(n5546), .Z(n110914)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam i5621_2_lut_rep_856_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i4536_3_lut_4_lut (.A(n905[3]), .B(n110657), .C(n906[1]), .D(n906[2]), 
         .Z(n915[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i4536_3_lut_4_lut.init = 16'h998c;
    LUT4 i4689_2_lut_4_lut_4_lut (.A(n899[0]), .B(n110660), .C(n899[1]), 
         .D(n899[2]), .Z(n908[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4689_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i4704_2_lut_3_lut_3_lut_4_lut (.A(n899[0]), .B(n110660), .C(n899[1]), 
         .D(n899[2]), .Z(n908[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4704_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4150_2_lut_rep_422_4_lut_4_lut (.A(n110541), .B(n920[2]), .C(n920[1]), 
         .D(n5133), .Z(n110480)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i4150_2_lut_rep_422_4_lut_4_lut.init = 16'h936c;
    LUT4 i4711_3_lut_4_lut_3_lut_4_lut (.A(n899[0]), .B(n110660), .C(n899[1]), 
         .D(n899[2]), .Z(n908[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4711_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i2997_4_lut (.A(\lux[26] ), .B(bcd_code_31__N_842), .C(bcd_code_31__N_846), 
         .D(n111115), .Z(n5804)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2997_4_lut.init = 16'hfcec;
    LUT4 i4697_3_lut_4_lut (.A(n899[0]), .B(n110660), .C(n899[1]), .D(n899[2]), 
         .Z(n908[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i4697_3_lut_4_lut.init = 16'h998a;
    LUT4 i5537_2_lut_3_lut_3_lut_4_lut (.A(n885[1]), .B(n110662), .C(n893[1]), 
         .D(n110653), .Z(n901[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5537_2_lut_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2961_3_lut_rep_589_4_lut (.A(n885[1]), .B(n110662), .C(n893[1]), 
         .D(n110653), .Z(n110647)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i2961_3_lut_rep_589_4_lut.init = 16'hf666;
    LUT4 i13821_2_lut_rep_868_3_lut_4_lut (.A(n824[1]), .B(n110949), .C(n829[1]), 
         .D(n110940), .Z(n110926)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13821_2_lut_rep_868_3_lut_4_lut.init = 16'hf600;
    LUT4 i5103_3_lut_4_lut_3_lut_4_lut (.A(n824[1]), .B(n110949), .C(n829[1]), 
         .D(n110940), .Z(n834[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5103_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2938_3_lut_rep_875_4_lut (.A(n824[1]), .B(n110949), .C(n829[1]), 
         .D(n110940), .Z(n110933)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2938_3_lut_rep_875_4_lut.init = 16'hf666;
    LUT4 i5096_2_lut_rep_859_3_lut_3_lut_4_lut (.A(n824[1]), .B(n110949), 
         .C(n829[1]), .D(n110940), .Z(n110917)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5096_2_lut_rep_859_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i5544_3_lut_4_lut_3_lut_4_lut (.A(n885[1]), .B(n110662), .C(n893[1]), 
         .D(n110653), .Z(n901[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5544_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5522_2_lut_4_lut_4_lut (.A(n110663), .B(n892[3]), .C(n893[1]), 
         .D(n110652), .Z(n901[0])) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5522_2_lut_4_lut_4_lut.init = 16'h332c;
    LUT4 i5081_2_lut_rep_869_4_lut_4_lut (.A(n828[3]), .B(n110950), .C(n829[1]), 
         .D(n110939), .Z(n110927)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5081_2_lut_rep_869_4_lut_4_lut.init = 16'h554a;
    LUT4 i6194_2_lut_rep_586_4_lut_4_lut (.A(n110664), .B(n891[3]), .C(n892[1]), 
         .D(n892[2]), .Z(n110644)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6194_2_lut_rep_586_4_lut_4_lut.init = 16'h332c;
    LUT4 i3058_2_lut_rep_877_3_lut (.A(bcd_code_31__N_1306), .B(n110951), 
         .C(bcd_code_31__N_1366), .Z(n110935)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3058_2_lut_rep_877_3_lut.init = 16'hf6f6;
    LUT4 i6566_3_lut_4_lut (.A(bcd_code_31__N_1306), .B(n110951), .C(bcd_code_31__N_1366), 
         .D(n110928), .Z(n839[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6566_3_lut_4_lut.init = 16'h6966;
    LUT4 i13220_3_lut_rep_886 (.A(n5948), .B(bcd_code_31__N_960), .C(n110966), 
         .Z(n110944)) /* synthesis lut_function=(A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13220_3_lut_rep_886.init = 16'ha8a8;
    LUT4 i6209_2_lut_3_lut_3_lut_4_lut (.A(n110664), .B(n891[3]), .C(n892[1]), 
         .D(n892[2]), .Z(n900[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6209_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2589_2_lut_rep_879_3_lut (.A(n110966), .B(n5948), .C(n110946), 
         .Z(n110937)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i2589_2_lut_rep_879_3_lut.init = 16'hf6f6;
    LUT4 i6216_3_lut_rep_570_4_lut_3_lut_4_lut (.A(n110664), .B(n891[3]), 
         .C(n892[1]), .D(n892[2]), .Z(n110628)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6216_3_lut_rep_570_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i13153_2_lut_rep_864_3_lut_4_lut (.A(n110966), .B(n5948), .C(n5546), 
         .D(n110946), .Z(n110922)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (B (C)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i13153_2_lut_rep_864_3_lut_4_lut.init = 16'hf060;
    LUT4 i5614_3_lut_4_lut (.A(n110966), .B(n5948), .C(n110946), .D(n5546), 
         .Z(n831[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(48[24:48])
    defparam i5614_3_lut_4_lut.init = 16'h6966;
    LUT4 i13754_2_lut_rep_873_3_lut_4_lut (.A(n820[1]), .B(n110960), .C(n825[1]), 
         .D(n110948), .Z(n110931)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13754_2_lut_rep_873_3_lut_4_lut.init = 16'hf600;
    LUT4 i6265_2_lut_rep_866_3_lut_3_lut_4_lut (.A(n820[1]), .B(n110960), 
         .C(n825[1]), .D(n110948), .Z(n110924)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6265_2_lut_rep_866_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i6272_3_lut_4_lut_3_lut_4_lut (.A(n820[1]), .B(n110960), .C(n825[1]), 
         .D(n110948), .Z(n830[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6272_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i2994_3_lut_rep_880_4_lut (.A(n820[1]), .B(n110960), .C(n825[1]), 
         .D(n110948), .Z(n110938)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i2994_3_lut_rep_880_4_lut.init = 16'hf666;
    LUT4 i4935_3_lut_rep_908_4_lut_3_lut_4_lut (.A(bcd_code_31__N_965), .B(n110996), 
         .C(n816[1]), .D(n110989), .Z(n110966)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4935_3_lut_rep_908_4_lut_3_lut_4_lut.init = 16'h9666;
    PFUMX i102557 (.BLUT(n111987), .ALUT(n111988), .C0(n110905), .Z(n110749));
    LUT4 i6202_3_lut_4_lut (.A(n110664), .B(n891[3]), .C(n892[1]), .D(n892[2]), 
         .Z(n900[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(50[24:48])
    defparam i6202_3_lut_4_lut.init = 16'h998a;
    LUT4 i6250_2_lut_rep_874_4_lut_4_lut (.A(n824[3]), .B(n110954), .C(n825[1]), 
         .D(n110947), .Z(n110932)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6250_2_lut_rep_874_4_lut_4_lut.init = 16'h554a;
    LUT4 i75819_4_lut_4_lut (.A(n110547), .B(rst_n_c), .C(n83379), .D(n110531), 
         .Z(n83327)) /* synthesis lut_function=(!(A (B (D))+!A (B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75819_4_lut_4_lut.init = 16'h37bf;
    LUT4 i2578_2_lut_rep_882_3_lut (.A(n823[3]), .B(n110955), .C(n828[3]), 
         .Z(n110940)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2578_2_lut_rep_882_3_lut.init = 16'hf6f6;
    LUT4 i5089_3_lut_4_lut (.A(n823[3]), .B(n110955), .C(n828[3]), .D(n110933), 
         .Z(n834[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i5089_3_lut_4_lut.init = 16'h6966;
    LUT4 i3019_4_lut (.A(\lux[11] ), .B(bcd_code_31__N_1589), .C(bcd_code_31__N_1593), 
         .D(n110994), .Z(n5956)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3019_4_lut.init = 16'hfcec;
    LUT4 i4739_3_lut_rep_575_4_lut_3_lut_4_lut (.A(n110667), .B(n897[3]), 
         .C(n898[1]), .D(n898[2]), .Z(n110633)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4739_3_lut_rep_575_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4732_2_lut_3_lut_3_lut_4_lut (.A(n110667), .B(n897[3]), .C(n898[1]), 
         .D(n898[2]), .Z(n907[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4732_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i4717_2_lut_rep_583_4_lut_4_lut (.A(n110667), .B(n897[3]), .C(n898[1]), 
         .D(n898[2]), .Z(n110641)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4717_2_lut_rep_583_4_lut_4_lut.init = 16'h332c;
    LUT4 i3071_2_lut_rep_890_3_lut (.A(n819[3]), .B(n110959), .C(n824[3]), 
         .Z(n110948)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3071_2_lut_rep_890_3_lut.init = 16'hf6f6;
    LUT4 i6258_3_lut_4_lut (.A(n819[3]), .B(n110959), .C(n824[3]), .D(n110938), 
         .Z(n830[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6258_3_lut_4_lut.init = 16'h6966;
    LUT4 i4725_3_lut_4_lut (.A(n110667), .B(n897[3]), .C(n898[1]), .D(n898[2]), 
         .Z(n907[1])) /* synthesis lut_function=(A (B+!(C+(D)))+!A !(B+!(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i4725_3_lut_4_lut.init = 16'h998a;
    LUT4 i13805_2_lut_rep_883_3_lut_4_lut (.A(n823[1]), .B(n110963), .C(n828[1]), 
         .D(n110957), .Z(n110941)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13805_2_lut_rep_883_3_lut_4_lut.init = 16'hf600;
    LUT4 i5208_2_lut_rep_876_3_lut_3_lut_4_lut (.A(n823[1]), .B(n110963), 
         .C(n828[1]), .D(n110957), .Z(n110934)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5208_2_lut_rep_876_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2943_3_lut_rep_893_4_lut (.A(n823[1]), .B(n110963), .C(n828[1]), 
         .D(n110957), .Z(n110951)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i2943_3_lut_rep_893_4_lut.init = 16'hf666;
    LUT4 i5215_3_lut_4_lut_3_lut_4_lut (.A(n823[1]), .B(n110963), .C(n828[1]), 
         .D(n110957), .Z(n833[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5215_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i5193_2_lut_rep_884_4_lut_4_lut (.A(bcd_code_31__N_1306), .B(n110964), 
         .C(n828[1]), .D(n110956), .Z(n110942)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i5193_2_lut_rep_884_4_lut_4_lut.init = 16'h554a;
    LUT4 i2935_3_lut_4_lut (.A(n110675), .B(n110670), .C(bcd_code_31__N_1394), 
         .D(bcd_code_31__N_1392), .Z(n5324)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i2935_3_lut_4_lut.init = 16'hffe0;
    LUT4 i5012_2_lut_rep_578_3_lut_4_lut (.A(n110675), .B(n110670), .C(bcd_code_31__N_1394), 
         .D(n5324), .Z(n110636)) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam i5012_2_lut_rep_578_3_lut_4_lut.init = 16'h1ef0;
    LUT4 i2954_4_lut (.A(\lux[12] ), .B(bcd_code_31__N_1520), .C(bcd_code_31__N_1524), 
         .D(n111006), .Z(n5470)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2954_4_lut.init = 16'hfcec;
    LUT4 i5530_3_lut_4_lut (.A(n110685), .B(n110671), .C(n892[3]), .D(n110647), 
         .Z(n901[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5530_3_lut_4_lut.init = 16'h6966;
    LUT4 i5535_2_lut_rep_595_3_lut (.A(n110685), .B(n110671), .C(n892[3]), 
         .Z(n110653)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(52[24:48])
    defparam i5535_2_lut_rep_595_3_lut.init = 16'hf6f6;
    LUT4 i5606_2_lut_rep_865_4_lut_4_lut (.A(n110968), .B(n110967), .C(n820[1]), 
         .D(n5546), .Z(n110923)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(B (D)+!B !(D))) */ ;
    defparam i5606_2_lut_rep_865_4_lut_4_lut.init = 16'h936c;
    LUT4 i13751_2_lut_rep_891_3_lut_4_lut (.A(n819[1]), .B(n110969), .C(n824[1]), 
         .D(n110962), .Z(n110949)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i13751_2_lut_rep_891_3_lut_4_lut.init = 16'hf600;
    LUT4 i6293_2_lut_rep_881_3_lut_3_lut_4_lut (.A(n819[1]), .B(n110969), 
         .C(n824[1]), .D(n110962), .Z(n110939)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6293_2_lut_rep_881_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2999_3_lut_rep_897_4_lut (.A(n819[1]), .B(n110969), .C(n824[1]), 
         .D(n110962), .Z(n110955)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i2999_3_lut_rep_897_4_lut.init = 16'hf666;
    LUT4 i6300_3_lut_4_lut_3_lut_4_lut (.A(n819[1]), .B(n110969), .C(n824[1]), 
         .D(n110962), .Z(n829[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6300_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i6474_2_lut_4_lut_4_lut (.A(n890[3]), .B(n110683), .C(n891[1]), 
         .D(n891[2]), .Z(n899[0])) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6474_2_lut_4_lut_4_lut.init = 16'h554a;
    LUT4 i6278_2_lut_rep_892_4_lut_4_lut (.A(n823[3]), .B(n110970), .C(n824[1]), 
         .D(n110961), .Z(n110950)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6278_2_lut_rep_892_4_lut_4_lut.init = 16'h554a;
    LUT4 i3020_4_lut (.A(\lux[13] ), .B(bcd_code_31__N_1451), .C(bcd_code_31__N_1455), 
         .D(n111016), .Z(n5988)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3020_4_lut.init = 16'hfcec;
    LUT4 i6776_3_lut_4_lut_3_lut_4_lut (.A(n815[1]), .B(n110991), .C(n819[1]), 
         .D(n110984), .Z(n824[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6776_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i3066_2_lut_rep_899_3_lut (.A(bcd_code_31__N_1246), .B(n110971), 
         .C(bcd_code_31__N_1306), .Z(n110957)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3066_2_lut_rep_899_3_lut.init = 16'hf6f6;
    LUT4 i5201_3_lut_4_lut (.A(bcd_code_31__N_1246), .B(n110971), .C(bcd_code_31__N_1306), 
         .D(n110951), .Z(n833[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i5201_3_lut_4_lut.init = 16'h6966;
    LUT4 i4556_2_lut_rep_591_4_lut_4_lut (.A(bcd_code_31__N_2066), .B(n110672), 
         .C(n905[1]), .D(n905[2]), .Z(n110649)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i4556_2_lut_rep_591_4_lut_4_lut.init = 16'h554a;
    LUT4 i3024_3_lut_rep_918_4_lut (.A(n815[1]), .B(n110991), .C(n819[1]), 
         .D(n110984), .Z(n110976)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3024_3_lut_rep_918_4_lut.init = 16'hf666;
    LUT4 i4578_3_lut_4_lut_3_lut_4_lut (.A(bcd_code_31__N_2066), .B(n110672), 
         .C(n905[1]), .D(n905[2]), .Z(n914[3])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i4578_3_lut_4_lut_3_lut_4_lut.init = 16'h1fe0;
    LUT4 i4571_2_lut_3_lut_3_lut_4_lut (.A(bcd_code_31__N_2066), .B(n110672), 
         .C(n905[1]), .D(n905[2]), .Z(n914[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i4571_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i2976_4_lut_then_4_lut (.A(n6268), .B(n6264), .C(n110905), .D(n110788), 
         .Z(n111283)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A !((C)+!B)) */ ;
    defparam i2976_4_lut_then_4_lut.init = 16'hac0c;
    LUT4 i4564_3_lut_4_lut (.A(bcd_code_31__N_2066), .B(n110672), .C(n905[1]), 
         .D(n905[2]), .Z(n914[1])) /* synthesis lut_function=(A (B)+!A !(B (C+(D))+!B !(D))) */ ;
    defparam i4564_3_lut_4_lut.init = 16'h998c;
    LUT4 i3021_3_lut_rep_901_4_lut (.A(n816[1]), .B(n110982), .C(n820[1]), 
         .D(n110968), .Z(n110959)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3021_3_lut_rep_901_4_lut.init = 16'hf666;
    LUT4 i6741_2_lut_rep_889_3_lut_3_lut_4_lut (.A(n816[1]), .B(n110982), 
         .C(n820[1]), .D(n110968), .Z(n110947)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6741_2_lut_rep_889_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i2949_4_lut (.A(\lux[14] ), .B(bcd_code_31__N_1367), .C(bcd_code_31__N_1371), 
         .D(n111026), .Z(n5369)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2949_4_lut.init = 16'hfcec;
    LUT4 i6748_3_lut_rep_888_4_lut_3_lut_4_lut (.A(n816[1]), .B(n110982), 
         .C(n820[1]), .D(n110968), .Z(n110946)) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6748_3_lut_rep_888_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i13818_2_lut_rep_902_4_lut (.A(n816[1]), .B(n110982), .C(n820[1]), 
         .D(n110968), .Z(n110960)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i13818_2_lut_rep_902_4_lut.init = 16'hf600;
    LUT4 i6726_2_lut_rep_896_4_lut_4_lut (.A(n819[3]), .B(n110975), .C(n820[1]), 
         .D(n110967), .Z(n110954)) /* synthesis lut_function=(!(A (C+(D))+!A !(B (C+(D))+!B (D)))) */ ;
    defparam i6726_2_lut_rep_896_4_lut_4_lut.init = 16'h554a;
    LUT4 i75671_4_lut_4_lut_4_lut (.A(n110545), .B(rst_n_c), .C(n110559), 
         .D(n110547), .Z(n16541)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(35[7] 61[5])
    defparam i75671_4_lut_4_lut_4_lut.init = 16'h7ff7;
    LUT4 i2976_4_lut_else_4_lut (.A(n6268), .B(n6264), .C(n110905), .D(n110788), 
         .Z(n111282)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(B (C+(D))+!B (C)))) */ ;
    defparam i2976_4_lut_else_4_lut.init = 16'h5c50;
    LUT4 i3073_2_lut_rep_904_3_lut (.A(n818[3]), .B(n110976), .C(n823[3]), 
         .Z(n110962)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i3073_2_lut_rep_904_3_lut.init = 16'hf6f6;
    LUT4 i6286_3_lut_4_lut (.A(n818[3]), .B(n110976), .C(n823[3]), .D(n110955), 
         .Z(n829[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6286_3_lut_4_lut.init = 16'h6966;
    LUT4 i3011_4_lut (.A(\lux[15] ), .B(bcd_code_31__N_1307), .C(bcd_code_31__N_1311), 
         .D(n111037), .Z(n5883)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i3011_4_lut.init = 16'hfcec;
    LUT4 i8219_2_lut_4_lut (.A(n5695), .B(bcd_code_31__N_1384), .C(n110701), 
         .D(n110749), .Z(n12231)) /* synthesis lut_function=(A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i8219_2_lut_4_lut.init = 16'ha800;
    LUT4 bcd_code_31__N_1039_bdd_3_lut_4_lut_3_lut_4_lut (.A(n110979), .B(n111044), 
         .C(n826[3]), .D(bcd_code_31__N_1042), .Z(n110275)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (C)) */ ;
    defparam bcd_code_31__N_1039_bdd_3_lut_4_lut_3_lut_4_lut.init = 16'hf070;
    LUT4 i6769_2_lut_rep_903_3_lut_3_lut_4_lut (.A(n815[1]), .B(n110991), 
         .C(n819[1]), .D(n110984), .Z(n110961)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(44[24:48])
    defparam i6769_2_lut_rep_903_3_lut_3_lut_4_lut.init = 16'h06f0;
    LUT4 i3383_2_lut_rep_847_4_lut (.A(n110979), .B(n111044), .C(n826[3]), 
         .D(bcd_code_31__N_1042), .Z(n110905)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i3383_2_lut_rep_847_4_lut.init = 16'h8880;
    LUT4 i5005_3_lut_4_lut (.A(n110701), .B(n5695), .C(n110675), .D(n5324), 
         .Z(n894[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i5005_3_lut_4_lut.init = 16'h6966;
    LUT4 i7944_3_lut_4_lut (.A(n110979), .B(n111044), .C(n4_adj_2346), 
         .D(n826[3]), .Z(n6264)) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i7944_3_lut_4_lut.init = 16'h7888;
    LUT4 mux_9090_i3_4_lut_4_lut (.A(n110979), .B(n111044), .C(n4_adj_2321), 
         .D(n110930), .Z(n826[3])) /* synthesis lut_function=(!(A (B (C)+!B !(D))+!A !(D))) */ ;
    defparam mux_9090_i3_4_lut_4_lut.init = 16'h7f08;
    LUT4 i13831_2_lut_rep_587_3_lut_4_lut (.A(n110701), .B(n5695), .C(n5324), 
         .D(n110675), .Z(n110645)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (B (C)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i13831_2_lut_rep_587_3_lut_4_lut.init = 16'hf060;
    LUT4 i6734_3_lut_4_lut (.A(n815[3]), .B(n110981), .C(n819[3]), .D(n110959), 
         .Z(n825[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+!(D)))+!A !(B (C+!(D))+!B !(C+!(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i6734_3_lut_4_lut.init = 16'h6966;
    LUT4 i3167_2_lut_rep_603_3_lut (.A(n110701), .B(n5695), .C(n110675), 
         .Z(n110661)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(54[24:48])
    defparam i3167_2_lut_rep_603_3_lut.init = 16'hf6f6;
    LUT4 i3081_2_lut_rep_910_3_lut (.A(n815[3]), .B(n110981), .C(n819[3]), 
         .Z(n110968)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(46[24:48])
    defparam i3081_2_lut_rep_910_3_lut.init = 16'hf6f6;
    LUT4 i2929_4_lut (.A(\lux[16] ), .B(bcd_code_31__N_1247), .C(bcd_code_31__N_1251), 
         .D(n111050), .Z(n5225)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2929_4_lut.init = 16'hfcec;
    LUT4 i6489_2_lut_3_lut_3_lut_4_lut (.A(n890[3]), .B(n110683), .C(n891[1]), 
         .D(n891[2]), .Z(n899[2])) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C)))) */ ;
    defparam i6489_2_lut_3_lut_3_lut_4_lut.init = 16'h1e10;
    LUT4 i13733_2_lut_rep_905_3_lut_4_lut (.A(n818[1]), .B(n110985), .C(n823[1]), 
         .D(n110978), .Z(n110963)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (B (D)+!B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i13733_2_lut_rep_905_3_lut_4_lut.init = 16'hf600;
    PFUMX i102178 (.BLUT(GND_net), .ALUT(GND_net), .C0(\lux[29] ), .Z(n5465));
    LUT4 i3003_3_lut_rep_913_4_lut (.A(n818[1]), .B(n110985), .C(n823[1]), 
         .D(n110978), .Z(n110971)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3003_3_lut_rep_913_4_lut.init = 16'hf666;
    LUT4 i6853_2_lut_rep_919_3_lut_3_lut_4_lut (.A(n814[1]), .B(n111003), 
         .C(n818[1]), .D(n111000), .Z(n110977)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6853_2_lut_rep_919_3_lut_3_lut_4_lut.init = 16'h06f0;
    PFUMX i102176 (.BLUT(n111294), .ALUT(n111295), .C0(n5465), .Z(bcd_code_31__N_850));
    LUT4 i6405_2_lut_rep_898_3_lut_3_lut_4_lut (.A(n818[1]), .B(n110985), 
         .C(n823[1]), .D(n110978), .Z(n110956)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B (C (D)+!C !(D))+!B ((D)+!C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6405_2_lut_rep_898_3_lut_3_lut_4_lut.init = 16'h06f0;
    PFUMX i102174 (.BLUT(n111291), .ALUT(n111292), .C0(\lux[29] ), .Z(bcd_code_31__N_842));
    LUT4 i6412_3_lut_4_lut_3_lut_4_lut (.A(n818[1]), .B(n110985), .C(n823[1]), 
         .D(n110978), .Z(n828[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6412_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    LUT4 i3028_3_lut_rep_934_4_lut (.A(n814[1]), .B(n111003), .C(n818[1]), 
         .D(n111000), .Z(n110992)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B+(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i3028_3_lut_rep_934_4_lut.init = 16'hf666;
    LUT4 i6860_3_lut_4_lut_3_lut_4_lut (.A(n814[1]), .B(n111003), .C(n818[1]), 
         .D(n111000), .Z(n823[3])) /* synthesis lut_function=(A (B (C (D))+!B !(C (D)))+!A !(B (C (D))+!B !(C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6860_3_lut_4_lut_3_lut_4_lut.init = 16'h9666;
    PFUMX i102172 (.BLUT(GND_net), .ALUT(n111289), .C0(\lux_31__N_511[27] ), 
          .Z(bcd_code_31__N_846));
    LUT4 i2950_4_lut (.A(\lux[17] ), .B(bcd_code_31__N_1181), .C(bcd_code_31__N_1185), 
         .D(n111059), .Z(n5401)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2950_4_lut.init = 16'hfcec;
    LUT4 i7034_2_lut_rep_1054_4_lut_4_lut_1_lut (.A(\lux[29] ), .Z(n111112)) /* synthesis lut_function=(A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(40[24:48])
    defparam i7034_2_lut_rep_1054_4_lut_4_lut_1_lut.init = 16'haaaa;
    PFUMX i102170 (.BLUT(n111285), .ALUT(n111286), .C0(bcd_code_31__N_960), 
          .Z(n5948));
    LUT4 i6390_2_lut_rep_906_4_lut_4_lut (.A(n110986), .B(bcd_code_31__N_1246), 
         .C(n823[1]), .D(n110977), .Z(n110964)) /* synthesis lut_function=(!(A (B (C+(D))+!B !(C+(D)))+!A (B (C+(D))+!B !(D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/bin_to_bcd.v(42[24:48])
    defparam i6390_2_lut_rep_906_4_lut_4_lut.init = 16'h332c;
    PFUMX i102168 (.BLUT(n111282), .ALUT(n111283), .C0(bcd_code_31__N_797), 
          .Z(n5653));
    
endmodule
//
// Verilog Description of module segment_scan
//

module segment_scan (clk_c, seg_din_c, seg_rck_c, n110534, rst_n_c, 
            n110536, n110535, seg_sck_c, n16584, n14, \lux_data[31] , 
            n7, n14_adj_1, n83303, n14_adj_2, n7_adj_3, n14_adj_4, 
            n16456, n107662, n14_adj_5, n14_adj_6, n16726, \lux_data[27] , 
            n7_adj_7, n14_adj_8, n83313, n14_adj_9, n16625, n14_adj_10, 
            n7_adj_11, n14_adj_12, n14_adj_13, n107670, n14_adj_14, 
            n7_adj_15, n14_adj_16, \lux_data[23] , n16601, n14_adj_17, 
            n83307, n14_adj_18, n7_adj_19, n14_adj_20, n16471, n107668, 
            n14_adj_21, n14_adj_22, n16738, \lux_data[19] , n7_adj_23, 
            n14_adj_24, n83319, n14_adj_25, n7_adj_26, n14_adj_27, 
            n16300, n14_adj_28, n14_adj_29, n107675, n14_adj_30, \lux_data[15] , 
            n83415, n16351, n7_adj_31, n14_adj_32, \lux_data[11] , 
            n83327, n14_adj_33, n7_adj_34, n14_adj_35, n16565, n14_adj_36, 
            n16541, n107666, n14_adj_37, n14_adj_38, n16700, \lux_data[7] , 
            n16558, n14_adj_39, n7_adj_40, n14_adj_41, n83413, n14_adj_42, 
            n7_adj_43, n14_adj_44, n14_adj_45, n107664, n14_adj_46, 
            n16550, n14_adj_47, \lux_data[3] , n7_adj_48, n14_adj_49, 
            n83295, n14_adj_50, n7_adj_51, n14_adj_52, n16428, n107610, 
            n14_adj_53, n14_adj_54, n110487, n110480, n110481, n110482, 
            n110476, n110475, n110478, n110497, n110491, n110490, 
            n110489, n110484, n110485, n110486, n110494, n110496, 
            n110495, n110493, GND_net, n110582, n110568, n110567, 
            n110566, n110556, n110557, n110558, n110506, n110507, 
            n110508, bcd_code_31__N_2138, n110591, n110592, n110524, 
            n110515, n110514, n110513, n110503, n110504, n110505, 
            n110523, n110522, n110521, n110520, n110817, n110581, 
            n110580, n110578, n110559, n110545, n110547, n110546, 
            n110533, n110532, n110530) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output seg_din_c;
    output seg_rck_c;
    input n110534;
    input rst_n_c;
    input n110536;
    input n110535;
    output seg_sck_c;
    input n16584;
    input n14;
    input \lux_data[31] ;
    input n7;
    input n14_adj_1;
    input n83303;
    input n14_adj_2;
    input n7_adj_3;
    input n14_adj_4;
    input n16456;
    input n107662;
    input n14_adj_5;
    input n14_adj_6;
    input n16726;
    input \lux_data[27] ;
    input n7_adj_7;
    input n14_adj_8;
    input n83313;
    input n14_adj_9;
    input n16625;
    input n14_adj_10;
    input n7_adj_11;
    input n14_adj_12;
    input n14_adj_13;
    input n107670;
    input n14_adj_14;
    input n7_adj_15;
    input n14_adj_16;
    input \lux_data[23] ;
    input n16601;
    input n14_adj_17;
    input n83307;
    input n14_adj_18;
    input n7_adj_19;
    input n14_adj_20;
    input n16471;
    input n107668;
    input n14_adj_21;
    input n14_adj_22;
    input n16738;
    input \lux_data[19] ;
    input n7_adj_23;
    input n14_adj_24;
    input n83319;
    input n14_adj_25;
    input n7_adj_26;
    input n14_adj_27;
    input n16300;
    input n14_adj_28;
    input n14_adj_29;
    input n107675;
    input n14_adj_30;
    input \lux_data[15] ;
    input n83415;
    input n16351;
    input n7_adj_31;
    input n14_adj_32;
    input \lux_data[11] ;
    input n83327;
    input n14_adj_33;
    input n7_adj_34;
    input n14_adj_35;
    input n16565;
    input n14_adj_36;
    input n16541;
    input n107666;
    input n14_adj_37;
    input n14_adj_38;
    input n16700;
    input \lux_data[7] ;
    input n16558;
    input n14_adj_39;
    input n7_adj_40;
    input n14_adj_41;
    input n83413;
    input n14_adj_42;
    input n7_adj_43;
    input n14_adj_44;
    input n14_adj_45;
    input n107664;
    input n14_adj_46;
    input n16550;
    input n14_adj_47;
    input \lux_data[3] ;
    input n7_adj_48;
    input n14_adj_49;
    input n83295;
    input n14_adj_50;
    input n7_adj_51;
    input n14_adj_52;
    input n16428;
    input n107610;
    input n14_adj_53;
    input n14_adj_54;
    input n110487;
    input n110480;
    input n110481;
    input n110482;
    input n110476;
    input n110475;
    input n110478;
    input n110497;
    input n110491;
    input n110490;
    input n110489;
    input n110484;
    input n110485;
    input n110486;
    input n110494;
    input n110496;
    input n110495;
    input n110493;
    input GND_net;
    input n110582;
    input n110568;
    input n110567;
    input n110566;
    input n110556;
    input n110557;
    input n110558;
    input n110506;
    input n110507;
    input n110508;
    input bcd_code_31__N_2138;
    input n110591;
    input n110592;
    input n110524;
    input n110515;
    input n110514;
    input n110513;
    input n110503;
    input n110504;
    input n110505;
    input n110523;
    input n110522;
    input n110521;
    input n110520;
    input n110817;
    input n110581;
    input n110580;
    input n110578;
    input n110559;
    input n110545;
    input n110547;
    input n110546;
    input n110533;
    input n110532;
    input n110530;
    
    wire clk_40khz /* synthesis is_clock=1, SET_AS_NETWORK=\u4/clk_40khz */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(75[5:14])
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/prox_detect.v(19[12:15])
    wire [15:0]data;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(83[14:18])
    
    wire clk_40khz_enable_29, n22865, n17522, n22868, n111257;
    wire [2:0]state;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(86[14:19])
    
    wire n109119, clk_40khz_N_2239;
    wire [9:0]cnt;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(67[11:14])
    
    wire cnt_9__N_2199;
    wire [9:0]n45;
    
    wire clk_40khz_enable_4, seg_din_N_2237, clk_40khz_enable_5, seg_rck_N_2232, 
        n17506, n14_c, n17540, clk_40khz_enable_9, n22862, n20969;
    wire [5:0]cnt_write;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(85[13:22])
    
    wire clk_40khz_enable_26, n22858;
    wire [5:0]n320;
    wire [2:0]cnt_main;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(84[13:21])
    
    wire clk_40khz_enable_27, n22855;
    wire [2:0]cnt_main_2__N_2207;
    
    wire n7_c, n109605, n109606, seg_din_N_2238;
    wire [15:0]data_15__N_2216;
    
    wire clk_40khz_enable_24, seg_sck_N_2235, seg_rck_N_2234, n109570, 
        n109571, n109574, n109618, n109619, n109622, n109632, n109633, 
        n109636, n109639, n109640, n109643, n109646, n109647, n109650, 
        n22872;
    wire [6:0]n165;
    wire [6:0]n182;
    
    wire n109577, n109578, n109581, n109625, n109626, n109629, n14_adj_2244, 
        n7_adj_2248, n7_adj_2250, n7_adj_2252, n7_adj_2259;
    wire [6:0]n199;
    wire [6:0]n216;
    
    wire n7_adj_2268, n7_adj_2270, n7_adj_2272, n7_adj_2279, n109572, 
        n109573, n109575, n109620, n109621, n109623, n109634, n109635, 
        n109637, n109641, n109642, n109644, n109648, n109649, n109651;
    wire [6:0]n233;
    wire [6:0]n250;
    
    wire n109579, n109580, n109582, n109627, n109628, n109630, n16576, 
        n14_adj_2282, n7_adj_2283, n14_adj_2284, n7_adj_2285, n107606, 
        n14_adj_2286, n7_adj_2287, n14_adj_2288, n7_adj_2295, n7_adj_2297;
    wire [6:0]n267;
    wire [6:0]n284;
    
    wire n7_adj_2299, n7_adj_2306, n7_adj_2315, n7_adj_2317, n109600, 
        n109599, n109598, n109597, n109309, n109311, n109596, n109595, 
        n109594, n109593, n111216, n107554, n83125, n4, n8, n106967, 
        n106966, n106965, n106964, n106963, n111218, n7_adj_2319, 
        n111246, n111252, n8_adj_2320, n109601, n109602, n109603, 
        n109604;
    
    FD1P3JX data_i0_i6 (.D(n17522), .SP(clk_40khz_enable_29), .PD(n22865), 
            .CK(clk_40khz), .Q(data[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i6.GSR = "DISABLED";
    FD1P3JX data_i0_i5 (.D(n111257), .SP(clk_40khz_enable_29), .PD(n22868), 
            .CK(clk_40khz), .Q(data[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i5.GSR = "DISABLED";
    FD1P3JX data_i0_i4 (.D(n111257), .SP(clk_40khz_enable_29), .PD(n22865), 
            .CK(clk_40khz), .Q(data[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i4.GSR = "DISABLED";
    FD1S3AX state_i0 (.D(n109119), .CK(clk_40khz), .Q(state[0])) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam state_i0.GSR = "ENABLED";
    FD1S3AX clk_40khz_68 (.D(clk_40khz_N_2239), .CK(clk_c), .Q(clk_40khz)) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(78[7] 79[25])
    defparam clk_40khz_68.GSR = "ENABLED";
    FD1S3IX cnt_2399__i0 (.D(n45[0]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i0.GSR = "ENABLED";
    FD1P3AX seg_din_72 (.D(seg_din_N_2237), .SP(clk_40khz_enable_4), .CK(clk_40khz), 
            .Q(seg_din_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam seg_din_72.GSR = "ENABLED";
    FD1P3AX seg_rck_74 (.D(seg_rck_N_2232), .SP(clk_40khz_enable_5), .CK(clk_40khz), 
            .Q(seg_rck_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam seg_rck_74.GSR = "ENABLED";
    FD1P3JX data_i0_i3 (.D(n17506), .SP(clk_40khz_enable_29), .PD(n22868), 
            .CK(clk_40khz), .Q(data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i3.GSR = "DISABLED";
    FD1P3JX data_i0_i2 (.D(n17506), .SP(clk_40khz_enable_29), .PD(n22865), 
            .CK(clk_40khz), .Q(data[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i2.GSR = "DISABLED";
    LUT4 i75697_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), 
         .C(n110536), .D(n110535), .Z(n14_c)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75697_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hff7f;
    FD1P3JX data_i0_i1 (.D(n17540), .SP(clk_40khz_enable_29), .PD(n22868), 
            .CK(clk_40khz), .Q(data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i1.GSR = "DISABLED";
    FD1P3IX state_i1 (.D(n20969), .SP(clk_40khz_enable_9), .CD(n22862), 
            .CK(clk_40khz), .Q(state[1])) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam state_i1.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i5 (.D(n320[5]), .SP(clk_40khz_enable_26), .CD(n22858), 
            .CK(clk_40khz), .Q(cnt_write[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i5.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i4 (.D(n320[4]), .SP(clk_40khz_enable_26), .CD(n22858), 
            .CK(clk_40khz), .Q(cnt_write[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i4.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i3 (.D(n320[3]), .SP(clk_40khz_enable_26), .CD(n22858), 
            .CK(clk_40khz), .Q(cnt_write[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i2 (.D(n320[2]), .SP(clk_40khz_enable_26), .CD(n22858), 
            .CK(clk_40khz), .Q(cnt_write[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i1 (.D(n320[1]), .SP(clk_40khz_enable_26), .CD(n22858), 
            .CK(clk_40khz), .Q(cnt_write[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i2 (.D(cnt_main_2__N_2207[2]), .SP(clk_40khz_enable_27), 
            .CD(n22855), .CK(clk_40khz), .Q(cnt_main[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_main_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i1 (.D(cnt_main_2__N_2207[1]), .SP(clk_40khz_enable_27), 
            .CD(n22855), .CK(clk_40khz), .Q(cnt_main[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_main_i0_i1.GSR = "ENABLED";
    LUT4 i75698_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), 
         .C(n110536), .D(n110535), .Z(n7_c)) /* synthesis lut_function=(!(A (B)+!A !(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75698_2_lut_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'h7737;
    FD1S3IX cnt_2399__i1 (.D(n45[1]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i1.GSR = "ENABLED";
    FD1S3IX cnt_2399__i2 (.D(n45[2]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i2.GSR = "ENABLED";
    FD1S3IX cnt_2399__i3 (.D(n45[3]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i3.GSR = "ENABLED";
    FD1S3IX cnt_2399__i4 (.D(n45[4]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i4.GSR = "ENABLED";
    FD1S3IX cnt_2399__i5 (.D(n45[5]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i5.GSR = "ENABLED";
    FD1S3IX cnt_2399__i6 (.D(n45[6]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i6.GSR = "ENABLED";
    FD1S3IX cnt_2399__i7 (.D(n45[7]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i7.GSR = "ENABLED";
    FD1S3IX cnt_2399__i8 (.D(n45[8]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i8.GSR = "ENABLED";
    FD1S3IX cnt_2399__i9 (.D(n45[9]), .CK(clk_c), .CD(cnt_9__N_2199), 
            .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399__i9.GSR = "ENABLED";
    L6MUX21 i101519 (.D0(n109605), .D1(n109606), .SD(cnt_write[4]), .Z(seg_din_N_2238));
    FD1P3AX data_i0_i8 (.D(data_15__N_2216[8]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i8.GSR = "DISABLED";
    FD1P3AX data_i0_i9 (.D(data_15__N_2216[9]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i9.GSR = "DISABLED";
    FD1P3AX data_i0_i10 (.D(data_15__N_2216[10]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i10.GSR = "DISABLED";
    FD1P3AX data_i0_i11 (.D(data_15__N_2216[11]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i11.GSR = "DISABLED";
    FD1P3AX data_i0_i12 (.D(data_15__N_2216[12]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i12.GSR = "DISABLED";
    FD1P3AX data_i0_i13 (.D(data_15__N_2216[13]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i13.GSR = "DISABLED";
    FD1P3AX data_i0_i14 (.D(data_15__N_2216[14]), .SP(clk_40khz_enable_29), 
            .CK(clk_40khz), .Q(data[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i14.GSR = "DISABLED";
    FD1P3AX seg_sck_73 (.D(seg_sck_N_2235), .SP(clk_40khz_enable_24), .CK(clk_40khz), 
            .Q(seg_sck_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam seg_sck_73.GSR = "ENABLED";
    FD1P3JX data_i0_i0 (.D(n17540), .SP(clk_40khz_enable_29), .PD(n22865), 
            .CK(clk_40khz), .Q(data[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i0.GSR = "DISABLED";
    FD1P3IX cnt_write_i0_i0 (.D(seg_rck_N_2234), .SP(clk_40khz_enable_26), 
            .CD(n22858), .CK(clk_40khz), .Q(cnt_write[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_write_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i0 (.D(cnt_main_2__N_2207[0]), .SP(clk_40khz_enable_27), 
            .CD(n22855), .CK(clk_40khz), .Q(cnt_main[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam cnt_main_i0_i0.GSR = "ENABLED";
    L6MUX21 i101486 (.D0(n109570), .D1(n109571), .SD(cnt_main[1]), .Z(n109574));
    L6MUX21 i101534 (.D0(n109618), .D1(n109619), .SD(cnt_main[1]), .Z(n109622));
    L6MUX21 i101548 (.D0(n109632), .D1(n109633), .SD(cnt_main[1]), .Z(n109636));
    L6MUX21 i101555 (.D0(n109639), .D1(n109640), .SD(cnt_main[1]), .Z(n109643));
    L6MUX21 i101562 (.D0(n109646), .D1(n109647), .SD(cnt_main[1]), .Z(n109650));
    FD1P3IX data_i0_i15 (.D(n22872), .SP(clk_40khz_enable_29), .CD(n22868), 
            .CK(clk_40khz), .Q(data[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i15.GSR = "DISABLED";
    L6MUX21 i101482 (.D0(n165[6]), .D1(n182[6]), .SD(cnt_main[0]), .Z(n109570));
    L6MUX21 i101493 (.D0(n109577), .D1(n109578), .SD(cnt_main[1]), .Z(n109581));
    L6MUX21 i101530 (.D0(n165[0]), .D1(n182[0]), .SD(cnt_main[0]), .Z(n109618));
    L6MUX21 i101541 (.D0(n109625), .D1(n109626), .SD(cnt_main[1]), .Z(n109629));
    L6MUX21 i101544 (.D0(n165[3]), .D1(n182[3]), .SD(cnt_main[0]), .Z(n109632));
    L6MUX21 i101551 (.D0(n165[4]), .D1(n182[4]), .SD(cnt_main[0]), .Z(n109639));
    L6MUX21 i101558 (.D0(n165[5]), .D1(n182[5]), .SD(cnt_main[0]), .Z(n109646));
    L6MUX21 i101489 (.D0(n165[1]), .D1(n182[1]), .SD(cnt_main[0]), .Z(n109577));
    L6MUX21 i101537 (.D0(n165[2]), .D1(n182[2]), .SD(cnt_main[0]), .Z(n109625));
    PFUMX mux_19_Mux_0_i15 (.BLUT(n16584), .ALUT(n14), .C0(\lux_data[31] ), 
          .Z(n165[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_19_Mux_6_i15 (.BLUT(n7), .ALUT(n14_adj_1), .C0(\lux_data[31] ), 
          .Z(n165[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    LUT4 i75699_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), .C(n110535), 
         .D(n110536), .Z(n14_adj_2244)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75699_4_lut_4_lut_4_lut.init = 16'hfff7;
    PFUMX mux_19_Mux_5_i15 (.BLUT(n83303), .ALUT(n14_adj_2), .C0(\lux_data[31] ), 
          .Z(n165[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    FD1P3JX data_i0_i7 (.D(n17522), .SP(clk_40khz_enable_29), .PD(n22868), 
            .CK(clk_40khz), .Q(data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam data_i0_i7.GSR = "DISABLED";
    PFUMX mux_19_Mux_4_i15 (.BLUT(n7_adj_3), .ALUT(n14_adj_4), .C0(\lux_data[31] ), 
          .Z(n165[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_19_Mux_3_i15 (.BLUT(n7_adj_2248), .ALUT(n16456), .C0(\lux_data[31] ), 
          .Z(n165[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_19_Mux_2_i15 (.BLUT(n107662), .ALUT(n14_adj_5), .C0(\lux_data[31] ), 
          .Z(n165[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_19_Mux_1_i15 (.BLUT(n7_adj_2250), .ALUT(n14_adj_6), .C0(\lux_data[31] ), 
          .Z(n165[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_3_i15 (.BLUT(n7_adj_2252), .ALUT(n16726), .C0(\lux_data[27] ), 
          .Z(n182[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_4_i15 (.BLUT(n7_adj_7), .ALUT(n14_adj_8), .C0(\lux_data[27] ), 
          .Z(n182[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_5_i15 (.BLUT(n83313), .ALUT(n14_adj_9), .C0(\lux_data[27] ), 
          .Z(n182[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_0_i15 (.BLUT(n16625), .ALUT(n14_adj_10), .C0(\lux_data[27] ), 
          .Z(n182[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_6_i15 (.BLUT(n7_adj_11), .ALUT(n14_adj_12), .C0(\lux_data[27] ), 
          .Z(n182[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_1_i15 (.BLUT(n7_adj_2259), .ALUT(n14_adj_13), .C0(\lux_data[27] ), 
          .Z(n182[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_21_Mux_2_i15 (.BLUT(n107670), .ALUT(n14_adj_14), .C0(\lux_data[27] ), 
          .Z(n182[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    L6MUX21 i101483 (.D0(n199[6]), .D1(n216[6]), .SD(cnt_main[0]), .Z(n109571));
    L6MUX21 i101531 (.D0(n199[0]), .D1(n216[0]), .SD(cnt_main[0]), .Z(n109619));
    L6MUX21 i101545 (.D0(n199[3]), .D1(n216[3]), .SD(cnt_main[0]), .Z(n109633));
    L6MUX21 i101552 (.D0(n199[4]), .D1(n216[4]), .SD(cnt_main[0]), .Z(n109640));
    L6MUX21 i101559 (.D0(n199[5]), .D1(n216[5]), .SD(cnt_main[0]), .Z(n109647));
    L6MUX21 i101490 (.D0(n199[1]), .D1(n216[1]), .SD(cnt_main[0]), .Z(n109578));
    L6MUX21 i101538 (.D0(n199[2]), .D1(n216[2]), .SD(cnt_main[0]), .Z(n109626));
    PFUMX mux_23_Mux_6_i15 (.BLUT(n7_adj_15), .ALUT(n14_adj_16), .C0(\lux_data[23] ), 
          .Z(n199[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_0_i15 (.BLUT(n16601), .ALUT(n14_adj_17), .C0(\lux_data[23] ), 
          .Z(n199[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_5_i15 (.BLUT(n83307), .ALUT(n14_adj_18), .C0(\lux_data[23] ), 
          .Z(n199[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_4_i15 (.BLUT(n7_adj_19), .ALUT(n14_adj_20), .C0(\lux_data[23] ), 
          .Z(n199[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_3_i15 (.BLUT(n7_adj_2268), .ALUT(n16471), .C0(\lux_data[23] ), 
          .Z(n199[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_2_i15 (.BLUT(n107668), .ALUT(n14_adj_21), .C0(\lux_data[23] ), 
          .Z(n199[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_23_Mux_1_i15 (.BLUT(n7_adj_2270), .ALUT(n14_adj_22), .C0(\lux_data[23] ), 
          .Z(n199[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_3_i15 (.BLUT(n7_adj_2272), .ALUT(n16738), .C0(\lux_data[19] ), 
          .Z(n216[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_4_i15 (.BLUT(n7_adj_23), .ALUT(n14_adj_24), .C0(\lux_data[19] ), 
          .Z(n216[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_5_i15 (.BLUT(n83319), .ALUT(n14_adj_25), .C0(\lux_data[19] ), 
          .Z(n216[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_6_i15 (.BLUT(n7_adj_26), .ALUT(n14_adj_27), .C0(\lux_data[19] ), 
          .Z(n216[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_0_i15 (.BLUT(n16300), .ALUT(n14_adj_28), .C0(\lux_data[19] ), 
          .Z(n216[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_1_i15 (.BLUT(n7_adj_2279), .ALUT(n14_adj_29), .C0(\lux_data[19] ), 
          .Z(n216[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_25_Mux_2_i15 (.BLUT(n107675), .ALUT(n14_adj_30), .C0(\lux_data[19] ), 
          .Z(n216[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    L6MUX21 i101487 (.D0(n109572), .D1(n109573), .SD(cnt_main[1]), .Z(n109575));
    L6MUX21 i101535 (.D0(n109620), .D1(n109621), .SD(cnt_main[1]), .Z(n109623));
    L6MUX21 i101549 (.D0(n109634), .D1(n109635), .SD(cnt_main[1]), .Z(n109637));
    L6MUX21 i101556 (.D0(n109641), .D1(n109642), .SD(cnt_main[1]), .Z(n109644));
    L6MUX21 i101563 (.D0(n109648), .D1(n109649), .SD(cnt_main[1]), .Z(n109651));
    L6MUX21 i101484 (.D0(n233[6]), .D1(n250[6]), .SD(cnt_main[0]), .Z(n109572));
    L6MUX21 i101494 (.D0(n109579), .D1(n109580), .SD(cnt_main[1]), .Z(n109582));
    L6MUX21 i101532 (.D0(n233[0]), .D1(n250[0]), .SD(cnt_main[0]), .Z(n109620));
    L6MUX21 i101542 (.D0(n109627), .D1(n109628), .SD(cnt_main[1]), .Z(n109630));
    L6MUX21 i101546 (.D0(n233[3]), .D1(n250[3]), .SD(cnt_main[0]), .Z(n109634));
    L6MUX21 i101553 (.D0(n233[4]), .D1(n250[4]), .SD(cnt_main[0]), .Z(n109641));
    L6MUX21 i101560 (.D0(n233[5]), .D1(n250[5]), .SD(cnt_main[0]), .Z(n109648));
    L6MUX21 i101491 (.D0(n233[1]), .D1(n250[1]), .SD(cnt_main[0]), .Z(n109579));
    L6MUX21 i101539 (.D0(n233[2]), .D1(n250[2]), .SD(cnt_main[0]), .Z(n109627));
    PFUMX mux_27_Mux_0_i15 (.BLUT(n16576), .ALUT(n14_adj_2282), .C0(\lux_data[15] ), 
          .Z(n233[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_6_i15 (.BLUT(n7_adj_2283), .ALUT(n14_adj_2284), .C0(\lux_data[15] ), 
          .Z(n233[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_5_i15 (.BLUT(n83415), .ALUT(n14_c), .C0(\lux_data[15] ), 
          .Z(n233[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_4_i15 (.BLUT(n7_c), .ALUT(n14_adj_2244), .C0(\lux_data[15] ), 
          .Z(n233[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_3_i15 (.BLUT(n7_adj_2285), .ALUT(n16351), .C0(\lux_data[15] ), 
          .Z(n233[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_2_i15 (.BLUT(n107606), .ALUT(n14_adj_2286), .C0(\lux_data[15] ), 
          .Z(n233[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_27_Mux_1_i15 (.BLUT(n7_adj_2287), .ALUT(n14_adj_2288), .C0(\lux_data[15] ), 
          .Z(n233[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_4_i15 (.BLUT(n7_adj_31), .ALUT(n14_adj_32), .C0(\lux_data[11] ), 
          .Z(n250[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_5_i15 (.BLUT(n83327), .ALUT(n14_adj_33), .C0(\lux_data[11] ), 
          .Z(n250[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_6_i15 (.BLUT(n7_adj_34), .ALUT(n14_adj_35), .C0(\lux_data[11] ), 
          .Z(n250[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_0_i15 (.BLUT(n16565), .ALUT(n14_adj_36), .C0(\lux_data[11] ), 
          .Z(n250[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_3_i15 (.BLUT(n7_adj_2295), .ALUT(n16541), .C0(\lux_data[11] ), 
          .Z(n250[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_2_i15 (.BLUT(n107666), .ALUT(n14_adj_37), .C0(\lux_data[11] ), 
          .Z(n250[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_29_Mux_1_i15 (.BLUT(n7_adj_2297), .ALUT(n14_adj_38), .C0(\lux_data[11] ), 
          .Z(n250[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    L6MUX21 i101485 (.D0(n267[6]), .D1(n284[6]), .SD(cnt_main[0]), .Z(n109573));
    L6MUX21 i101533 (.D0(n267[0]), .D1(n284[0]), .SD(cnt_main[0]), .Z(n109621));
    L6MUX21 i101547 (.D0(n267[3]), .D1(n284[3]), .SD(cnt_main[0]), .Z(n109635));
    L6MUX21 i101554 (.D0(n267[4]), .D1(n284[4]), .SD(cnt_main[0]), .Z(n109642));
    L6MUX21 i101561 (.D0(n267[5]), .D1(n284[5]), .SD(cnt_main[0]), .Z(n109649));
    L6MUX21 i101492 (.D0(n267[1]), .D1(n284[1]), .SD(cnt_main[0]), .Z(n109580));
    L6MUX21 i101540 (.D0(n267[2]), .D1(n284[2]), .SD(cnt_main[0]), .Z(n109628));
    PFUMX mux_31_Mux_3_i15 (.BLUT(n7_adj_2299), .ALUT(n16700), .C0(\lux_data[7] ), 
          .Z(n267[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_0_i15 (.BLUT(n16558), .ALUT(n14_adj_39), .C0(\lux_data[7] ), 
          .Z(n267[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_6_i15 (.BLUT(n7_adj_40), .ALUT(n14_adj_41), .C0(\lux_data[7] ), 
          .Z(n267[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_5_i15 (.BLUT(n83413), .ALUT(n14_adj_42), .C0(\lux_data[7] ), 
          .Z(n267[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_4_i15 (.BLUT(n7_adj_43), .ALUT(n14_adj_44), .C0(\lux_data[7] ), 
          .Z(n267[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_1_i15 (.BLUT(n7_adj_2306), .ALUT(n14_adj_45), .C0(\lux_data[7] ), 
          .Z(n267[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_31_Mux_2_i15 (.BLUT(n107664), .ALUT(n14_adj_46), .C0(\lux_data[7] ), 
          .Z(n267[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    LUT4 i75668_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), .C(n110536), 
         .D(n110535), .Z(n16576)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75668_3_lut_4_lut_4_lut_4_lut.init = 16'hffb7;
    PFUMX mux_33_Mux_0_i15 (.BLUT(n16550), .ALUT(n14_adj_47), .C0(\lux_data[3] ), 
          .Z(n284[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_6_i15 (.BLUT(n7_adj_48), .ALUT(n14_adj_49), .C0(\lux_data[3] ), 
          .Z(n284[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_5_i15 (.BLUT(n83295), .ALUT(n14_adj_50), .C0(\lux_data[3] ), 
          .Z(n284[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_4_i15 (.BLUT(n7_adj_51), .ALUT(n14_adj_52), .C0(\lux_data[3] ), 
          .Z(n284[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_3_i15 (.BLUT(n7_adj_2315), .ALUT(n16428), .C0(\lux_data[3] ), 
          .Z(n284[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_2_i15 (.BLUT(n107610), .ALUT(n14_adj_53), .C0(\lux_data[3] ), 
          .Z(n284[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    PFUMX mux_33_Mux_1_i15 (.BLUT(n7_adj_2317), .ALUT(n14_adj_54), .C0(\lux_data[3] ), 
          .Z(n284[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=14, LSE_RCOL=3, LSE_LLINE=56, LSE_RLINE=72 */ ;
    LUT4 i2_3_lut_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), .C(n110536), 
         .D(n110535), .Z(n107606)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i2_3_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hfbff;
    LUT4 mux_27_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut (.A(n110534), 
         .B(rst_n_c), .C(n110535), .D(n110536), .Z(n14_adj_2288)) /* synthesis lut_function=(!(A (B (C))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam mux_27_Mux_1_i14_3_lut_3_lut_4_lut_3_lut_4_lut_4_lut.init = 16'h3b7f;
    LUT4 i101512_3_lut (.A(data[1]), .B(data[0]), .C(cnt_write[1]), .Z(n109600)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101512_3_lut.init = 16'hcaca;
    LUT4 i101511_3_lut (.A(data[3]), .B(data[2]), .C(cnt_write[1]), .Z(n109599)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101511_3_lut.init = 16'hcaca;
    LUT4 i101510_3_lut (.A(data[5]), .B(data[4]), .C(cnt_write[1]), .Z(n109598)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101510_3_lut.init = 16'hcaca;
    LUT4 i101509_3_lut (.A(data[7]), .B(data[6]), .C(cnt_write[1]), .Z(n109597)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101509_3_lut.init = 16'hcaca;
    LUT4 i13696_2_lut (.A(state[1]), .B(state[0]), .Z(n20969)) /* synthesis lut_function=(!(A+!(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(93[3] 160[10])
    defparam i13696_2_lut.init = 16'h4444;
    LUT4 i101827_2_lut (.A(state[0]), .Z(clk_40khz_enable_26)) /* synthesis lut_function=(!(A)) */ ;
    defparam i101827_2_lut.init = 16'h5555;
    LUT4 i101222_2_lut (.A(cnt_write[0]), .B(n109309), .Z(n109311)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i101222_2_lut.init = 16'heeee;
    LUT4 i101508_3_lut (.A(data[9]), .B(data[8]), .C(cnt_write[1]), .Z(n109596)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101508_3_lut.init = 16'hcaca;
    LUT4 i101507_3_lut (.A(data[11]), .B(data[10]), .C(cnt_write[1]), 
         .Z(n109595)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101507_3_lut.init = 16'hcaca;
    LUT4 i101506_3_lut (.A(data[13]), .B(data[12]), .C(cnt_write[1]), 
         .Z(n109594)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101506_3_lut.init = 16'hcaca;
    LUT4 i75784_2_lut_4_lut (.A(n110487), .B(rst_n_c), .C(n110480), .D(n110481), 
         .Z(n7_adj_2250)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(105[37:42])
    defparam i75784_2_lut_4_lut.init = 16'hb7ff;
    LUT4 i101505_3_lut (.A(data[15]), .B(data[14]), .C(cnt_write[1]), 
         .Z(n109593)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101505_3_lut.init = 16'hcaca;
    LUT4 mux_19_Mux_3_i7_4_lut_4_lut (.A(n110482), .B(n110476), .C(n110475), 
         .D(n110478), .Z(n7_adj_2248)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(105[37:42])
    defparam mux_19_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    LUT4 i75821_2_lut_4_lut (.A(n110497), .B(rst_n_c), .C(n110491), .D(n110490), 
         .Z(n7_adj_2259)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(106[37:42])
    defparam i75821_2_lut_4_lut.init = 16'hb7ff;
    LUT4 mux_21_Mux_3_i7_4_lut_4_lut (.A(n110489), .B(n110484), .C(n110485), 
         .D(n110486), .Z(n7_adj_2252)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(106[37:42])
    defparam mux_21_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    LUT4 mux_23_Mux_3_i7_4_lut_4_lut (.A(n110494), .B(n110496), .C(n110495), 
         .D(n110493), .Z(n7_adj_2268)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(107[37:42])
    defparam mux_23_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    LUT4 i10497_2_lut (.A(cnt_main[1]), .B(cnt_main[2]), .Z(n17540)) /* synthesis lut_function=(A+(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i10497_2_lut.init = 16'heeee;
    LUT4 i1_3_lut (.A(state[0]), .B(state[1]), .C(n111216), .Z(n109119)) /* synthesis lut_function=(!(A+!((C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam i1_3_lut.init = 16'h5151;
    LUT4 i101220_4_lut (.A(cnt_write[4]), .B(cnt_write[3]), .C(cnt_write[2]), 
         .D(cnt_write[1]), .Z(n109309)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i101220_4_lut.init = 16'hfffe;
    LUT4 i2_4_lut (.A(cnt[9]), .B(n107554), .C(cnt[8]), .D(cnt[7]), 
         .Z(clk_40khz_N_2239)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut.init = 16'hfefa;
    LUT4 i2_4_lut_adj_191 (.A(cnt[6]), .B(n83125), .C(cnt[5]), .D(cnt[4]), 
         .Z(n107554)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut_adj_191.init = 16'hfefa;
    LUT4 i75629_3_lut (.A(cnt[1]), .B(cnt[3]), .C(cnt[2]), .Z(n83125)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;
    defparam i75629_3_lut.init = 16'hecec;
    LUT4 i2777_4_lut (.A(cnt[7]), .B(cnt[9]), .C(cnt[8]), .D(n4), .Z(cnt_9__N_2199)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2777_4_lut.init = 16'hfcec;
    LUT4 i1_4_lut (.A(cnt[6]), .B(n8), .C(cnt[5]), .D(cnt[4]), .Z(n4)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;
    defparam i1_4_lut.init = 16'hfaea;
    LUT4 i3442_4_lut (.A(cnt[0]), .B(cnt[3]), .C(cnt[2]), .D(cnt[1]), 
         .Z(n8)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i3442_4_lut.init = 16'hc8c0;
    LUT4 i3829_2_lut (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n320[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3829_2_lut.init = 16'h6666;
    LUT4 i2_1_lut (.A(state[1]), .Z(clk_40khz_enable_27)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam i2_1_lut.init = 16'h5555;
    LUT4 i101808_2_lut (.A(state[1]), .B(state[0]), .Z(n22855)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i101808_2_lut.init = 16'h1111;
    LUT4 i3814_3_lut (.A(cnt_main[2]), .B(cnt_main[1]), .C(cnt_main[0]), 
         .Z(cnt_main_2__N_2207[2])) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(100[18:33])
    defparam i3814_3_lut.init = 16'h6a6a;
    LUT4 i3807_2_lut (.A(cnt_main[1]), .B(cnt_main[0]), .Z(cnt_main_2__N_2207[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(100[18:33])
    defparam i3807_2_lut.init = 16'h6666;
    LUT4 i101536_3_lut (.A(n109622), .B(n109623), .C(cnt_main[2]), .Z(data_15__N_2216[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101536_3_lut.init = 16'hcaca;
    LUT4 i101495_3_lut (.A(n109581), .B(n109582), .C(cnt_main[2]), .Z(data_15__N_2216[9])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101495_3_lut.init = 16'hcaca;
    LUT4 i101543_3_lut (.A(n109629), .B(n109630), .C(cnt_main[2]), .Z(data_15__N_2216[10])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101543_3_lut.init = 16'hcaca;
    LUT4 i101550_3_lut (.A(n109636), .B(n109637), .C(cnt_main[2]), .Z(data_15__N_2216[11])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101550_3_lut.init = 16'hcaca;
    LUT4 i101557_3_lut (.A(n109643), .B(n109644), .C(cnt_main[2]), .Z(data_15__N_2216[12])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101557_3_lut.init = 16'hcaca;
    LUT4 i101564_3_lut (.A(n109650), .B(n109651), .C(cnt_main[2]), .Z(data_15__N_2216[13])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101564_3_lut.init = 16'hcaca;
    LUT4 i101488_3_lut (.A(n109574), .B(n109575), .C(cnt_main[2]), .Z(data_15__N_2216[14])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i101488_3_lut.init = 16'hcaca;
    CCU2D cnt_2399_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n106967), .S0(n45[9]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_2399_add_4_11.INIT1 = 16'h0000;
    defparam cnt_2399_add_4_11.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_2399_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106966), 
          .COUT(n106967), .S0(n45[7]), .S1(n45[8]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_2399_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_2399_add_4_9.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_2399_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106965), 
          .COUT(n106966), .S0(n45[5]), .S1(n45[6]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_2399_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_2399_add_4_7.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_7.INJECT1_1 = "NO";
    LUT4 i75812_2_lut_4_lut (.A(n110582), .B(rst_n_c), .C(n110568), .D(n110567), 
         .Z(n7_adj_2306)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(111[37:42])
    defparam i75812_2_lut_4_lut.init = 16'hb7ff;
    LUT4 mux_31_Mux_3_i7_4_lut_4_lut (.A(n110566), .B(n110556), .C(n110557), 
         .D(n110558), .Z(n7_adj_2299)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(111[37:42])
    defparam mux_31_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    CCU2D cnt_2399_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106964), 
          .COUT(n106965), .S0(n45[3]), .S1(n45[4]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_2399_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_2399_add_4_5.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_2399_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n106963), 
          .COUT(n106964), .S0(n45[1]), .S1(n45[2]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_2399_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_2399_add_4_3.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_2399_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n106963), .S1(n45[0]));   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(71[14:24])
    defparam cnt_2399_add_4_1.INIT0 = 16'hF000;
    defparam cnt_2399_add_4_1.INIT1 = 16'h0555;
    defparam cnt_2399_add_4_1.INJECT1_0 = "NO";
    defparam cnt_2399_add_4_1.INJECT1_1 = "NO";
    LUT4 i3857_3_lut_4_lut (.A(cnt_write[3]), .B(n111218), .C(cnt_write[4]), 
         .D(cnt_write[5]), .Z(n320[5])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3857_3_lut_4_lut.init = 16'h7f80;
    LUT4 i2_2_lut (.A(cnt_write[2]), .B(cnt_write[3]), .Z(n7_adj_2319)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2_2_lut.init = 16'heeee;
    LUT4 i2_3_lut_rep_1158 (.A(n109309), .B(cnt_write[0]), .C(cnt_write[5]), 
         .Z(n111216)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i2_3_lut_rep_1158.init = 16'h4040;
    LUT4 i1_2_lut_4_lut (.A(n109309), .B(cnt_write[0]), .C(cnt_write[5]), 
         .D(n111246), .Z(clk_40khz_enable_9)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ;
    defparam i1_2_lut_4_lut.init = 16'hff40;
    LUT4 i15352_2_lut_4_lut (.A(n109309), .B(cnt_write[0]), .C(cnt_write[5]), 
         .D(n111246), .Z(n22862)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i15352_2_lut_4_lut.init = 16'h0040;
    LUT4 i3850_2_lut_3_lut_4_lut (.A(cnt_write[2]), .B(n111252), .C(cnt_write[4]), 
         .D(cnt_write[3]), .Z(n320[4])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3850_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i75788_2_lut_4_lut (.A(n110506), .B(rst_n_c), .C(n110507), .D(n110508), 
         .Z(n7_adj_2270)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(107[37:42])
    defparam i75788_2_lut_4_lut.init = 16'hb7ff;
    LUT4 i2_3_lut_rep_1178 (.A(state[1]), .B(state[0]), .C(rst_n_c), .Z(clk_40khz_enable_29)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam i2_3_lut_rep_1178.init = 16'h4040;
    LUT4 i15363_2_lut_4_lut (.A(state[1]), .B(state[0]), .C(rst_n_c), 
         .D(cnt_main[0]), .Z(n22868)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam i15363_2_lut_4_lut.init = 16'h0040;
    LUT4 i15357_2_lut_4_lut (.A(state[1]), .B(state[0]), .C(rst_n_c), 
         .D(cnt_main[0]), .Z(n22865)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(92[11] 161[5])
    defparam i15357_2_lut_4_lut.init = 16'h4000;
    LUT4 state_2__I_0_i5_2_lut_rep_1188 (.A(state[0]), .B(state[1]), .Z(n111246)) /* synthesis lut_function=(A+!(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam state_2__I_0_i5_2_lut_rep_1188.init = 16'hbbbb;
    LUT4 i1_4_lut_4_lut (.A(state[0]), .B(state[1]), .C(cnt_write[5]), 
         .D(cnt_write[0]), .Z(clk_40khz_enable_4)) /* synthesis lut_function=(!(A+(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i1_4_lut_4_lut.init = 16'h1115;
    LUT4 i75459_2_lut_3_lut (.A(state[0]), .B(state[1]), .C(seg_din_N_2238), 
         .Z(seg_din_N_2237)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i75459_2_lut_3_lut.init = 16'h4040;
    LUT4 i101793_2_lut_3_lut (.A(state[0]), .B(state[1]), .C(cnt_write[0]), 
         .Z(seg_rck_N_2232)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i101793_2_lut_3_lut.init = 16'h0404;
    LUT4 i75413_2_lut_3_lut (.A(state[0]), .B(state[1]), .C(cnt_write[0]), 
         .Z(seg_sck_N_2235)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i75413_2_lut_3_lut.init = 16'h4040;
    LUT4 i101775_3_lut_3_lut (.A(state[0]), .B(state[1]), .C(cnt_write[5]), 
         .Z(clk_40khz_enable_24)) /* synthesis lut_function=(!(A+(B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i101775_3_lut_3_lut.init = 16'h1515;
    LUT4 i101851_4_lut_4_lut (.A(state[0]), .B(state[1]), .C(cnt_write[5]), 
         .D(n109311), .Z(n22858)) /* synthesis lut_function=(!(A+!((C (D))+!B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i101851_4_lut_4_lut.init = 16'h5111;
    LUT4 i1_4_lut_4_lut_adj_192 (.A(state[0]), .B(state[1]), .C(n8_adj_2320), 
         .D(n7_adj_2319), .Z(clk_40khz_enable_5)) /* synthesis lut_function=(!(A+(B (C+(D))))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(116[4:9])
    defparam i1_4_lut_4_lut_adj_192.init = 16'h1115;
    LUT4 i3831_2_lut_rep_1194 (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n111252)) /* synthesis lut_function=(A (B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3831_2_lut_rep_1194.init = 16'h8888;
    LUT4 i3838_2_lut_rep_1160_3_lut (.A(cnt_write[1]), .B(cnt_write[0]), 
         .C(cnt_write[2]), .Z(n111218)) /* synthesis lut_function=(A (B (C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3838_2_lut_rep_1160_3_lut.init = 16'h8080;
    LUT4 i3836_2_lut_3_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[2]), 
         .Z(n320[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3836_2_lut_3_lut.init = 16'h7878;
    LUT4 i3843_2_lut_3_lut_4_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[3]), 
         .D(cnt_write[2]), .Z(n320[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3843_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i10471_2_lut_rep_1199 (.A(cnt_main[1]), .B(cnt_main[2]), .Z(n111257)) /* synthesis lut_function=(A+!(B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i10471_2_lut_rep_1199.init = 16'hbbbb;
    LUT4 i15362_1_lut_2_lut (.A(cnt_main[1]), .B(cnt_main[2]), .Z(n22872)) /* synthesis lut_function=(!(A+!(B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i15362_1_lut_2_lut.init = 16'h4444;
    LUT4 i3_3_lut (.A(cnt_write[1]), .B(cnt_write[4]), .C(cnt_write[5]), 
         .Z(n8_adj_2320)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i3_3_lut.init = 16'hefef;
    LUT4 i101810_2_lut (.A(cnt_main[1]), .B(cnt_main[2]), .Z(n17506)) /* synthesis lut_function=((B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i101810_2_lut.init = 16'hdddd;
    LUT4 i75778_2_lut_4_lut (.A(bcd_code_31__N_2138), .B(rst_n_c), .C(n110591), 
         .D(n110592), .Z(n7_adj_2317)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(112[37:42])
    defparam i75778_2_lut_4_lut.init = 16'hb7ff;
    LUT4 i75818_2_lut_4_lut (.A(n110524), .B(rst_n_c), .C(n110515), .D(n110514), 
         .Z(n7_adj_2279)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(108[37:42])
    defparam i75818_2_lut_4_lut.init = 16'hb7ff;
    LUT4 mux_25_Mux_3_i7_4_lut_4_lut (.A(n110513), .B(n110503), .C(n110504), 
         .D(n110505), .Z(n7_adj_2272)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(108[37:42])
    defparam mux_25_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    LUT4 mux_27_Mux_3_i7_4_lut_4_lut (.A(n110523), .B(n110522), .C(n110521), 
         .D(n110520), .Z(n7_adj_2285)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam mux_27_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    L6MUX21 i101517 (.D0(n109601), .D1(n109602), .SD(cnt_write[3]), .Z(n109605));
    L6MUX21 i101518 (.D0(n109603), .D1(n109604), .SD(cnt_write[3]), .Z(n109606));
    LUT4 i75770_2_lut_4_lut (.A(n110534), .B(rst_n_c), .C(n110535), .D(n110536), 
         .Z(n7_adj_2287)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75770_2_lut_4_lut.init = 16'hb7ff;
    LUT4 mux_33_Mux_3_i7_4_lut_4_lut (.A(n110817), .B(n110581), .C(n110580), 
         .D(n110578), .Z(n7_adj_2315)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(112[37:42])
    defparam mux_33_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    LUT4 i3827_1_lut (.A(cnt_write[0]), .Z(seg_rck_N_2234)) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(118[24:40])
    defparam i3827_1_lut.init = 16'h5555;
    LUT4 i9272_1_lut (.A(cnt_main[0]), .Z(cnt_main_2__N_2207[0])) /* synthesis lut_function=(!(A)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i9272_1_lut.init = 16'h5555;
    LUT4 i75368_2_lut_2_lut_3_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), 
         .C(n110535), .D(n110536), .Z(n14_adj_2286)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75368_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h3bff;
    LUT4 mux_27_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), 
         .C(n110521), .D(n110535), .Z(n7_adj_2283)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(B (C+(D))+!B (C)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam mux_27_Mux_6_i7_3_lut_3_lut_4_lut_4_lut_4_lut.init = 16'h7cf0;
    LUT4 i75725_3_lut_4_lut (.A(n110534), .B(rst_n_c), .C(n110536), .D(n110535), 
         .Z(n14_adj_2282)) /* synthesis lut_function=(((C (D)+!C !(D))+!B)+!A) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75725_3_lut_4_lut.init = 16'hf77f;
    LUT4 i75683_2_lut_3_lut_4_lut_4_lut_4_lut (.A(n110534), .B(rst_n_c), 
         .C(n110536), .D(n110535), .Z(n14_adj_2284)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(109[37:42])
    defparam i75683_2_lut_3_lut_4_lut_4_lut_4_lut.init = 16'hffbf;
    LUT4 i101813_2_lut (.A(cnt_main[1]), .B(cnt_main[2]), .Z(n17522)) /* synthesis lut_function=(!(A (B))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(102[6] 114[13])
    defparam i101813_2_lut.init = 16'h7777;
    PFUMX i101513 (.BLUT(n109593), .ALUT(n109594), .C0(cnt_write[2]), 
          .Z(n109601));
    PFUMX i101514 (.BLUT(n109595), .ALUT(n109596), .C0(cnt_write[2]), 
          .Z(n109602));
    LUT4 i75797_2_lut_4_lut (.A(n110559), .B(rst_n_c), .C(n110545), .D(n110547), 
         .Z(n7_adj_2297)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(B (C (D)))) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(110[37:42])
    defparam i75797_2_lut_4_lut.init = 16'hb7ff;
    PFUMX i101515 (.BLUT(n109597), .ALUT(n109598), .C0(cnt_write[2]), 
          .Z(n109603));
    PFUMX i101516 (.BLUT(n109599), .ALUT(n109600), .C0(cnt_write[2]), 
          .Z(n109604));
    LUT4 mux_29_Mux_3_i7_4_lut_4_lut (.A(n110546), .B(n110533), .C(n110532), 
         .D(n110530), .Z(n7_adj_2295)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // e:/fpgaproject/stepbaseboard/step-mxo2 4.0/lab8_prox_detect/source/segment_scan.v(110[37:42])
    defparam mux_29_Mux_3_i7_4_lut_4_lut.init = 16'hfd0d;
    
endmodule
